5 4 3 2 1

HL4A1/HL5A1 Logic Schematics

D
NM-D272 VER 1.0 D

October.8.2020

1.TITLE PAGE 36.DDR4 SUB CHANNEL-B 71.BLANK 106.DC/DC VCC1R2A(SY8310RAC)

2.BLOCK DIAGRAM 37.N18S-G5(1/6) PEG I/F 72.Smart Card Reader 107.DC/DC VCC2R5A(RT8068A)
3.CPU (1/16): DDI/TYPE-C 38.N18S-G5(2/6)_VRAM I/F 73.GBE JACKSONVILLE 108.DC/DC IMVP8(RT3613EE)
4.CPU (2/16): DDR (1/2) 39.BLANK 74.GBE LAN SWITCH 109.DC/DC VCCCPUCORE (RT9610CGQ)
5.CPU (3/16): DDR (2/2) 40.N18S-G5(3/6)DIGITA / XTAL 75.LAN_B CONNECTOR 110.DC/DC VCCPCHCORE (RT6543)
6.CPU (4/16): MISC/JTAG 41.N18S-G5(4/6) STRAP / GPIO 76.MEDIA CARD CONTROLLER 111.BLANK
7.CPU (5/16): ESPI/SPI/SMBUS/C-LINK 42.N18S-G5(5/6) POWER 77.MEDIA CONNECTOR 112.DC/DC Decoupling Cap
C C

8.CPU (6/16): LPSS/ISH 43.BLANK 78.AUDIO ALC3287 113.BLANK

9.CPU (7/16): AUDIO/SDXC 44.N18S-G5(6/6) GND 79.AUDIO CONNECTOR 114.BLANK
10.CPU (8/16): PCIE/USB/SATA 45.VRAM CHANNEL-A 80.AUDIO JACK SENSE 115.BLANK
11.CPU (9/16): CSI-2/EMMC/CNVI 46.BLANK 81.AUDIO EXT MIC I/F 116.DC/DC VCC1R8_SUS(RT8068A)
12.CPU (10/16): CLOCK SIGNALS 47.BLANK 82.AUDIO SPEAKER 117.DC/DC VCCGFXCORE_D(NCP81278)
13.CPU (11/16): SYSTEM PM 48.BLANK 83.AUDIO BEEP 118.DC/DC VCC1R2VIDEO(MP2941)
14.CPU (12/16): CPU POWER (1/2) 49.BLANK 84.AUDIO DEBUG 119.DC/DC VCC1R8VIDEO_AON(BD9B304)
15.CPU (13/16): CPU POWER (2/2) 50.Load SW VGA 85.EC_NPCE68APA0DX(1/2) 120.DC/DC VCC1R0VIDEO(BD9B304)
16.CPU (14/16): PCH POWER 51.LCD CAMERA/MIC/TOUCH 86.EC_NPCE68APA0DX(2/2) 121.BLANK
17.CPU (15/16): GND 52.LID/CAMERA/MIC/TOUCH INTERFACE 87.BLANK 122.BLANK
18.CPU (16/16): CFG/RESERVED 53.HDMI Re-Timer (PS8409A) 88.KEYBOARD/TRACK POINT 123.LOADSW VCCST&VCCSTG
19.BLANK 54.HDMI CONNECTOR 89.TOUCH PAD/NFC/FPR 124.LOAD SW PCH SUS
B

20.RTC BATTERY 55.BURNSIDE BRIDGE(1/2) 90.FAN CONNECTOR 125.LOAD SW SSD/CR B

21.SPI FLASH 56.BURNSIDE BRIDGE(2/2) 91.APS G-SENSOR 126.LOAD SW LAN

22.BLANK 57.PCIe Re-driver-1 92.THERMAL SENSOR 127.LOAD SW B
23.BLANK 58.PCIe Re-driver-2 93.SMBUS SWITCH 128.LOAD SW WLAN
24.BLANK 59.THUNDERBOLT PD(PTPS65994AD) 94.BLANK 129.PLM BOM
25.BLANK 60.TYPEC_DCIN 95.BLANK
26.BLANK 61.USB TYPE-C RE-DRIVER (BLANK) 96.BLANK
27.BLANK 62.DOCKING CONNECTOR 97.SATA Re-driver
28.BLANK 63.TYPE-C CONNECTOR 98.DISCRETE TPM 2.0
29.BLANK 64.M.2 SOCKET 3 MODULE I/F 99.SCREW HOLES
30.BLANK 65.BLANK 100.DC-IN
31.BLANK 66.WLAN 101.BATTERY INPUT
A 32.BLANK 67.M.2 SOCKET 102.BATTERY CHARGER(BQ25700A) A

33.DDR4 SUB CHANNEL-A 68.DDI DEMULTIPLEXER 103.DC/DC VCC5M (LV6228C)

34.DDR4 SUB CHANNEL-A 69.USB TYPE-A CONNECTOR 104.DC/DC +5VTPC(LV6228C)
35.DDR4 SUB CHANNEL-B 70.USB TYPE-A CONN 105.DC/DC VCC3M (SYX198B)
Security Classification LC Future Center Secret Data Title
Issued Date 2018/01/12 Deciphered Date 2018/01/12 TITLE PAGE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 1 of 130

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 5 4 3 2 1

LCD
14" FHD IPS/HD DDI-A x4
DDR4
Odin/Thor Gen2 Block Diagram
15" FHD IPS/HD(p51) DDR4 SO-DIMM
CPU 3200MHZ 4GB,8GB,16GB,32GB(max)
(p33.35)
Project Code: HL4A0/HL5A0
HDMI 2.0b HDMI Re-t i mer DDI-B x4
HDMI (PS8409A) (p53)
Intel
TCP(2)
D Tiger Lake PECI 3.0 D

USB Type-C Rear Port

TI
TPS65994AD SM Bus SM Bus_B WLAN
Type-C TBT Front Port (p59)
TBT Retimer TCP(1) (p66)
Burnside Bridge(p55)

GBE TBT Type-A M.2 Card

ROM I2C1 Touch Panel
I2C3 NFC
Port 10 USB 2.0
USB 2.0x10 ports (Gen.3)

Port 1
USB 2.0 System Port DCI(Sub board) GPU
Port 2
USB 3.0x4 ports PCI Express Max 6 ports
(NVIDIA) GDDR6 2GB
Port 3 (p45)
Port 12 Port 9 (N18S-LP)
Port 1 (Gen.3) (Gen.3) (p37)
Port 4 USB 3.0 System Port(on SUB/B) Port 5
Finger Printer SPI Flash SATA Port 5
Port 2 16MB(p21) Gen.3
Port 5 USB 3.0 System Port(AOU) Media Intel Port 11
SMART Card Card GbE PHY
Port 3
Port 6 Controller JACKSONVILLE
BT SPI
C Port 4 SPI Flash (RTS5232S) ULT (p73) 2.5" SATA M.2 Sub Card C
Port 7 32MB(p21) (p76) HDD
CAMERA
Port 8 HDA
USB 2.0 TYPE-C(TBT) RJ 45 Docking
TPM 2.0
Port 9 (p98)
USB 2.0 System Port(AOU)
Port 10 Micro SD M.2 SSD
USB 2.0 TYPE-C Card Slot
RTC Battery RJ 45
eSPI
USB 2.0 Port 1
USB 3.0 Port 1 FAN

Audio Sub Board I2C-CHARGE

PECI 3.0
I2C-BAT/BC
Embedded I2C-BAT
LED LOGO/CHG
G-Sensor Controller
NPCE68BPA0DX Battery
HDA CODEC T-Sensor
(ALC3287) (p85) 8K EEPROM Battery
PWRSW
49 Charger
Microphone
Headphone PS2
DRV/SENSE (BQ25700A)
B Keyboard B
Stereo Internal I2C3_NFC SM Bus
Speaker Mic
VINT20 from USB Type-C Rear Port
Track Point (p102) DC/DC
Converter
NFC ClickPad

External Connector/Socket
Camera(USB2.0 Port 7)
RGB + IR Camera(Optional) Internal Connector/Socket
USB 2.0 Non Camera Sub card Internal Mic
Touch FPR Port 8 Internal Switch

Power SW Sub card PWRSW

LED
ThinkPad Logo LED
Touch Panel(Optional) I2C2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/01/12 Deciphered Date BLOCK DIAGRAM
2018/01/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 2 of 130

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 5 4 3 2 1

[7,8,10,12,13,33,34,35,36,37,51,52,53,55,63,64,66,70,73,76,78,85,88,89,91,92,93,97,98,101,127] VCC3B VCC3B

[6,7,8,10,13,16,21,37,40,50,51,72,93,98,117,123,124] VCC3_SUS VCC3_SUS

UCPU1A

1 OF 21

AC2 AY2
DDIA_TXP_3 TCP0_TXRX_P1
AC1 AY1
DDIA_TXN_3 TCP0_TXRX_N1
AD2 BB1
DDIA_TXP_2 TCP0_TXRX_P0
AD1 BB2
EDP_TXP1 DDIA_TXN_2 TCP0_TXRX_N0
[51] EDP_TXP1 AF1 AM5
EDP_TXN1 DDIA_TXP_1 TCP0_TX_P1
[51] EDP_TXN1 AF2 AM7
EDP_TXP0 DDIA_TXN_1 TCP0_TX_N1
eDP [51] EDP_TXP0 EDP_TXN0
AG2
DDIA_TXP_0 TCP0_TX_P0
AT7
[51] EDP_TXN0 AG1 AT5
DDIA_TXN_0 TCP0_TX_N0
AP7
D
EDP_AUXP TCP0_AUX_P D
[51] EDP_AUXP AJ2 AP5
EDP_AUXN DDIA_AUX_P TCP0_AUX
[51] EDP_AUXN AJ1
DDIA_AUX TCP1_RX1_DP
AT2 TCP1_RX1_DP [55]
AUX_PBIAS TCP1_TXRX_P1 TCP1_RX1_DN
[63] AUX_PBIAS DN4 AT1 TCP1_RX1_DN [55]
AUX_NBIAS GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 TCP1_RX0_DP
[63] AUX_NBIAS DT6 AU1 TCP1_RX0_DP [55]
GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 TCP1_RX0_DN
AU2 TCP1_RX0_DN [55]
EDP_HPD TCP1_TXRX_N0 TCP1_TX1_DP
[51] EDP_HPD DR5 AD5 TCP1_TX1_DP [55]
GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1 TCP1_TX1_DN
DDIB_3P TCP1_TX_N1
AD7
TCP1_TX0_DP
TCP1_TX1_DN [55] CS18 DOCK port
[53] DDIB_3P T12 AH7 TCP1_TX0_DP [55]
DDIB_3N DDIB_TXP_3 TCP1_TX_P0 TCP1_TX0_DN
[53] DDIB_3N T11 AH5 TCP1_TX0_DN [55]
DDIB_2P DDIB_TXN_3 TCP1_TX_N0 TCP1_AUX_DP
[53] DDIB_2P Y11 AF7 TCP1_AUX_DP [55]
DDIB_2N DDIB_TXP_2 TCP1_AUX_P TCP1_AUX_DN
[53] DDIB_2N Y9 AF5 TCP1_AUX_DN [55]
DDIB_1P DDIB_TXN_2 TCP1_AUX
HDMI [53] DDIB_1P DDIB_1N
T9
DDIB_TXP_1 TCP2_RX1_DP
[53] DDIB_1N P9 BF1 TCP2_RX1_DP [63]
DDIB_0P DDIB_TXN_1 TCP2_TXRX_P1 TCP2_RX1_DN
[53] DDIB_0P V11 BF2 TCP2_RX1_DN [63]
DDIB_0N DDIB_TXP_0 TCP2_TXRX_N1 TCP2_RX0_DP
[53] DDIB_0N V9 BE2 TCP2_RX0_DP [63]
DDIB_TXN_0 TCP2_TXRX_P0 TCP2_RX0_DN
BE1 TCP2_RX0_DN [63]
TP0302 Test_Point_40MIL 1 DDIB_AUX_P TCP2_TXRX_N0 TCP2_TX1_DP
AB9 BD7 TCP2_TX1_DP [63]
TP0303 Test_Point_40MIL 1 DDIB_AUX_N DDIB_AUX_P TCP2_TX_P1 TCP2_TX1_DN
AD9
DDIB_AUX TCP2_TX_N1
BD5
TCP2_TX0_DP
TCP2_TX1_DN [63] TYPE-C port
AY5 TCP2_TX0_DP [63]
DDIB_CTRLCLK TCP2_TX_P0 TCP2_TX0_DN
[53] DDIB_CTRLCLK DM29 AY7 TCP2_TX0_DN [63]
DDIB_CTRLDATA GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0 TCP2_AUX_DP
[53] DDIB_CTRLDATA DK27 BB5 TCP2_AUX_DP [63]
GPP_H17/DDPB_CTRLDATA TCP2_AUX_P TCP2_AUX_DN
BB7 TCP2_AUX_DN [63]
HDMI_HPD TCP2_AUX
[53] HDMI_HPD DG43
GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD
BK1
TCP3_TXRX_P1
DG47 BK2
GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1
DJ47 BJ2
GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0
BJ1
-DISCRETE_PRESENCE TCP3_TXRX_N0
[8] -DISCRETE_PRESENCE DU8 BM7
GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1
DV8 BM5
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1
BH5
TCP1_LSTX TCP3_TX_P0
[55] TCP1_LSTX DF6 BH7
TCP1_LSRX GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0
To BB [55] TCP1_LSRX DD6
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P
BK5
BK7
TCP3_AUX
DN23
GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# TC_RCOMPP R0301 1 2 1/20W_150_1%_0201
DM23 AN2
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P TC_RCOMPN
AN1
TC_RCOMP
C DK23 C
GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO
DN21 M8
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
DF43 AB1 EDP_COMP R0302 1 2 1/20W_150_1%_0201
GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
DF45
GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK
DF47 CE4
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1
DH52
-USB_PORT4_OC2 DK45 GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
OC2 : non AOU port [70] -USB_PORT4_OC2 GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
PANEL_POWER_ON_CPU DM8
VGA_BLON EDP_VDDEN
[85] VGA_BLON DN8
PANEL_BKLT_CTRL_CPU EDP_BKLTEN
[51] PANEL_BKLT_CTRL_CPU DG10
EDP_BKLTCTL
2

TGLLAKE-U_BGA1449
R0303
1/20W_100K_5%_0201 @
1

B B

VCC3_SUS VCC3B

1 2 DDIB_CTRLCLK

R0305
1/20W_2.2K_5%_0201

1 2 -USB_PORT4_OC2 1 2 DDIB_CTRLDATA

R0306 R0307
1/20W_10K_5%_0201 1/20W_2.2K_5%_0201

LCD_Self_test
PANEL_POWER_ON_CPU D0301 2 1 RB520CM-30T2R_VMN2M2 PANEL_POWER_ON
PANEL_POWER_ON [51]
A A
LCD_SELF_TEST_ON D0302 2 1 RB520CM-30T2R_VMN2M2
[51,85] LCD_SELF_TEST_ON
1

R0308
1/20W_100K_5%_0201
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 TGL(A)_DDI/eDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 3 of 130

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 5 4 3 2 1

[5,14,15,33,34,35,36,106] VCC1R2A VCC1R2A

DDR4 non interleaved Type

DDR4 CHANNEL 0 UCPU1B
2 OF 21

DDR4/LP4
[35,36]

[13,16,51,52,55,56,59,84,85,86,88,102,103,104,105,106,110,116,118,119,120,123,124,125,126,127,128]
M_A_VREF_CA

VCC3M
M_A_VREF_CA

VCC3M
DDR4 (NIL)/LP4
DDR0_DQ0_7 CP53 BT42 DDR0_CLK1_DP
[35] DDR0_DQ0_[7:0] DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P DDR0_CLK1_DP [35]
DDR0_DQ0_6 CP52 BT41 DDR0_CLK1_DN
DDR0_DQ0_5 DDR0_DQ0_6/DDR0_DQ0_6 DDR0_CLK_N1/DDR3_CLK DDR0_CLK1_DN [35]
CP50 BP52
DDR0_DQ0_4 DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P
CP49 BP53
DDR0_DQ0_4/DDR0_DQ0_4 NC/DDR2_CLK
M-A-DQ0 DDR0_DQ0_3
DDR0_DQ0_2
CU53
DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P
CD42
CU52 CD41
DDR0_DQ0_1 DDR0_DQ0_2/DDR0_DQ0_2 NC/DDR1_CLK DDR0_CLK0_DP
CU50 CC52 DDR0_CLK0_DP [35]
DDR0_DQ0_0 DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P DDR0_CLK0_DN
CU49 CC53 DDR0_CLK0_DN [35]
DDR0_DQ1_7 DDR0_DQ0_0/DDR0_DQ0_0 DDR0_CLK_N0/DDR0_CLK
[35] DDR0_DQ1_[7:0] CH53
D
DDR0_DQ1_6 DDR0_DQ1_7/DDR0_DQ1_7 DDR4/LP4 D
CH52 BT45
DDR0_DQ1_5 DDR0_DQ1_6/DDR0_DQ1_6 NC/DDR3_CKE0
CH50 BT47
DDR0_DQ1_4 DDR0_DQ1_5/DDR0_DQ1_5 NC/DDR3_CKE1
CH49 BN51
DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0
M-A-DQ1 DDR0_DQ1_3
DDR0_DQ1_2
CL53
DDR0_DQ1_3/DDR0_DQ1_3 NC/DDR2_CKE1
BN53
CL52 CD45
DDR0_DQ1_1 DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0
CL50 CD47
DDR0_DQ1_0 DDR0_DQ1_1/DDR0_DQ1_1 NC/DDR1_CKE1
CL49 CA51
DDR0_DQ2_7 DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0
[35] DDR0_DQ2_[7:0] CT47 CA53
DDR0_DQ2_6 DDR0_DQ2_7/DDR1_DQ0_7 NC/DDR0_CKE1
CV47
DDR0_DQ2_5 DDR0_DQ2_6/DDR1_DQ0_6 DDR4/LP4
DDR0_CKE1
CT45 BU52 DDR0_CKE1 [35]
DDR0_DQ2_4 DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4 DDR0_CKE0
CV45 BL50 DDR0_CKE0 [35]
DDR0_DQ2_4/DDR1_DQ0_4 DDR0_CKE0/DDR2_CA5
M-A-DQ2 DDR0_DQ2_3
DDR0_DQ2_2
CT42
DDR0_DQ2_3/DDR1_DQ0_3 DDR4/LP4
DDR0_CS1
CV42 CF42 DDR0_CS1 [35]
DDR0_DQ2_1 DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1 DDR0_CS0
CT41 CF47 DDR0_CS0 [35]
DDR0_DQ2_0 DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC
CV41
DDR0_DQ3_7 DDR0_DQ2_0/DDR1_DQ0_0 DDR4/LP4
[35] DDR0_DQ3_[7:0] CK47 CE53
DDR0_DQ3_6 DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0
CM47 CE50
DDR0_DQ3_5 DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1
CK45 BL53
DDR0_DQ3_4 DDR0_DQ3_5/DDR1_DQ1_5 NC/DDR2_CS0
CM45 BP47
DDR0_DQ3_4/DDR1_DQ1_4 NC/DDR3_CA5
M-A-DQ3 DDR0_DQ3_3
DDR0_DQ3_2
CK42
DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4
BP42
CM42 BP45
DDR0_DQ3_1 DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3
CM41 BP44
DDR0_DQ3_0 DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2
CK41
DDR0_DQ4_7 DDR0_DQ3_0/DDR1_DQ1_0 DDR4 (NIL)/LP4
DDR0_DQS7_DP
[35] DDR0_DQ4_[7:0] BF53 BB44 DDR0_DQS7_DP [35]
DDR0_DQ4_6 DDR0_DQ4_7/DDR2_DQ0_7 DDR0_DQSP_7/DDR3_DQSP_1 DDR0_DQS7_DN
BF52 BD44 DDR0_DQS7_DN [35]
DDR0_DQ4_5 DDR0_DQ4_6/DDR2_DQ0_6 DDR0_DQSN_7/DDR3_DQSN_1 DDR0_DQS6_DP
BF50 BK44 DDR0_DQS6_DP [35]
DDR0_DQ4_4 DDR0_DQ4_5/DDR2_DQ0_5 DDR0_DQSP_6/DDR3_DQSP_0 DDR0_DQS6_DN
BF49 BH44 DDR0_DQS6_DN [35]
DDR0_DQ4_4/DDR2_DQ0_4 DDR0_DQSN_6/DDR3_DQSN_0
M-A-DQ4 DDR0_DQ4_3
DDR0_DQ4_2
BH53
DDR0_DQ4_3/DDR2_DQ0_3 DDR0_DQSP_5/DDR2_DQSP_1
BA51 DDR0_DQS5_DP
DDR0_DQS5_DN
DDR0_DQS5_DP [35]
BH52 BA50 DDR0_DQS5_DN [35]
DDR0_DQ4_1 DDR0_DQ4_2/DDR2_DQ0_2 DDR0_DQSN_5/DDR2_DQSN_1 DDR0_DQS4_DP
BH50 BG51 DDR0_DQS4_DP [35]
DDR0_DQ4_0 DDR0_DQ4_1/DDR2_DQ0_1 DDR0_DQSP_4/DDR2_DQSP_0 DDR0_DQS4_DN
BH49 BG50 DDR0_DQS4_DN [35]
DDR0_DQ5_7 DDR0_DQ4_0/DDR2_DQ0_0 DDR0_DQSN_4/DDR2_DQSN_0 DDR0_DQS3_DP
[35] DDR0_DQ5_[7:0] AY53 CK44 DDR0_DQS3_DP [35]
DDR0_DQ5_6 DDR0_DQ5_7/DDR2_DQ1_7 DDR0_DQSP_3/DDR1_DQSP_1 DDR0_DQS3_DN
AY52 CM44 DDR0_DQS3_DN [35]
DDR0_DQ5_5 DDR0_DQ5_6/DDR2_DQ1_6 DDR0_DQSN_3/DDR1_DQSN_1 DDR0_DQS2_DP
AY50 CT44 DDR0_DQS2_DP [35]
DDR0_DQ5_4 DDR0_DQ5_5/DDR2_DQ1_5 DDR0_DQSP_2/DDR1_DQSP_0 DDR0_DQS2_DN
AY49 CV44 DDR0_DQS2_DN [35]
DDR0_DQ5_4/DDR2_DQ1_4 DDR0_DQSN_2/DDR1_DQSN_0
M-A-DQ5 DDR0_DQ5_3
DDR0_DQ5_2
BC53
DDR0_DQ5_3/DDR2_DQ1_3 DDR0_DQSP_1/DDR0_DQSP_1
CK51 DDR0_DQS1_DP
DDR0_DQS1_DN
DDR0_DQS1_DP [35]
BC52 CK50 DDR0_DQS1_DN [35]
DDR0_DQ5_1 DDR0_DQ5_2/DDR2_DQ1_2 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQS0_DP
C BC50 CR51 DDR0_DQS0_DP [35] C
DDR0_DQ5_0 DDR0_DQ5_1/DDR2_DQ1_1 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQS0_DN
BC49 CR50 DDR0_DQS0_DN [35]
DDR0_DQ6_7 DDR0_DQ5_0/DDR2_DQ1_0 DDR0_DQSN_0/DDR0_DQSN_0
[35] DDR0_DQ6_[7:0] BK47 DDR4/LP4
DDR0_DQ6_6 DDR0_DQ6_7/DDR3_DQ0_7 DDR0_ODT1
BK45 CF44 DDR0_ODT1 [35]
DDR0_DQ6_5 DDR0_DQ6_6/DDR3_DQ0_6 DDR0_ODT1/DDR1_CA0 DDR0_ODT0
BH47 CF45 DDR0_ODT0 [35]
DDR0_DQ6_4 DDR0_DQ6_5/DDR3_DQ0_5 DDR0_ODT0/DDR1_CS0
BH45 DDR4/LP4
DDR0_DQ6_4/DDR3_DQ0_4
M-A-DQ6 DDR0_DQ6_3
DDR0_DQ6_2
BH42
DDR0_DQ6_3/DDR3_DQ0_3 DDR0_MA16/DDR1_CA4
CB47 DDR0_MA16
DDR0_MA15
DDR0_MA16 [35]
BK42 CB44 DDR0_MA15 [35]
DDR0_DQ6_1 DDR0_DQ6_2/DDR3_DQ0_2 DDR0_MA15/DDR1_CA3 DDR0_MA14
BK41 CB45 DDR0_MA14 [35]
DDR0_DQ6_0 DDR0_DQ6_1/DDR3_DQ0_1 DDR0_MA14/DDR1_CA2 DDR0_MA13
BH41 CF41 DDR0_MA13 [35]
DDR0_DQ7_7 DDR0_DQ6_0/DDR3_DQ0_0 DDR0_MA13/DDR1_CS1 DDR0_MA12
[35] DDR0_DQ7_[7:0] BD47 BU53 DDR0_MA12 [35]
DDR0_DQ7_6 DDR0_DQ7_7/DDR3_DQ1_7 DDR0_MA12/DDR2_CA1 DDR0_MA11
BB47 BT51 DDR0_MA11 [35]
DDR0_DQ7_5 DDR0_DQ7_6/DDR3_DQ1_6 DDR0_MA11/NC DDR0_MA10
BD45 BV42 DDR0_MA10 [35]
DDR0_DQ7_4 DDR0_DQ7_5/DDR3_DQ1_5 DDR0_MA10/DDR3_CA1 DDR0_MA9
BB45 BU50 DDR0_MA9 [35] TABLE of (Q0401)
DDR0_DQ7_4/DDR3_DQ1_4 DDR0_MA9/DDR2_CA0
M-A-DQ7 DDR0_DQ7_3
DDR0_DQ7_2
BB42
DDR0_DQ7_3/DDR3_DQ1_3 DDR0_MA8/DDR0_CA2
BY53 DDR0_MA8
DDR0_MA7
DDR0_MA8 [35]
BB41 CA50 DDR0_MA7 [35] Vendor LCFC P/N Description
DDR0_DQ7_1 DDR0_DQ7_2/DDR3_DQ1_2 DDR0_MA7/DDR0_CA4 DDR0_MA6
BD42 BY52 DDR0_MA6 [35]
DDR0_DQ7_0 DDR0_DQ7_1/DDR3_DQ1_1 DDR0_MA6/DDR0_CA3 DDR0_MA5
BD41 BY50 DDR0_MA5 [35] ROHM SB00000WC0J S TR DTC015TMT2L NPN VMT3
DDR0_DQ7_0/DDR3_DQ1_0 DDR0_MA5/DDR0_CA5 DDR0_MA4
CD51 DDR0_MA4 [35]
DDR0_MA4/DDR0_CS0 DDR0_MA3
CD53 DDR0_MA3 [35] TOSHIBA SB000010700 S TR RN1131MFV NPN VESM
DDR0_MA3/DDR0_CS1 DDR0_MA2
BV47 DDR0_MA2 [35]
DDR0_MA2/DDR3_CS0 DDR0_MA1
CE52 SB000013J00
DDR0_MA1/NC
BV41 DDR0_MA0 DDR0_MA1 [35] ON S TR DTC115TM3T5G NPN SOT-723-
DDR0_MA0/NC DDR0_MA0 [35]
DDR4/LP4
BN50 DDR0_BG1
DDR0_BG1/DDR2_CA2 DDR0_BG1 [35]
BL52 DDR0_BG0
DDR0_BG0/DDR2_CA3 DDR0_BG0 [35]
DDR4/LP4
CB42 DDR0_BA1 VCC3M
DDR0_BA1/DDR1_CA5 DDR0_BA0 DDR0_BA1 [35]
BV44 DDR0_BA0 [35]
DDR0_BA0/DDR3_CA0
DDR4/LP4
BT53 DDR0_ACT_N
DDR0_ACT#/DDR2_CS1 DDR0_ACT_N [35]

2
DDR4/LP4 DDR0_PARITY
BV45 DDR0_PARITY [35]
DDR0_PAR/DDR3_CS1 R0401
DDR4 DDR0_ALERT_N 1/20W_100K_5%_0201
AU50 DDR0_ALERT_N [35]
DDR0_ALERT# DDR0_VREF_CA
AU49
DDR0_VREF_CA

1
E52 DDR_VTT_PG_CTRL_R
B DDR_VTT_CTL -DRAMRST_R B
DV47
DRAM_RESET# DDR_COMP DDR_VTT_PG_CTRL
C49 DDR_VTT_PG_CTRL [106]
DDR_RCOMP VCC1R2A

1
TGLLAKE-U_BGA1449
R0402
@ 1/20W_100_1%_0201 2 Q0401

DTC015TMT2L_VMT3

3
VCC1R2A M_A_VREF_CA

2
R0409
2

VCC1R2A @ 1/20W_10K_5%_0201
R0403
1/20W_1K_1%_0201

1
2
1

R0407
DDR0_VREF_CA 1 2 1/20W_470_1%_0201

R0404
1

1/20W_2_1%_0201 -DRAMRST_R R0408 1 2 0_0201_SP

-DRAMRST [33,35]
2
C0401
0.022U_6.3V_K_X5R_0201
2

1 R0406
1/20W_1K_1%_0201
1
2

R0405
1/20W_24.9_1%_0201
A A
1

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 TGL(B)_DDR4 CH.A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 4 of 130

5 4 3 2 1
 5 4 3 2 1

[33,34] M_B_VREF_CA M_B_VREF_CA

DDR4 CHANNEL 1 [4,14,15,33,34,35,36,106] VCC1R2A VCC1R2A

UCPU1C
3 OF 21

DDR4 (NIL)/LP4 DDR4/LP4

DDR1_DQ0_7 AL53 R41 DDR1_CLK1_DP
[33] DDR1_DQ0_[7:0] DDR1_DQ0_7/DDR4_DQ0_7 DDR1_CLK_P1/DDR7_CLK_P DDR1_CLK1_DP [33]
DDR1_DQ0_6 AL52 R42 DDR1_CLK1_DN
D DDR1_DQ0_6/DDR4_DQ0_6 DDR1_CLK_N1/DDR7_CLK DDR1_CLK1_DN [33] D
DDR1_DQ0_5 AL50 M52
DDR1_DQ0_4 DDR1_DQ0_5/DDR4_DQ0_5 NC/DDR6_CLK_P
AL49 M53
DDR1_DQ0_4/DDR4_DQ0_4 NC/DDR6_CLK
M-B-DQ0 DDR1_DQ0_3
DDR1_DQ0_2
AP53
DDR1_DQ0_3/DDR4_DQ0_3 NC/DDR5_CLK_P
AC42
AP52 AC41
DDR1_DQ0_1 DDR1_DQ0_2/DDR4_DQ0_2 NC/DDR5_CLK DDR1_CLK0_DP
AP50 Y52 DDR1_CLK0_DP [33]
DDR1_DQ0_0 DDR1_DQ0_1/DDR4_DQ0_1 DDR1_CLK_P0/DDR4_CLK_P DDR1_CLK0_DN
AP49 Y53 DDR1_CLK0_DN [33]
DDR1_DQ1_7 DDR1_DQ0_0/DDR4_DQ0_0 DDR1_CLK_N0/DDR4_CLK
[33] DDR1_DQ1_[7:0] AF53
DDR1_DQ1_6 DDR1_DQ1_7/DDR4_DQ1_7 DDR4/LP4
AF52 R47
DDR1_DQ1_5 DDR1_DQ1_6/DDR4_DQ1_6 NC/DDR7_CKE0
AF50 R45
DDR1_DQ1_4 DDR1_DQ1_5/DDR4_DQ1_5 NC/DDR7_CKE1
AF49 K51
DDR1_DQ1_4/DDR4_DQ1_4 NC/DDR6_CKE0
M-B-DQ1 DDR1_DQ1_3
DDR1_DQ1_2
AH53
DDR1_DQ1_3/DDR4_DQ1_3 NC/DDR6_CKE1
K53
AH52 AC47
DDR1_DQ1_1 DDR1_DQ1_2/DDR4_DQ1_2 NC/DDR5_CKE0
AH50 AC45
DDR1_DQ1_0 DDR1_DQ1_1/DDR4_DQ1_1 NC/DDR5_CKE1
AH49 W51
DDR1_DQ2_7 DDR1_DQ1_0/DDR4_DQ1_0 NC/DDR4_CKE0
[33] DDR1_DQ2_[7:0] AR41 W53
DDR1_DQ2_6 DDR1_DQ2_7/DDR5_DQ0_7 NC/DDR4_CKE1
AV42 DDR4/LP4
DDR1_DQ2_5 DDR1_DQ2_6/DDR5_DQ0_6 DDR1_CKE1
AR42 P52 DDR1_CKE1 [33]
DDR1_DQ2_4 DDR1_DQ2_5/DDR5_DQ0_5 DDR1_CKE1/DDR6_CA4 DDR1_CKE0
AV41 J50 DDR1_CKE0 [33]
DDR1_DQ2_4/DDR5_DQ0_4 DDR1_CKE0/DDR6_CA5
M-B-DQ2 DDR1_DQ2_3
DDR1_DQ2_2
AR45
DDR1_DQ2_3/DDR5_DQ0_3 DDR4/LP4 DDR1_CS1
AV45 AE42 DDR1_CS1 [33]
DDR1_DQ2_1 DDR1_DQ2_2/DDR5_DQ0_2 DDR1_CS1/DDR5_CA1 DDR1_CS0
AR47 AE47 DDR1_CS0 [33]
DDR1_DQ2_0 DDR1_DQ2_1/DDR5_DQ0_1 DDR1_CS0/NC
AV47
DDR1_DQ3_7 DDR1_DQ2_0/DDR5_DQ0_0 DDR4/LP4
[33] DDR1_DQ3_[7:0] AJ41 N42
DDR1_DQ3_6 DDR1_DQ3_7/DDR5_DQ1_7 NC/DDR7_CA5
AJ42 N45
DDR1_DQ3_5 DDR1_DQ3_6/DDR5_DQ1_6 NC/DDR7_CA4
AL41 N44
DDR1_DQ3_4 DDR1_DQ3_5/DDR5_DQ1_5 NC/DDR7_CA3
AL42 N47
DDR1_DQ3_4/DDR5_DQ1_4 NC/DDR7_CA2
M-B-DQ3 DDR1_DQ3_3
DDR1_DQ3_2
AJ45
DDR1_DQ3_3/DDR5_DQ1_3 NC/DDR6_CS0
J53
AJ47 AC50
DDR1_DQ3_1 DDR1_DQ3_2/DDR5_DQ1_2 NC/DDR4_CA1
AL45 AC53
DDR1_DQ3_0 DDR1_DQ3_1/DDR5_DQ1_1 NC/DDR4_CA0
C AL47 C
DDR1_DQ4_7 DDR1_DQ3_0/DDR5_DQ1_0 DDR4 (NIL)/LP4
DDR1_DQS7_DP
[33] DDR1_DQ4_[7:0] A43 K36 DDR1_DQS7_DP [33]
DDR1_DQ4_6 DDR1_DQ4_7/DDR6_DQ0_7 DDR1_DQSP_7/DDR7_DQSP_1 DDR1_DQS7_DN
B43 K38 DDR1_DQS7_DN [33]
DDR1_DQ4_5 DDR1_DQ4_6/DDR6_DQ0_6 DDR1_DQSN_7/DDR7_DQSN_1 DDR1_DQS6_DP
D43 G44 DDR1_DQS6_DP [33]
DDR1_DQ4_4 DDR1_DQ4_5/DDR6_DQ0_5 DDR1_DQSP_6/DDR7_DQSP_0 DDR1_DQS6_DN
E44 J44 DDR1_DQS6_DN [33]
DDR1_DQ4_4/DDR6_DQ0_4 DDR1_DQSN_6/DDR7_DQSN_0
M-B-DQ4 DDR1_DQ4_3
DDR1_DQ4_2
A46
DDR1_DQ4_3/DDR6_DQ0_3 DDR1_DQSP_5/DDR6_DQSP_1
D39 DDR1_DQS5_DP
DDR1_DQS5_DN
DDR1_DQS5_DP [33]
B46 C39 DDR1_DQS5_DN [33]
DDR1_DQ4_1 DDR1_DQ4_2/DDR6_DQ0_2 DDR1_DQSN_5/DDR6_DQSN_1 DDR1_DQS4_DP
D46 C45 DDR1_DQS4_DP [33]
DDR1_DQ4_0 DDR1_DQ4_1/DDR6_DQ0_1 DDR1_DQSP_4/DDR6_DQSP_0 DDR1_DQS4_DN
E47 D45 DDR1_DQS4_DN [33]
DDR1_DQ5_7 DDR1_DQ4_0/DDR6_DQ0_0 DDR1_DQSN_4/DDR6_DQSN_0 DDR1_DQS3_DP
[33] DDR1_DQ5_[7:0] E38 AJ44 DDR1_DQS3_DP [33]
DDR1_DQ5_6 DDR1_DQ5_7/DDR6_DQ1_7 DDR1_DQSP_3/DDR5_DQSP_1 DDR1_DQS3_DN
D38 AL44 DDR1_DQS3_DN [33]
DDR1_DQ5_5 DDR1_DQ5_6/DDR6_DQ1_6 DDR1_DQSN_3/DDR5_DQSN_1 DDR1_DQS2_DP
B38 AV44 DDR1_DQS2_DP [33]
DDR1_DQ5_4 DDR1_DQ5_5/DDR6_DQ1_5 DDR1_DQSP_2/DDR5_DQSP_0 DDR1_DQS2_DN
A38 AR44 DDR1_DQS2_DN [33]
DDR1_DQ5_4/DDR6_DQ1_4 DDR1_DQSN_2/DDR5_DQSN_0
M-B-DQ5 DDR1_DQ5_3
DDR1_DQ5_2
E41
DDR1_DQ5_3/DDR6_DQ1_3 DDR1_DQSP_1/DDR4_DQSP_1
AG51 DDR1_DQS1_DP
DDR1_DQS1_DN
DDR1_DQS1_DP [33]
D40 AG50 DDR1_DQS1_DN [33]
DDR1_DQ5_1 DDR1_DQ5_2/DDR6_DQ1_2 DDR1_DQSN_1/DDR4_DQSN_1 DDR1_DQS0_DP
B40 AN51 DDR1_DQS0_DP [33]
DDR1_DQ5_0 DDR1_DQ5_1/DDR6_DQ1_1 DDR1_DQSP_0/DDR4_DQSP_0 DDR1_DQS0_DN
A40 AN50 DDR1_DQS0_DN [33]
DDR1_DQ6_7 DDR1_DQ5_0/DDR6_DQ1_0 DDR1_DQSN_0/DDR4_DQSN_0
[33] DDR1_DQ6_[7:0] G42
DDR1_DQ6_6 DDR1_DQ6_7/DDR7_DQ0_7 DDR4/LP4 DDR1_ODT1
G41 AE44 DDR1_ODT1 [33]
DDR1_DQ6_5 DDR1_DQ6_6/DDR7_DQ0_6 DDR1_ODT1/DDR5_CA0 DDR1_ODT0
J41 AE45 DDR1_ODT0 [33]
DDR1_DQ6_4 DDR1_DQ6_5/DDR7_DQ0_5 DDR1_ODT0/DDR5_CS0
J42
DDR1_DQ6_4/DDR7_DQ0_4 DDR4/LP4
M-B-DQ6 DDR1_DQ6_3
DDR1_DQ6_2
G45
DDR1_DQ6_3/DDR7_DQ0_3 DDR1_MA16/DDR5_CA4
AA47 DDR1_MA16
DDR1_MA15
DDR1_MA16 [33]
J45 AA44 DDR1_MA15 [33]
DDR1_DQ6_1 DDR1_DQ6_2/DDR7_DQ0_2 DDR1_MA15/DDR5_CA3 DDR1_MA14
G47 AA45 DDR1_MA14 [33]
DDR1_DQ6_0 DDR1_DQ6_1/DDR7_DQ0_1 DDR1_MA14/DDR5_CA2 DDR1_MA13
J47 AE41 DDR1_MA13 [33]
DDR1_DQ7_7 DDR1_DQ6_0/DDR7_DQ0_0 DDR1_MA13/DDR5_CS1 DDR1_MA12
[33] DDR1_DQ7_[7:0] G38 P53 DDR1_MA12 [33]
DDR1_DQ7_6 DDR1_DQ7_7/DDR7_DQ1_7 DDR1_MA12/DDR6_CA1 DDR1_MA11
G36 N51 DDR1_MA11 [33]
DDR1_DQ7_5 DDR1_DQ7_6/DDR7_DQ1_6 DDR1_MA11/NC DDR1_MA10
H36 U42 DDR1_MA10 [33]
DDR1_DQ7_4 DDR1_DQ7_5/DDR7_DQ1_5 DDR1_MA10/DDR7_CA1 DDR1_MA9
H38 P50 DDR1_MA9 [33]
DDR1_DQ7_4/DDR7_DQ1_4 DDR1_MA9/DDR6_CA0
B
M-B-DQ7 DDR1_DQ7_3
DDR1_DQ7_2
N36
DDR1_DQ7_3/DDR7_DQ1_3 DDR1_MA8/DDR4_CA2
U53 DDR1_MA8
DDR1_MA7
DDR1_MA8 [33] B
L36 W50 DDR1_MA7 [33]
DDR1_DQ7_1 DDR1_DQ7_2/DDR7_DQ1_2 DDR1_MA7/DDR4_CA4 DDR1_MA6
L38 U52 DDR1_MA6 [33]
DDR1_DQ7_0 DDR1_DQ7_1/DDR7_DQ1_1 DDR1_MA6/DDR4_CA3 DDR1_MA5
N38 U50 DDR1_MA5 [33]
DDR1_DQ7_0/DDR7_DQ1_0 DDR1_MA5/DDR4_CA5 DDR1_MA4
AA51 DDR1_MA4 [33]
DDR1_MA4/DDR4_CS0 DDR1_MA3
AA53 DDR1_MA3 [33]
DDR1_MA3/DDR4_CS1 DDR1_MA2
U47 DDR1_MA2 [33]
DDR1_MA2/DDR7_CS0 DDR1_MA1
AC52 DDR1_MA1 [33]
DDR1_MA1/NC DDR1_MA0
U41 DDR1_MA0 [33]
DDR1_MA0/NC
DDR4/LP4 DDR1_BG1
K50 DDR1_BG1 [33]
DDR1_BG1/DDR6_CA2 DDR1_BG0
J52 DDR1_BG0 [33]
VCC1R2A M_B_VREF_CA DDR1_BG0/DDR6_CA3
DDR4/LP4 DDR1_BA1
AA42 DDR1_BA1 [33]
DDR1_BA1/DDR5_CA5 DDR1_BA0
U44 DDR1_BA0 [33]
DDR1_BA0/DDR7_CA0
2

N53 DDR1_ACT_N
DDR1_ACT#/DDR6_CS1 DDR1_ACT_N [33]
R0501
1/20W_1K_1%_0201 U45 DDR1_PARITY
DDR1_PAR/DDR7_CS1 DDR1_PARITY [33]
AU53 DDR1_ALERT_N
DDR1_ALERT_N [33]
1

DDR1_ALERT# DDR1_VREF_CA
AU52
DDR1_VREF_CA 1 2 DDR1_VREF_CA

R0502
TGLLAKE-U_BGA1449
1/20W_2_1%_0201
@
2
C0501
0.022U_6.3V_K_X5R_0201
2

A
1 R0504
1/20W_1K_1%_0201
www.teknisi-indonesia.com A
1
2

R0503
1/20W_24.9_1%_0201 Title
Security Classification LC Future Center Secret Data
Issued Date 2015/09/01 Deciphered Date 2016/12/31 TGL(C)_DDR4 CH.B
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 5 of 130

5 4 3 2 1
 5 4 3 2 1

[3,7,8,10,13,16,21,37,40,50,51,72,93,98,117,123,124] VCC3_SUS VCC3_SUS

TABLE : Functional Strap TABLE : Functional Strap [13,14,108,123] VCCST VCCST
[14,123] VCCSTG VCCSTG
[14] VCCSTG_TERM VCCSTG_TERM
DBG_PMODE (DFx Test Mode) GPP_C5/SML0ALERT# (Boot Strap Bit 0)

HIGH DFx Test Mode Disabled (default) * GPP_H0 (Boot Strap Bit 1)

LOW DFx Test Mode Enabled GPP_H1 (Boot Strap Bit 2)

GPP_H2 (Boot Strap Bit 3)

TABLE : Functional Strap
D
0000b Master Attached Flash Configuration (Default) D
GPP_F7 (Reserved) - Should Sample LOW

HIGH

LOW (Default)

TABLE : Functional Strap

GPP_F10 (Reserved) - Should Sample LOW

HIGH

LOW (Default) VCCSTG_TERM VCC1R05_OUT_FET VCCST VCCSTG VCCSTG_TERM

2
R0601

1
1/20W_1K_5%_0201
R0629

1/20W_51_5%_0201
@ R0609

1/20W_51_5%_0201
@ R0610

1/20W_51_5%_0201

1/20W_100_5%_0201
@ R0612
1/20W_1K_5%_0201 R0602 R0603 R0604

R0611
@ 1/20W_1.5K_5%_0201 1/20W_1K_5%_0201 1/20W_1K_5%_0201
1

2
UCPU1U
21 OF 21

C -CATERR M7 K4 PROC_TRST R0614 1 2 0_0201_SP -XDP_TRST C

PECI CATERR# PROC_TRST# PROC_TMS R0615 1 2 0_0201_SP XDP_TMS
[85] PECI BK9 B9
-PROCHOT R0605 2 1 1/20W_499_1%_0201 -PROCHOT_CPU E2 PECI PROC_TMS PROC_TDO R0616 1 2 0_0201_SP XDP_TDO
[59,85,102,108] -PROCHOT D12
-THRMTRIP PROCHOT# PROC_TDO PROC_TDI R0617 1 2 0_0201_SP XDP_TDI
M5 A12
THRMTRIP# PROC_TDI PROC_TCK R0618 1 2 0_0201_SP XDP_TCK0
B6
R0607 1 2 1/20W_49.9_1%_0201 PROC_POPIRCOMP CT39 PROC_TCK
R0608 1 2 1/20W_49.9_1%_0201 PCH_OPIRCOMP PROC_POPIRCOMP
CB9 D8
PCH_OPIRCOMP PCH_JTAGX
CW12 A9
TP_1 PCH_TMS
CM39 E12
TP_2 PCH_TDO
B12
DBG_PMODE PCH_TDI
DF4 A7 PCH_TCK_R
DBG_PMODE PCH_TCK
H4
GPP_B4 PCH_TRST#
DB42
GPP_B3 GPP_B4/CPU_GP3
DB41 C11
-CS_SLEEP GPP_B3/CPU_GP2 PROC_PREQ#
DF8 D11
GPP_E7/CPU_GP1 PROC_PRDY#
DU5
GPP_E3/CPU_GP0 -EAR_STRAP
G1
GPP_H2 EAR_N/EAR_N_TEST_NCTF
DF31
GPP_H1 GPP_H2
DV32 DT15
GPP_H1 GPP_F7
DW32 DR15
GPP_H0 GPP_F9
DT14PLANARID0 PLANARID0 [7]
-MIC_HW_EN DJ27 GPP_F10
GPP_H19/TIME_SYNC0

TGLLAKE-U_BGA1449

2
R0619 @ R0620 R0621
0_0201_SP 1/20W_51_5%_0201 @ 1/20W_51_5%_0201

1
B B

VCC3_SUS

R0623 1 @ 2 1/20W_100K_5%_0201-CS_SLEEP

R0625 1 @ 2 1/20W_20K_5%_0201 GPP_H1

R0626 1 @ 2 1/20W_20K_5%_0201 GPP_H2

R0627 1 @ 2 1/20W_0_5%_0201 GPP_B4

R0628 1 @ 2 1/20W_0_5%_0201 GPP_B3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 TGL(D)_MISC/ JTAG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 6 of 130

5 4 3 2 1
 5 4 3 2 1

TABLE : Functional Strap TABLE : Functional Strap TABLE : Functional Strap

SPI0_MOSI (Boot Halt) SPI0_IO3 (A0 Personality Strap) GPP_C5/SML0ALERT# (Boot Strap Bit 0)

HIGH Disabled * HIGH Disabled * GPP_H0 (Boot Strap Bit 1)

LOW Enabled LOW Enabled GPP_H1 (Boot Strap Bit 2)

GPP_H2 (Boot Strap Bit 3)

TABLE : Functional Strap TABLE : Functional Strap
0000b Master Attached Flash Configuration (Default)
SPI0_IO2 (Consent Strap) GPP_E6 (JTAG ODT Disable)
D D
HIGH Disabled * HIGH JTAG ODT Enabled *
LOW Enabled LOW JTAG ODT Disabled

TABLE : Functional Strap TABLE : Functional Strap

GPP_C2/SMBALERT# (TLS Confidentiality) GPP_B23/SML1ALERT#/PCHHOT# (CPUNSSC Clock Frequency)

HIGH Enable ME Crypto TLS with Confidentiality * HIGH 19.2MHz Clock (Derived from 38.4MHz Crystal)

LOW Disable ME Crypto TLS (Default) LOW 38.4MHz Clock (Direct from Crystal) *

VCC3_SUS VCC3_SUS VCC3B VCC3_SUS VCC3B

VCC3_SUS VCC3_SUS VCC3_SUS VCC1R8_SUS

1
1/20W_100K_5%_0201
R0705

1/20W_47K_5%_0201
R0706

R0713

R0714

R0715

R0716

R0717

R0718

R0719
R0702

R0703

R0704
@

1
1/20W_10K_5%_0201

2
1

@
R0701

SPI_CLK_CPU 1 2

2
1/20W_1K_5%_0201

1/20W_499_1%_0201

1/20W_499_1%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_1K_5%_0201
C C

1/20W_1K_5%_0201
R0938
2

2
1/20W_100K_5%_0201

1/20W_100K_5%_0201
1/20W_4.7K_5%_0201

1/20W_100K_5%_0201
1/20W_15K_5%_0201
1

R0707
2

UCPU1E
@
5 OF 21

SPI_CLK R0708 1 2 1/20W_10_1%_0201 SPI_CLK_CPU DJ37 DK21 SMB_CLK

[21,98]
[21]
SPI_CLK
SPI_IO3
SPI_IO3 R0709 1 2 1/20W_10_1%_0201 SPI_IO3_CPU DG35
SPI0_CLK GPP_C0/SMBCLK
DM19 SMB_DATA SMB_CLK [93]
SMB_DATA [93]
DIMM1,DIMM2,CP
SPI_IO2 R0710 1 2 1/20W_10_1%_0201 SPI_IO2_CPU SPI0_IO3 GPP_C1/SMBDATA GPP_C2
[21] SPI_IO2 DJ39 DN19
SPI_MISO_IO1 R0711 1 2 1/20W_10_1%_0201 SPI_MISO_IO1_CPU SPI0_IO2 GPP_C2/SMBALERT#
[21,98] SPI_MISO_IO1 DJ33
SPI_MOSI_IO0 R0712 1 2 1/20W_10_1%_0201 SPI_MOSI_IO0_CPU SPI0_MISO SML0_CLK
[21,98] SPI_MOSI_IO0 DJ35 DK19 SML0_CLK [55,73]
-SPI_CS1 SPI0_MOSI GPP_C3/SML0CLK SML0_DATA
DF35 DM17
-SPI_CS1 For
[21]
SPI [21]
-SPI_CS1
-SPI_CS0
-SPI_CS0 DG37
SPI0_CS1# GPP_C4/SML0DATA
DN17 SML0_ALERT_N SML0_DATA [55,73] LAN PHY,TBT BB
-SPI_CS2 SPI0_CS0# GPP_C5/SML0ALERT#
-SPI_CS0 For SPI [98] -SPI_CS2 DF39
SPI0_CS2#
-SPI_CS2 For TPM DK17 SML1_CLK
GPP_C6/SML1CLK SML1_DATA SML1_CLK [59,93]
DJ6 DJ17
[40,119] 1R8VIDEO_AON_ON
1R8VIDEO_AON_ON DN5 GPP_E11/THC0_SPI1_CLK GPP_C7/SML1DATA
CY50 SML1_ALERT_N SML1_DATA [59,93] TBT's PD
GPP_E2/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#
DR9
GPP_E1/THC0_SPI1_IO2 -ESPI_CLK_R R0720 1 2 1/20W_51_5%_0201
DM6 DN53 ESPICLK_60M [85]
-GPU_RST DK6 GPP_E12/THC0_SPI1_IO1 GPP_A5/ESPI_CLK ESPI_IO3_R R0721 1 2 1/20W_15_5%_0201
[37] -GPU_RST DJ53 ESPI_IO3 [85]
GPP_E13/THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2_R R0722 1 2 1/20W_15_5%_0201
M2_CARD_DET DK8
GPP_E10/THC0_SPI1_CS# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK
DH50 ESPI_IO2 [85]
0 -W/CARD ==>GND [64] DV11 DP50 ESPI_IO1_R R0723 1 2 1/20W_15_5%_0201
M2_CARD_DET GPP_E8/SATA_LED# GPP_A1/ESPI_IO1 ESPI_IO1 [85]
1 -W/O CARD ==>PU [51] DW9 DP52 ESPI_IO0_R R0724 1 2 1/20W_15_5%_0201
-TCH_PNL_INT GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_IO0 [85]
GPP_E6 DT8 DK52 -ESPI_CS_R R0725 1 2 0_0201_SP
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# -ESPI_RESET_R -ESPI_CS [85]
DL50 R0726 1 2 0_0201_SP
GPP_A6/ESPI_RESET# -ESPI_RESET [85]
PLANARID1 DN15
GPP_F11/THC1_SPI2_CLK
DK13
GPP_F15/GSXSRESET#/THC1_SPI2_IO3
DM13
GPP_F14/GSXDIN/THC1_SPI2_IO2

1
PLANARID3 DN13
PLANARID2 GPP_F13/GSXSLOAD/THC1_SPI2_IO1
DJ15 1
GPP_F12/GSXDOUT/THC1_SPI2_IO0 R0727
B DK15 B
GPP_F16/GSXCLK/THC1_SPI2_CS# 1/20W_75K_1%_0201 C0701
DN10
GPP_F18/THC1_SPI2_INT# 22P_50V_J_NPO_0402
DV14

2
GPP_F17/THC1_SPI2_RST# 2 EMC_NS@
CL_CLK_WLAN DH3
[66] CL_CLK_WLAN CL_DATA_WLAN CL_CLK
[66] CL_DATA_WLAN DH4
-CL_RST_WLAN CL_DATA
[66] -CL_RST_WLAN DF2
CL_RST#

TGLLAKE-U_BGA1449
@
10PC_25VC_JC_NPOC_0201

2
1/20W_1M_1%_0201

1
1

@ R0728
R0733

C0702

@ 1/20W_1K_5%_0201
2
1
2

TABLE: PLANARID PHASE PLANARID3

PLANARID2
PLANARID[3:0] Wave1 Wave2 PLANARID1
PLANARID0
PLANARID0 [6]
0h (0000b) FVT1 FVT1
1/20W_0_5%_0201

1/20W_0_5%_0201

1/20W_0_5%_0201

1/20W_0_5%_0201

1h (0001b) FVT2 FVT2

2

2h (0010b) SIT FVT3

R0729

R0730

R0731

R0732

3h (0011b) SIT @ @ @ @
A A
Fh (1111b) SVT SVT
1

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (5/16): ESPI/SPI/SMBUS/C-LINK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 7 of 130

5 4 3 2 1
 5 4 3 2 1

TABLE : Functional Strap TABLE : Functional Strap GPP_B22, Internal PD 20K GPP_B18, Internal PD 20K
*L: SPI *L: Disable “ No Reboot” mode VCC3_SUS
GPP_B14/SPKR (Top Swap Override) GPP_B18/GSPI0_MOSI (No Reboot) H: LPC VCC3_SUS H: Enable “ No Reboot” mod
e

1
HIGH Enable "Top Swap" mode HIGH Enable "No Reboot" Mode ISH I2C0: 1.8V R0821 R0823
@ 1/20W_4.7K_5%_0201 @ 1/20W_0_5%_0201
LOW Disable "Top Swap" mode (Default) * LOW Disable "No Reboot" Mode (Default) * ISH I2C1: 3.3V

2
GPP_B18
GPP_B22

1
R0824

1
@ 1/20W_0_5%_0201
D D
R0822
@ 1/20W_20K_5%_0201

2
2
VCC3_SUS VCC3WLAN VCC3_SUS VCC3_SUS

1/20W_10K_5%_0201

R0803
2

2
R0801

R0805

R0806

R0807

R0808
@
@

1/20W_10K_5%_0201
1

2
@ @

1
1/20W_10K_5%_0201
1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_1K_5%_0201
UCPU1F
6 OF 21

R81096 1 2 0_0201_SP
[85] TOP_SWAP_EN
GPP_B16 DC53 DR27 BOARD_ID_CTL Touch Panel
GPP_B18 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD
DA51 DW27 -TCH_PNL_RST [51]
GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD
DC49 DV25 -SSD_RTD3_RST_CPU -SSD_RTD3_RST_CPU [64]
PCH_SPKR GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#
[83] PCH_SPKR DC50 DT25
Size CTL GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5
[51] Size CTL DC52
GPP_B15/GSPI0_CS0#
DB45
PAD_DISABLE R0810 1 2 0_0201_SP PAD_DISABLE_PCH GPP_B6/ISH_I2C0_SCL
C
[89] PAD_DISABLE CY49 DB44 C
GPP_B22 GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA
CY53
HP_JACK_IN GPP_B22/GSPI1_MOSI
[70] HP_JACK_IN CY52 CY39
-WLAN_RF_KILL DA50 GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL
[66] -WLAN_RF_KILL DB47
GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA
DV21 DD47
GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL
DT21 DD44
GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA
DR21
GPP_C11/UART0_CTS#
DW21 DJ8
GPP_C10/UART0_RTS# GPP_E16/ISH_GP7
DR7 -TOUCH_DETECT [51]
GPP_E15/ISH_GP6
[51] TCH_PNL_EN DV19 DR24
SMARTCARD_ON GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_D18/ISH_GP5
[72] SMARTCARD_ON DT19 DU25
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4
DR18 DV31
-TPM_IRQ GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3
[98] -TPM_IRQ DU19 DU31
GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2 -LID_CLOSE_PCH R0811 1 2 0_0201_SP -LID_CLOSE_CP
DT27 -LID_CLOSE_CP [89]
UART_TX GPP_D1/ISH_GP1/BK1/SBK1 TP4_RESET_PCH R0812 1 2 0_0201_SP TP4_RESET
[66,84] UART_TX DJ21 DV27 TP4_RESET [88]
UART_RX GPP_C21/UART2_TXD GPP_D0/ISH_GP0/BK0/SBK0
[66,84] UART_RX DG23
-EC_WAKE GPP_C20/UART2_RXD GPP_RCOMP
[85] -EC_WAKE DJ19 DR51
-EC_SCI_C GPP_C23/UART2_CTS# GPP_RCOMP
DF21
GPP_C22/UART2_RTS#
DN33
GPP_T3
DV18 DT35
GPP_C17/I2C0_SCL GPP_T2
DW18
GPP_C16/I2C0_SDA
DG17
LPSS_I2C1_SCL_PNL GPP_U5
[51] LPSS_I2C1_SCL_PNL DJ23 DG19
LPSS_I2C1_SDA_PNL GPP_C19/I2C1_SCL GPP_U4
Touch Panel[51] LPSS_I2C1_SDA_PNL DT18
GPP_C18/I2C1_SDA
DJ29
GPP_H5/I2C2_SCL
DJ31
GPP_H4/I2C2_SDA

1
DF29 1
GPP_H7/I2C3_SCL EMC_NS@ R0818
NFC DG29
GPP_H6/I2C3_SDA C0801 1/20W_200_1%_0201
DF25 10P_25V_J_NPO_0201
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD 2
DF27

2
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
1

R0819
TGLLAKE-U_BGA1449
1/16W_100K_5%_0402
B @ B
2

LPSS Port Assignment

I2C0 Reserved
I2C1 Touch Panel Graphics ID
I2C2 -DISCRETE_ VCC3B
Reserved
Status PRESENCE
I2C3 NFC (GPP_E18)
I2C4 Reserved
DIS 0 (R0817)
I2C5 USB 3.1 Gen2 redriver

1
UART0 R0814 R0815
UMA 1 (R0815) HDD@ 1/20W_10K_5%_0201 UMA@ 1/20W_10K_5%_0201
UART1

2
UART2 -DISCRETE_PRESENCE
Debug Port [3] -DISCRETE_PRESENCE
BOARD_ID_CTL
GSPI0 BOARD ID Control

1
Reserved BOARD_ID_CTL R0816 R0817
GSPI1 SSD@ DIS@
Status (GPP_D14) 1/20W_10K_5%_0201 1/20W_10K_5%_0201
GSPI2

2
SSD 0 (R0816)
A A

HDD 1 (R0814)

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (6/16): LPSS/ISH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 8 of 130

5 4 3 2 1
 5 4 3 2 1

VCC1R8_SUS PLACE ON BOTTOM SIDE

1 2 FLASH_DESC_R 1 @ 2
D D
TABLE : Functional Strap R0901 R0902
1/20W_1K_5%_0201 1/20W_0_5%_0201
GPP_R2/HDA_SDO/I2S0_TXD
Flash Descriptor Security Override 1 1
HIGH Disable Flash Descriptor Security (Override) TP0901 TP0902
LOW Enable Flash Descriptor Security (Default) Test_Point_40MIL Test_Point_40MIL
VCC3WLAN
TEST PAD

1/20W_10K_5%_0201
BOTTOM SIDE

2
DO NOT MOVE AFTER FIX

R0903
1
UCPU1G
7 OF 21 R0904 1 2 0_0201_SP ME_FLASH
ME_FLASH [85]

R0917 2 1 0_0201_SP GC6_FB_EN_R DW15 DR38 HDA_BCLK_PCH EMC@ R0905 1 2 1/20W_33_5%_0201 HDA_BCLK
[40,118] GC6_FB_EN -SC_DTCT GPP_F8/I2S_MCLK2_INOUT GPP_R0/HDA_BCLK/I2S0_SCLK HDA_SYNC_PCH HDA_SYNC HDA_BCLK [78]
DW24 DU37 R0906 1 2 1/20W_33_5%_0201
[72] -SC_DTCT GPP_D19/I2S_MCLK1 GPP_R1/HDA_SYNC/I2S0_SFRM HDA_SYNC [78]
DT37 HDA_SDO_PCH R0907 1 2 1/20W_33_5%_0201 HDA_SDO
GPP_R2/HDA_SDO/I2S0_TXD HDA_SDO [78]
RT_FORCE_PWR DG41 DV37 HDA_SDIN0
[55,59] RT_FORCE_PWR GPP_A23/I2S1_SCLK GPP_R3/HDA_SDI0/I2S0_RXD HDA_SDIN0 [78]
DT38 @
GPP_R7/I2S1_SFRM
DV38 DV41 HDA_RST_N_R 1 TP9808
GPP_R6/I2S1_TXD GPP_R4/HDA_RST#
DW38 DL53
GPP_R5/HDA_SDI1/I2S1_RXD GPP_A7/I2S2_SCLK/DMIC_CLK_A0
DG51
PCH_DMIC_CLK0 1/20W_33_5%_0201 2 1 R0912 DMIC_CLK0_PCH_R GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0
[51] PCH_DMIC_CLK0 DN31 DG50
PCH_DMIC_DATA0 2 1 DMIC_DATA0_PCH_R GPP_S6/SNDW3_CLK/DMIC_CLK_A0 GPP_A10/I2S2_RXD/DMIC_DATA1
[51] PCH_DMIC_DATA0 DM31
R0914 0_0201_SP GPP_S7/SNDW3_DATA/DMIC_DATA0
DL49
GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1 SSD_ON
C DK33 DL52 SSD_ON [125] C
GPP_S4/SNDW2_CLK/DMIC_CLK_A1 GPP_A11/PMC_I2C_SDA/I2S3_SCLK
DK31
GPP_S5/SNDW2_DATA/DMIC_DATA1 BDC_ON
DH49 BDC_ON [66]
GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0
DW35
GPP_S2/SNDW1_CLK/DMIC_CLK_B0 SD_RCOMP
DV35 DF33
GPP_S3/SNDW1_DATA/DMIC_CLK_B1 SNDW_RCOMP
1/20W_10K_5%_0201

1/20W_10K_5%_0201

DT32
GPP_S0/SNDW0_CLK
1

DR35
GPP_S1/SNDW0_DATA
R0911

R0916
DIS@

1
R0910
TGLLAKE-U_BGA1449

1
1/20W_200_1%_0201
2

@ R0909
@ 1/20W_100K_5%_0201

2
HDA_BCLK PCH_DMIC_CLK0
HDA_SDO_PCH
22P_25V_J_NPO_0201_MURATA

HDA_SYNC HDA_RST_N_R PCH_DMIC_DATA0

220P_25V_K_X5R_0201

B 1 1 B
EMC@ 1 EMC_NS@ 1 RF@ RF@
C0901 C0902 C0903 C0904 1 1
2P_25V_C_NPO_0201 2P_25V_C_NPO_0201
2 2 C0906 C0907
2 2 47P_50V_J_NPO_0402 47P_50V_J_NPO_0402
2 2
EMC_NS@ EMC_NS@
RF 20191213 Add
EMC 20200505 Add

Place Near CPU Side

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (7/16): AUDIO/SDXC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 9 of 130

5 4 3 2 1
 5 4 3 2 1

Flexible I/O Configuration PCIe Port Assignment (up to Gen3) USB 3.0 Port Assignment USB 2.0 Port Assignment
PCI PCI PCIE 1 USB3P1 USB3_1 USB Type-A Port-A (DCI) (Sub board) USB2_1 USB Type-A Port-A (DCI) (Sub board)
HSIO Port High Speed Signals HSIO Descriptor
Device Function Configuration for PCIe Net Name Device Function PCIE 2 USB3P2 USB3_2 USB Type-A Port-A (AOU) (MB) USB2_2 Reserved
PCIE 3 Reserved USB3_3 Reserved USB2_3 Reserved
PCH L0 USB 3.1 #1 / PCIe Gen3 #1 0h USB 3.1 #1 USB3P1
1x2, 2x1 PCIE 4 Reserved USB3_4 Reserved USB2_4 Finger Print
PCH L1 USB 3.1 #2 / PCIe Gen3 #2 1h USB 3.1 #2 USB3P2
1Ch Lane Reversal PCIE 5 GPU PCIE5_L0 USB2_5 SMART Card
PCH L2 USB 3.1 #3 / PCIe Gen3 #3 2h PCIe Gen3 #3 Disabled N/A
PCIE 6 GPU PCIE5_L1 USB2_6 TYPE-C Port (Rear Port)
PCH L3 USB 3.1 #4 / PCIe Gen3 #4 3h PCIe Gen3 #4 N/A
PCIE 7 GPU PCIE5_L2 USB2_7 Camera
PCH L4 PCIe Gen3 #5 4h PCIe Gen3 #5 PCIE5_L0
1x4 PCIE 8 GPU PCIE5_L3 USB2_8 Thunderbolt Port-B (Front Port)
PCH L5 PCIe Gen3 #6 5h PCIe Gen3 #6 PCIE5_L1
1Ch Lane Reversal PCIE 9 GbE PHY USB2_9 USB Type-A Port-A (AOU) (MB)
PCH L6 PCIe Gen3 #7 (GbE) 6h PCIe Gen3 #7 (GbE) Disabled PCIE5_L2
PCIE 10 Media Card Reader SATA Port Assignment USB2_10 BT
D PCH L7 PCIe Gen3 #8 (GbE) 7h PCIe Gen3 #8 PCIE5_L3 D
PCIE 11 SATA 0 2.5" SATA HDD
PCH L8 PCIe Gen3 #9 (GbE) 0h PCIe Gen3 #9 (x4) PCIE9
4x1 PCIE 12 WLAN SATA 1
PCH L9 PCIe Gen3 #10 1h PCIe Gen3 #10 (x4) Lane Reversal PCIE10
1Dh
PCH L10 PCIe Gen3 #11 / SATA #0 2h PCIe Gen3 #11 (x4) Disabled PCIE11 PCIe Port Assignment (up to Gen4)
PCH L11 PCIe Gen3 #12 / SATA #1 3h PCIe Gen3 #12 (x4) PCIE12 PCIE 4_L0 NVMe SSD
CPU L0 PCIe Gen4 x4Lane 0 PCIe Gen4 (x4) L0 1x4 PCIE4_L0 PCIE 4_L1 NVMe SSD
CPU L1 PCIe Gen4 x4Lane 1 PCIe Gen4 (x4) L1 Lane Reversal PCIE4_L1 PCIE 4_L2 NVMe SSD VCC3_SUS VCC3B
06h 0h Disabled
CPU L2 PCIe Gen4 x4Lane 2 PCIe Gen4 (x4) L2 PCIE4_L2 PCIE 4_L3 NVMe SSD
CPU L3 PCIe Gen4 x4Lane 3 PCIe Gen4 (x4) L3 PCIE4_L4

R1001

R1002

R1011

R1012
1
1

1
teknisi-indonesia.com

2
2

2
1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201
UCPU1I
9 OF 21

PCIE12_TXP BT7 CV4 USB2_P10_DP

[66] PCIE12_TXP PCIE12_TXN PCIE12_TXP/SATA1_TXP USB2P_10 USB2_P10_DN USB2_P10_DP [66]
[66] PCIE12_TXN BT8 CY3 USB2_P10_DN [66] BT
PCIE12_RXP PCIE12_TXN/SATA1_TXN USB2N_10
CE2
WLAN [66]
[66]
PCIE12_RXP
PCIE12_RXN
PCIE12_RXN CE1
PCIE12_RXP/SATA1_RXP
PCIE12_RXN/SATA1_RXN USB2P_9
DD5 USB2_P9_DP
USB2_P9_DP [69]
DD4 USB2_P9_DN USB Type-A Port-A (AOU)
PCIE11_L0_SATA0_TXP USB2N_9 USB2_P9_DN [69]
[97] PCIE11_L0_SATA0_TXP BT9
PCIE11_L0_SATA0_TXN PCIE11_TXP/SATA0_TXP USB2_P8_DP
C [97] PCIE11_L0_SATA0_TXN BV9 CW9 USB2_P8_DP [62] C
PCIE11_L0_SATA0_RXP PCIE11_TXN/SATA0_TXN USB2P_8 USB2_P8_DN
CF4 DA9 Thunderbolt Port-B
2.5" SATA HDD [97]
[97]
PCIE11_L0_SATA0_RXP
PCIE11_L0_SATA0_RXN
PCIE11_L0_SATA0_RXN CF3
PCIE11_RXP/SATA0_RXP
PCIE11_RXN/SATA0_RXN
USB2N_8 USB2_P8_DN [62]
DD1 USB2_P7_DP
PCIE10_TXP USB2P_7 USB2_P7_DN USB2_P7_DP [51]
[76] PCIE10_TXP BV7 DD2 USB2_P7_DN [51] CAMERA
PCIE10_TXN PCIE10_TXP USB2N_7
[76] PCIE10_TXN BV8
PCIE10_RXP PCIE10_TXN USB2_P6_DP
Media Card Reader [76] PCIE10_RXP PCIE10_RXN
CG2
PCIE10_RXP USB2P_6
DA1
USB2_P6_DN USB2_P6_DP [63]
[76] PCIE10_RXN CG1
PCIE10_RXN USB2N_6
DA2 USB2_P6_DN [63] TYPE-C
PCIE9_TXP BY7 DA12 USB2_P5_DP
[73] PCIE9_TXP PCIE9_TXN PCIE9_TXP USB2P_5 USB2_P5_DN USB2_P5_DP [72]
[73] PCIE9_TXN BY8
PCIE9_TXN USB2N_5
DA11 USB2_P5_DN [72] SMART Card
PCIE9_RXP CG5
LAN [73]
[73]
PCIE9_RXP
PCIE9_RXN
PCIE9_RXN CG4
PCIE9_RXP
PCIE9_RXN USB2P_4
DC8 USB2_P4_DP
USB2_P4_DP [89]
DC7 USB2_P4_DN
PCIE5_L3_TXP CB8
USB2N_4 USB2_P4_DN [89] Finger Printer
[37] PCIE5_L3_TXP PCIE5_L3_TXN PCIE8_TXP
[37] PCIE5_L3_TXN CB7 DB4
PCIE5_L3_RXP PCIE8_TXN USB2P_3
[37] PCIE5_L3_RXP CK5 DB3
PCIE5_L3_RXN PCIE8_RXP USB2N_3
[37] PCIE5_L3_RXN CK4
PCIE8_RXN
DA5
PCIE5_L2_TXP USB2P_2
[37] PCIE5_L2_TXP CD9 DA4
PCIE5_L2_TXN PCIE7_TXP USB2N_2
[37] PCIE5_L2_TXN CD8
PCIE5_L2_RXP PCIE7_TXN
[37] PCIE5_L2_RXP CK1 DC11 USB2_P1_DP USB2_P1_DP [70]
PCIE5_L2_RXN PCIE7_RXP USB2P_1 USB2_P1_DN
[37] PCIE5_L2_RXN CK2
PCIE7_RXN USB2N_1
DC9 USB2_P1_DN [70] USB Type-A Port-A (DCI) (Sub board)
GPU [37] PCIE5_L1_TXP
PCIE5_L1_TXP CG8
PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0
DP4 -SATA_DTCT
PCIE5_L1_TXN CG7 DF41
[37] PCIE5_L1_TXN PCIE5_L1_RXP PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM
[37] PCIE5_L1_RXP CL4
PCIE5_L1_RXN PCIE6_RXP -USB_TCSS_OC0
[37] PCIE5_L1_RXN CL3 DD8 -USB_TCSS_OC0 [59]
PCIE6_RXN GPP_E9/USB_OC0# -USB_PORT3_OC3
GPP_A16/USB_OC3#/I2S4_SFRM
DJ45 -USB_PORT3_OC3 [69] OC3 : AOU port
PCIE5_L0_TXP CJ8
[37] PCIE5_L0_TXP PCIE5_L0_TXN PCIE5_TXP SATA1_DEVSLP
[37] PCIE5_L0_TXN CJ7 DN6 (M.2_SSD)
PCIE5_L0_RXP PCIE5_TXN GPP_E5/DEVSLP1 HD_SSD_DEVSLP SATA1_DEVSLP [64]
[37] PCIE5_L0_RXP CN2 DG8 (2.5_HDD)
PCIE5_L0_RXN PCIE5_RXP GPP_E4/DEVSLP0 HD_SSD_DEVSLP [96] VCC3_SUS
[37] PCIE5_L0_RXN CN1
PCIE5_RXN

1/20W_10K_5%_0201
DN29
GPP_H15/M2_SKT2_CFG3
CR8 DK29
PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2

2
CR7 DT31
PCIE4_TXN/USB31_4_TXN GPP_H13/M2_SKT2_CFG1

R1009
CN5 DR32
PCIE4_RXP/USB31_4_RXP GPP_H12/M2_SKT2_CFG0 SSD@
CN4
PCIE4_RXN/USB31_4_RXN PCIE_COMP_P R1004 1 2 1/20W_100_1%_0201
DV9
PCIE_RCOMP_P PCIE_COMP_N
CU8 DT9

1
PCIE3_TXP/USB31_3_TXP PCIE_RCOMP
CU7
PCIE3_TXN/USB31_3_TXN
CT2 DC12 USB2_VBUSSENSE R1005 1 2 1/20W_10K_5%_0201 -SATA_DTCT
PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE USB2_ID R1006 1 2 1/20W_10K_5%_0201
CT1 DF1
PCIE3_RXN/USB31_3_RXN USB_ID

1/20W_0_5%_0201
DE1 USB2_COMP R1007 1 2 1/20W_113_1%_0201
USB3P2_TXP USB2_COMP
[69] USB3P2_TXP CW8
PCIE2_TXP/USB31_2_TXP

2
B
USB3P2_TXN CW7 E3 UFS_RESET_N Test_Point_12MIL 1 TP1001 B
[69] USB3P2_TXN PCIE2_TXN/USB31_2_TXN RSVD_BSCAN

R1010
USB Port3 (AOU) USB3P2_RXP CU3
[69] USB3P2_RXP USB3P2_RXN PCIE2_RXP/USB31_2_RXP
CT4 HDD@
[69] USB3P2_RXN PCIE2_RXN/USB31_2_RXN
USB3P1_TXP DA8
[70] USB3P1_TXP

1
USB3P1_TXN PCIE1_TXP/USB31_1_TXP
[70] USB3P1_TXN DA7
USB3P1_RXP PCIE1_TXN/USB31_1_TXN
USB Port4 For DCI (Sub board) [70] USB3P1_RXP USB3P1_RXN
CV2
PCIE1_RXP/USB31_1_RXP
[70] USB3P1_RXN CV1
PCIE1_RXN/USB31_1_RXN

TGLLAKE-U_BGA1449
@

PCIE Gen4 for NVMe SSD.

CFG[14]
1 : Normal
0 : Reversal
UCPU1H
8 OF 21

[64] PCIE4_L3_TXP P5 V5 PCIE4_L1_TXP [64]

PCIE4_TX_P_3 PCIE4_TX_P_1
[64] PCIE4_L3_TXN P7 V7 PCIE4_L1_TXN [64]
PCIE4_TX_N_3 PCIE4_TX_N_1
[64] PCIE4_L3_RXP N1 T1 PCIE4_L1_RXP [64]
PCIE4_RX_P_3 PCIE4_RX_P_1
A [64] PCIE4_L3_RXN N2 T2 PCIE4_L1_RXN [64] A
PCIE4_RX_N_3 PCIE4_RX_N_1

[64] PCIE4_L2_TXP T5 Y5 PCIE4_L0_TXP [64]

PCIE4_TX_P_2 PCIE4_TX_P_0
[64] PCIE4_L2_TXN T7 Y7 PCIE4_L0_TXN [64]
PCIE4_TX_N_2 PCIE4_TX_N_0
[64] PCIE4_L2_RXP R1 V1 PCIE4_L0_RXP [64]
PCIE4_RX_P_2 PCIE4_RX_P_0
[64] PCIE4_L2_RXN R2 V2 PCIE4_L0_RXN [64]
PCIE4_RX_N_2 PCIE4_RX_N_0
Y12 PCIE4_RCOMPP R1008 1 2 1/20W_2.2K_1%_0201
PCIE4_RCOMP_P PCIE4_RCOMPN
V12
PCIE4_RCOMP V12
2.2K_0201_1% NEED LCFC P/N
TGLLAKE-U_BGA1449
@
Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (8/16): PCIE/USB/SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 10 of 130

5 4 3 2 1
 5 4 3 2 1

TABLE : Functional Strap

GPP_F2/CNV_RGI_DT(M.2 CNVi Mode Select)

HIGH Integrated CNVi Disabled *

UCPU1J LOW Integrated CNVi Enabled
10 OF 21
D D

D22 DK47 TABLE : Functional Strap

CSI_F_DP_1 CNVI_WT_D1P
B22 DM47
CSI_F_DN_1 CNVI_WT_D1N
E22 DN49
CSI_F_DP_0 CNVI_WT_D0P
D20
CSI_F_DN_0 CNVI_WT_D0N
DR49 GPP_F0/CNV_BRI_DT (XTAL Frequency Selection)
A20 DN45
CSI_F_CLK_P CNVI_WT_CLKP
B20 DN47
CSI_F_CLK CNVI_WT_CLKN
HIGH 24MHz XTAL selected
B18 DU43
CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P
A18 DV43
D18
E18
C16
CSI_E_DN_1/CSI_F_DN_2
CSI_E_DP_0/CSI_F_DP_3
CSI_E_DN_0/CSI_F_DN_3
CNVI_WR_D1N
CNVI_WR_D0P
CNVI_WR_D0N
DR44
DT43
DV44
LOW 38.4MHz XTAL frequency selected *
CSI_E_CLK_P CNVI_WR_CLKP
D16 DW44
CSI_E_CLK CNVI_WR_CLKN
D15 DN51 CNV_WT_RCOMP
CSI_C_DP_2 CNVI_WT_RCOMP
E15
CSI_C_DN_2
A15 DJ13
CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS# RGI_DT_R
B15 DG13
CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD
DF15
GPP_F1/CNV_BRI_RSP/UART0_RXD BRI_DT_R
L18 DF17
CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS#
N18
CSI_C_DN_1 -GPU_EVENT
C
L20 DJ10 -GPU_EVENT [40] C
CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ DGFX_PWRGD
N20 DV15 DGFX_PWRGD [37] To GPU
CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING
G20 DK10
CSI_C_CLK_P GPP_F4/CNV_RF_RESET#
H20
CSI_C_CLK
H16
CSI_B_DP_1
G16
CSI_B_DN_1
G18
CSI_B_DP_0
H18
CSI_B_DN_0

1
L16
CSI_B_CLK_P R1107
N16
CSI_B_CLK 1/20W_150_1%_0201
G14
CSI_B_DP_2
H14

2
CSI_B_DN_2
L14
CSI_B_DP_3
N14
CSI_B_DN_3
Update to 150ohm from 100ohm CSI_COMP K14
CSI_RCOMP
TOUCHPANEL_ON DK25
[52] TOUCHPANEL_ON GPP_H23/IMGCLKOUT4
-TAMPER_SW_DTCT DM25
[13] -TAMPER_SW_DTCT GPP_H22/IMGCLKOUT3
DN25
GPP_H21/IMGCLKOUT2
[51] -INT_MIC_DTCT DJ25
GPP_H20/IMGCLKOUT1
DR30
GPP_D4/IMGCLKOUT_0/BK4/SBK4
B B
2

TGLLAKE-U_BGA1449
R1105
1/20W_150_1%_0201 @
1

VCC1R8_SUS

@
BRI_DT_R R1101 1 2 1/16W_4.7K_5%_0402
RGI_DT_R R1102 1 2 1/16W_100K_5%_0402

BRI_DT_R R1103 1 2 1/16W_100K_5%_0402

RGI_DT_R R1104 @1 2 1/16W_100K_5%_0402

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (9/16): CSI-2/EMMC/CNVI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 11 of 130

5 4 3 2 1
 5 4 3 2 1

D D

VCC3B
PCIE CLK Table CLKREQ Table
CLK 100M_P0 SSD CLKREQ0 SSD TABLE of Y1201
2

R1201 Vendor P/N LCFC P/N

CLK 100M_P1 LAN CLKREQ1 LAN
1/20W_10K_5%_0201
TXC 8Y38480004 SJ10000SN00
CLK 100M_P2 Media Card Reader CLKREQ2 Media Card Reader
Harmony X2CL038400DA1H-HU SJ10000XS00
1

-CLKREQ_PCIE5
CLK 100M_P3 GPU CLKREQ3 GPU
KDS 7AF03840A04 SJ10000XG00
CLK 100M_P4 Reserved CLKREQ4 Reserved
2

CLK 100M_P5 Reserved CLKREQ5 Reserved

R1202
1/20W_10K_5%_0201 CLK 100M_P6 WLAN CLKREQ6 WLAN
@
C1201
1

C C
XTAL_38P4M_OUT_R 1 2

10P_50V_D_NPO_0201
UCPU1K
11 OF 21

2
1
Y1201

NC2 3

1 NC1
PCIE12_CLK_100M BW1 DU14 -CLKREQ_PCIE12 R1206 38.4MHZ_10PF_8Y38480004
[66] PCIE12_CLK_100M CLKOUT_PCIE_P6 GPP_F19/SRCCLKREQ6# -CLKREQ_PCIE12 [66]
WLAN -PCIE12_CLK_100M BW2 DF23 1/20W_200K_1%_0201
[66] -PCIE12_CLK_100M CLKOUT_PCIE_N6 GPP_H11/SRCCLKREQ5#
DG25
GPP_H10/SRCCLKREQ4# -CLKREQ_PCIE5
CB2 DT24 -CLKREQ_PCIE5 [37]

1
CLKOUT_PCIE_P5 GPP_D8/SRCCLKREQ3# -CLKREQ_PCIE10
CB1 DT30 -CLKREQ_PCIE10 [76]
CLKOUT_PCIE_N5 GPP_D7/SRCCLKREQ2# -CLKREQ_PCIE9
DV30 -CLKREQ_PCIE9 [73]
GPP_D6/SRCCLKREQ1# -CLKREQ_PCIE4
DW30
BW4
CLKOUT_PCIE_P4
GPP_D5/SRCCLKREQ0# -CLKREQ_PCIE4 [64] EMC C1202
BW5 DM1 XTAL_38P4M_OUT EMC@ R1204 1 2 1/16W_0_5%_0402
CLKOUT_PCIE_N4 XTAL_OUT XTAL_38P4M_IN EMC@ R1205 1 2 1/16W_0_5%_0402 XTAL_38P4M_IN_R 1 2
DL1
PCIE5_CLK_100M XTAL_IN
[37] PCIE5_CLK_100M CL7
-PCIE5_CLK_100M CLKOUT_PCIE_P3
GPU [37] -PCIE5_CLK_100M CL8 DW41 SUS_CLK SUS_CLK [66]
CLKOUT_PCIE_N3 GPD8/SUSCLK 10P_50V_D_NPO_0201
PCIE10_CLK_100M CB4 DT47 RTCX2 C1203 1 2 10P_25V_J_NPO_0201
[76] PCIE10_CLK_100M CLKOUT_PCIE_P2 RTCX2
Media Card Reader[76] -PCIE10_CLK_100M CB5 DR47 RTCX1
-PCIE10_CLK_100M CLKOUT_PCIE_N2 RTCX1

1/20W_10M_5%_0201
PCIE9_CLK_100M BY4 DN37 -RTCRST
[73] PCIE9_CLK_100M CLKOUT_PCIE_P1 RTCRST# -RTCRST [20]

2
LAN -PCIE9_CLK_100M BY3 DK37 -SRTCRST
[73] -PCIE9_CLK_100M CLKOUT_PCIE_N1 SRTCRST# -SRTCRST [20]

R1208
Y1202
PCIE4_CLK_100M CN7 32.768KHZ_9PF_9H03280012
[64] PCIE4_CLK_100M CLKOUT_PCIE_P0
SSD -PCIE4_CLK_100M CN8 SJ10000J900
[64] -PCIE4_CLK_100M

1
B CLKOUT_PCIE_N0 B

1
CLK_BIASREF DJ5
XCLK_BIASREF

1
@ C1204 1 2 10P_25V_J_NPO_0201
TGLLAKE-U_BGA1449 R1207
1/20W_60.4_1%_0201

@ 1/20W_100K_5%_0201
2

、
RTCX1、 、 Crysta l
RTCX2

2
R1203

1. Space > 15mils

1

2. No trace under crystal

3. Place on oppsosit side of
MCP for temp inf l uence

TABLE of XTAL (Y1202)

Vendor LCFC P/N Description
TXC SJ10000J900 S CRYSTAL 32.768KHZ 9PF 20PPM
KDS SJ100069400 S CRYSTAL 32.768KHZ 9PF 1TJF09
A
SEIKO SJ10000IX00 S CRYSTAL 32.768KHZ 9PF X1A000 A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (10/16): CLOCK SIGNALS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 12 of 130

5 4 3 2 1
 5 4 3 2 1

TABLE : Functional Strap TABLE : Functional Strap

[4,16,51,52,55,56,59,84,85,86,88,102,103,104,105,106,110,116,118,119,120,123,124,125,126,127,128] VCC3M VCC3M
SPIVCCIOSEL (SPI Operation Voltage Select) GPD7 (Crystal Input Mode) [6,14,108,123] VCCST VCCST
-PCH_SLP_S3 1 -PCH_SLP_SUS
TP1301
-PCH_SLP_S4 1 -PCH_SLP_S3
TP1302 [3,6,7,8,10,16,21,37,40,50,51,72,93,98,117,123,124] VCC3_SUS VCC3_SUS
-PCH_SLP_M
TP1303
1 -PCH_SLP_S4 HIGH SPI Voltage is 1.8V HIGH Crystal Input is single ended
-PCH_SLP_WLAN 1 -PCH_SLP_S5
TP1304 [16,20] RTCVCC RTCVCC
-PCH_SLP_LAN 1 -PCH_SLP_WLAN
TP1305
TP1306
1 -PCH_SLP_S0 LOW SPI Voltage is 3.3V
* LOW Crystal is attached (Default) *
1

1
1/20W_100K_5%_0201
R1301

1/20W_100K_5%_0201
R1302

1/20W_100K_5%_0201
R1303

1/20W_100K_5%_0201
R1304

1/20W_100K_5%_0201
R1305
1 -PCH_SLP_LAN
TP1307
2

2
@ @ @ @ @
D D

RTCVCC VCC3_SUS VCC3B VCC3_SUS VCC3_SUS VCC3M

VCC3M VCC3M

1/20W_1M_1%_0201

1/20W_100K_5%_0201
1

1
1/20W_10K_5%_0201

1/20W_100K_5%_0201

1/20W_8.2K_5%_0201
R1315
1/20W_10K_5%_0201

1
R1306

R1307

R1309

R1312

R1314
1/20W_1K_5%_0201
R1310

1/20W_4.7K_5%_0201
R1311
2

2
@

2 @
2

2
UCPU1L
12 OF 21

-PCH_SLP_SUS DV49 BM9 CPU_PWRGD 1 TP1308 Test_Point_40MIL

[56,86] -PCH_SLP_SUS SLP_SUS# PROCPWRGD -PWRSW_EC
DK41 -PWRSW_EC [64,86]
-PCH_SLP_S5 DM43 GPD3/PWRBTN# -BATLOW
DN41
-PCH_SLP_S4 DJ41 GPD10/SLP_S5# GPD0/BATLOW# AC_PRESENT
[106,107,123] -PCH_SLP_S4 DK43 AC_PRESENT [86]
-PCH_SLP_S3 DJ43 GPD5/SLP_S4# GPD1/ACPRESENT
[123] -PCH_SLP_S3 -PCH_SLP_M DR41 GPD4/SLP_S3#
CW40 -PMC_ALERT -PMC_ALERT [59]
-PCH_SLP_WLANDT44 GPD6/SLP_A# GPP_B11/PMCALERT#
DN27 -CPU_C10_GATE -CPU_C10_GATE [123]
GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE#
DG31 -RJ45_LINKUP -RJ45_LINKUP [73,74]
-PCH_SLP_S0 DD42 GPP_H3/SX_EXIT_HOLDOFF#
-PCH_SLP_LAN DN39 GPP_B12/SLP_S0# -PCIE_WAKE
DK39 -PCIE_WAKE [66]
SLP_LAN# WAKE#

[13] -RSMRST
-RSMRST DM35 DM41 -LANWAKE_DSW R1325 1 2 0_0201_SP -LANWAKE [73]
-XDP_DBR DD10 RSMRST# GPD2/LAN_WAKE#
DT41 LANPHYPC LANPHYPC [73] FOR VPRO -LAN WAKE
-PLTRST SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON
DD41
GPP_B13/PLTRST# -RT_PERST_R
DN43
MPWRG R1316 1 2 0_0201_SP MPWRG_R DK35 GPD7
[86] MPWRG BPWRG_R DF10 DSW_PWROK
C R1317 1 2 0_0201_SP CE5 C
[86] BPWRG SYS_PWROK VCCSTPWRGOOD_TCSS
R1318 1 2 0_0201_SP CPUCORE_PWRGD_R DN35 BP8 VCCST_PWRGD
[85] CPUCORE_PWRGD PCH_PWROK VCCST_PWRGD
BP9 VCCST_OVERRIDE [123]
1 @ 2 R1319 1 2 0_0201_SP -INTRUDER DM37 VCCST_OVERRIDE
[85,108] VGATE INTRUDER#
2

2
1/20W_1M_5%_0201

1/20W_1M_5%_0201

SPIVCCIOSEL DT49 DR12 EXT_PWR_GATE#

1/20W_1M_5%_0201

SPIVCCIOSEL GPP_F20/EXT_PWR_GATE#
R1321

R1322

R1323

R1320 DW12 EXT_PWR_GATE2#

1/20W_0_5%_0201 GPP_F21/EXT_PWR_GATE2#
1

1
1/20W_100K_5%_0201
R1345

1/20W_4.7K_5%_0201
R1324

@ R1326
TGLLAKE-U_BGA1449
1

1
1/20W_100K_5%_0201
@ @ @
-INTRUDER_R

2
S1301
1 4 -PLTRST_FAR R1343 1 2 1/20W_0_5%_0201
[11] -TAMPER_SW_DTCT
@

2 3
-RT_PERST_R R1344 1 2 1/20W_0_5%_0201
SPVR310100_4P -RT_PERST [55]
@

VCC3_SUS VCCST
TABLE of (S1301) VCC3_SUS
VCCST_PWRGD
Vendor LCFC P/N Description

1
1
ALPS SN400001800 S PUSH SW SPVR310100 SPST ALPS H3.14 4P R1329 1 2 1/20W_100K_5%_0201 EXT_PWR_GATE# R1332
R1331 1/20W_1K_5%_0201
DIP SN400001J00 S PUSH SW ELUPLCQR SPST H3.14 4P R1330 1 2 1/20W_100K_5%_0201 EXT_PWR_GATE2# 1/20W_10K_5%_0201 R1333

2
VCCST_PWRGD_R 1 2 VCCST_PWRGD

2
Q1503P3
B B
1/20W_62_5%_0201

3
R1342 1 2 1/20W_100K_5%_0201 CPUCORE_PWRGD

3
Q1302
Q1301 1 LSK3541G1ET2L_VMT3

2
CPUCORE_ON 1 LSK3541G1ET2L_VMT3
[86,108] CPUCORE_ON

2
-RSMRST R1341 1 @ 2 1/20W_0_5%_0201 MPWRG_R

VCC3_SUS

-RSMRST -RSMRST_EC R1340 1 2 1/20W_0_5%_0201 -RSMRST

1
@ R1337
1/20W_10K_5%_0201
PLTRST BUFF Bypass

2
R1336 1 2 0_0201_SP
-PCH_SLP_SUS 1 2 -RSMRST
-RSMRST [13]
D1301
VCC3M RB521CM-30T2R_VMN2M-2
MPWRG 1 2

5 1 VCC3M D1302
Vcc NC RB521CM-30T2R_VMN2M-2
-PLTRST_FAR 1 2
[37,51,64,66,73,76] -PLTRST_FAR

1
2 -PLTRST
R1334 IN A R1338
1/20W_33_5%_0201 1/20W_10K_5%_0201
-PLTRST_NEAR 1 2 -PLT_RST 4 3
[98] -PLTRST_NEAR OUT GND

2
1 1 R1335 Q1501P3
100P_25V_J_NPO_0201
C1301

100P_25V_J_NPO_0201
C1302

1/20W_33_5%_0201 U1301

3
A NL17SZ17XV5T2G_SON-5 A

2 2 @
Q1303 Q1304
-RSMRST_EC 1 LSK3541G1ET2L_VMT3 1 LSK3541G1ET2L_VMT3
[86] -RSMRST_EC

2
1 2

@ R1339
1/20W_100K_5%_0201

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (11/16): SYSTEM PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 13 of 130

5 4 3 2 1
 5 4 3 2 1

VCCST VCCST_CPU VCCCPUCORE

[15,109,112] VCCCPUCORE
R1405 1 2 0_0402_SP VCCST
[6,13,108,123] VCCST

[4,5,15,33,34,35,36,106] VCC1R2A VCC1R2A

VCCSTG VCCSTG_CPU VCCSTG_TERM
VCC1R2A [6] VCCSTG_TERM
R1406 1 2 0_0402_SP UCPU1O VCCSTG
[6,123] VCCSTG
15 OF 21
[18,85] VCCIO_OUT VCCIO_OUT
D D
AA39 AF9 VCCSTG_OUT_1
VDD2_1 VCCSTG_OUT_1
AB40 AF12
VDD2_2 VCCSTG_1
AC39 AD12
VDD2_3 VCCSTG_2 INTERNAL RAIL
AD40
VDD2_4
AD51 AN10
VDD2_5 VCCSTG_OUT_2 VCCIO_OUT
AD52 AM9
VDD2_6 VCCSTG_OUT_3 INTERNAL RAIL
AE39 AG10
VDD2_7 VCCSTG_OUT_4
AF40
VDD2_8 VCCSTG_TERM VCCST_CPU
AG39 V15
VDD2_9 VCCIO_OUT
AH40
VDD2_10
AJ39 M9
VDD2_11 VCCSTG_OUT_LGC
AK40
VDD2_12
AK51 BT2
VDD2_13 VCCST_1
AK52 BT1
VDD2_14 VCCST_2 VCCSTG_CPU
AL39 BT4 1 1
VDD2_15 VCCST_3
AM40
VDD2_16 C1403 C1404
AN39 BP2
VDD2_17 VCCSTG_3
AP40 BP1 1U_25V_K_X5R_0402 1U_25V_K_X5R_0402
VDD2_18 VCCSTG_4 2 2
AR39 BP4
VDD2_19 VCCSTG_5
AT52
VDD2_20
AU40
VDD2_21
AW40
UCPU1M VDD2_22
AW51
VCCCPUCORE VCCCPUCORE VDD2_23
AW52 1 1
13 OF 21 VDD2_24
BD51
VDD2_25 C1401 C1402
BD52
VDD2_26
A24 G32 BK51 1U_25V_K_X5R_0402 1U_25V_K_X5R_0402
VCCIN_1 VCCIN_66 VDD2_27 2 2
A26 H24 BK52
VCCIN_2 VCCIN_67 VDD2_28
A29 H26 BV51
VCCIN_3 VCCIN_68 VDD2_29
C A30 H30 BV52 C
VCCIN_4 VCCIN_69 VDD2_30
A33 H32 CA40
VCCIN_5 VCCIN_70 VDD2_31
A35 J1 CC40
VCCIN_6 VCCIN_71 VDD2_32
AY39 J2 CC49
VCCIN_7 VCCIN_72 VDD2_33
B24 K1 CC50
VCCIN_8 VCCIN_73 VDD2_34
B26 K2 CE40
VCCIN_9 VCCIN_74 VDD2_35
B29 K24 CG40
VCCIN_10 VCCIN_75 VDD2_36
B30 K26 CH39
VCCIN_11 VCCIN_76 VDD2_37
B33 K30 CJ40
VCCIN_12 VCCIN_77 VDD2_38
B35 K32 CL40
VCCIN_13 VCCIN_78 VDD2_39
BA10 L24 CN40
VCCIN_14 VCCIN_79 VDD2_40
BA40 L26 CP47
VCCIN_15 VCCIN_80 VDD2_41
BB39 L30 CR40
VCCIN_16 VCCIN_81 VDD2_42
BB9 L32 D50
VCCIN_17 VCCIN_82 VDD2_43
BC10 N24 E51
VCCIN_18 VCCIN_83 VDD2_44
BC40 N26 F49
VCCIN_19 VCCIN_84 VDD2_45
BD39 N30 T51
VCCIN_20 VCCIN_85 VDD2_46
BD9 N32 T52
VCCIN_21 VCCIN_86 VDD2_47
BE10 P24
VCCIN_22 VCCIN_87
BE40 P26
VCCIN_23 VCCIN_88
BF9 P28 TGLLAKE-U_BGA1449
VCCIN_24 VCCIN_89
BG10 P30
VCCIN_25 VCCIN_90 @
BG40 P32
VCCIN_26 VCCIN_91
BH12 T21
VCCIN_27 VCCIN_92 VCCST
BH39 T23
VCCIN_28 VCCIN_93
BH9 T25
VCCIN_29 VCCIN_94
BJ10 T27
VCCIN_30 VCCIN_95
BJ40 T31
VCCIN_31 VCCIN_96
@ R1413

BK39 U23
VCCIN_32 VCCIN_97
1

1
1/20W_100_1%_0201
R1412

1/20W_43_5%_0201

1/20W_56_5%_0201
R1414 VCCCPUCORE
BL10 U27
B VCCIN_33 VCCIN_98 B
BL40 U29
VCCIN_34 VCCIN_99
BM39 U31
VCCIN_35 VCCIN_100
BN40 U33
VCCIN_36 VCCIN_101
BP12 V23
2

VCCIN_37 VCCIN_102

1
1/20W_100_1%_0201
R1415
BP39 V25
VCCIN_38 VCCIN_103
BR10 V27
VCCIN_39 VCCIN_104
BR40 V29
VCCIN_40 VCCIN_105
BT12 V31
VCCIN_41 VCCIN_106
BT39 V33

2
VCCIN_42 VCCIN_107
BU10 W22
VCCIN_43 VCCIN_108
BU40 W24
VCCIN_44 VCCIN_109
BV12 W28
VCCIN_45 VCCIN_110
BY12 W32
VCCIN_46 VCCIN_111
CA10
VCCIN_47 VCC_SENSE_R R1407 1 2 0_0201_SP VCC_SENSE
CB12 R38 VCC_SENSE [108]
VCCIN_48 VCCIN_SENSE VSS_SENSE_R R1408 1 2 0_0201_SP VSS_SENSE
D24 R37 VSS_SENSE [108]
VCCIN_49 VSSIN_SENSE
D26
VCCIN_50
D29 M12 SVID_DATA_CPU R1409 1 2 0_0201_SP SVID_DATA
SVID_DATA [108]
VCCIN_51 VIDSOUT
D30 M11 SVID_CLK_CPU R1410 1 2 0_0201_SP SVID_CLK
SVID_CLK [108]
VCCIN_52 VIDSCK
D33 P12 -SVID_ALERT_CPU R1411 1 2 0_0201_SP -SVID_ALERT
-SVID_ALERT [108]
VCCIN_53 VIDALERT#
D35
VCCIN_54
E24
VCCIN_55
1
1/20W_100_1%_0201
R1416
E26
VCCIN_56
E27
VCCIN_57
E29
VCCIN_58
E30
VCCIN_59
E32
2

VCCIN_60
E33
VCCIN_61
G2
VCCIN_62
A G24 A
VCCIN_63
G26
VCCIN_64
G30
VCCIN_65

TGLLAKE-U_BGA1449
@ Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (12/16): CPU POWER (1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 14 of 130

5 4 3 2 1
 5 4 3 2 1

VCCCPUCORE CAP IN PWR SHEET VCCCPUCORE PDG LCFC EMC [16,110,112] VCCPCHCORE VCCPCHCORE

[14,109,112] VCCCPUCORE VCCCPUCORE

330uF_B2(CS) 2 HW:0/PWR:1
[4,5,14,33,34,35,36,106] VCC1R2A VCC1R2A
22uF_B2(CS) 8 HW:0/PWR:2
10uF_0402(CS) 12 HW:12/PWR:0
VCCCPUCORE
VCCPCHCORE

1 1 1 1 1 1
EMC@ EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@
C1513 C1514 C1515 C1516 C1517 C1518
D D
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
0.1U_10V_K_X5R_0201 120P_50V_J_COG_0201 15P_25V_J_NPO_0201 3.3P_25V_C_COG_0201 3.3P_25V_C_COG_0201 3.3P_25V_C_COG_0201
2 2 2 2 2 2
1 1 1 1 1 1
C1501

C1502

C1503

C1504

C1505

C1506
2 2 2 2 2 2

EMC CAPS -PLACEMENT: < 5MM FROM SOC'S VCCIN_AUX

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
VCCCPUCORE
1 1 1 1 1 1
C1507

C1508

C1509

C1510

C1511

C1512
@

2 2 2 2 2 2
1 1 1 1 1 1
EMC@ EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@
C1519 C1520 C1521 C1522 C1523 C1524
0.1U_10V_K_X5R_0201 120P_50V_J_COG_0201 15P_25V_J_NPO_0201 3.3P_25V_C_COG_0201 15P_25V_J_NPO_0201 3.3P_25V_C_COG_0201
2 2 2 2 2 2

CAPS -PLACEMENT: < 5MM FROM SOC'S VCCIN EMC CAPS -PLACEMENT: < 5MM FROM SOC'S VCCIN
C C

VCCPCHCORE CAP IN PWR SHEET VCCPCHCORE PDG LCFC

VCC1R2A CAP VCC1R2A_CPU PDG LCFC
330uF_B2(CS) 1 HW:0/PWR:0 Requirement Design
220uF_B2(CS) 1 HW:0/PWR:1 47uF_0603(CS) 2 HW:0/PWR:0
47uF_0805(CS) 3 HW:0/PWR:3 22uF_0603(CS) 0 HW:0/PWR:6
22uF_0603(CS) 12 HW:0/PWR:12 10uF_0402(SS) 8 HW:8/PWR:0
10uF_0402(CS) 15 HW:15/PWR:0 1uF_0402(CS) 8 HW:8/PWR:0
10uF_0402(SS) 10 HW:10/PWR:0
VCC1R2A

VCCPCHCORE

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
1 1 1 1 1 1 1 1

C1560

C1561

C1562

C1563

C1564

C1565

C1566

C1567
@ @ @ @ @ @ @

2 2 2 2 2 2 2 2
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

B B

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1525

C1526

C1527

C1528

C1529

C1530

C1531

C1532

C1533

C1534

C1535

C1536

C1537

C1538

C1539

@ @ @ @ @ @ @

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402
1 1 1 1 1 1 1 1

C1568

C1569

C1570

C1571

C1572

C1573

C1574

C1575
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1
C1540

C1541

C1542

C1543

C1544

C1545

C1546

C1547

C1548

C1549

@ @

2 2 2 2 2 2 2 2 2 2

A A

CAPS -PLACEMENT: < 5MM FROM SOC'S VCCIN_AUX

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (13/16): CPU POWER (2/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 15 of 130

5 4 3 2 1
 5 4 3 2 1

[7,9,11,16,51,78,85,108,110,116,117] VCC1R8_SUS VCC1R8_SUS

VCC1R8_SUS VCCPRIM_1P8
VCCPRIM_1P8 VCCPRIM_1P8

VCCA_CLKLDO_1P8 VCCA_CLKLDO_1P8
R1601 1 2 1/10W_0_5%_0603
[3,6,7,8,10,13,21,37,40,50,51,72,93,98,117,123,124] VCC3_SUS VCC3_SUS

VCCPRIM_3P3 VCCPRIM_3P3
VCCA_CLKLDO_1P8
VCCPDSW_3P3 VCCPDSW_3P3
L1601 1 2 R1602 1 2 1/10W_0_5%_0603 VCC3M
[4,13,51,52,55,56,59,84,85,86,88,102,103,104,105,106,110,116,118,119,120,123,124,125,126,127,128] VCC3M
0.68UH_DFE201610E-R68M-P2_3.1A_20%
[7,9,11,16,51,78,85,108,110,116,117] VCC1R8_SUS VCC1R8_SUS
VCC3M
VCCPGPPR VCCPGPPR
VCCPDSW_3P3
D D
[15,110,112] VCCPCHCORE VCCPCHCORE
R1605 1 2 0_0402_SP RTCVCC
[13,20] RTCVCC

[6,123] VCC1R05_OUT_FET VCC1R05_OUT_FET

VCC3_SUS VCCPRIM_3P3

R1604 1 2 0_0603_SP

VCC1R8_SUS VCCPGPPR VCCPRIM_1P8

VCCPCHCORE UCPU1N
R1603 1 2 0_0603_SP 1 1
14 OF 21
C1601 C1602
AB12 CY18 1U_10V_K_X5R_0402 1U_10V_K_X5R_0402
VCCIN_AUX_1 VCCPRIM_1P8_1 2 2
AC10 CY20
VCCIN_AUX_2 VCCPRIM_1P8_2
AE10 CY24
VCCIN_AUX_3 VCCPRIM_1P8_3
AK2 CY26
VCCIN_AUX_4 VCCPRIM_1P8_4
AR10 DA18
VCCIN_AUX_5 VCCPRIM_1P8_5
AT12 DA20
VCCIN_AUX_6 VCCPRIM_1P8_6 VCCPRIM_3P3
AU10 DA22
VCCIN_AUX_7 VCCPRIM_1P8_7
AW10 DA24
VCCIN_AUX_8 VCCPRIM_1P8_8
BV1 DA26
VCCIN_AUX_9 VCCPRIM_1P8_9
BV39 DC18 1 1
VCCIN_AUX_10 VCCPRIM_1P8_10
BW40 DC20
VCCIN_AUX_11 VCCPRIM_1P8_11 C1603 C1604
BY39 DC22
VCCIN_AUX_12 VCCPRIM_1P8_12 1U_10V_K_X5R_0402 0.1U_6.3V_K_X7R_0201
CC1 DC24
VCCIN_AUX_13 VCCPRIM_1P8_13 2 2
CD12 DC26
VCCIN_AUX_14 VCCPRIM_1P8_14
CF10 DD20
VCCIN_AUX_15 VCCPRIM_1P8_15
CG12 DD22
VCCIN_AUX_16 VCCPRIM_1P8_16
CH10 DV22
VCCIN_AUX_17 VCCPRIM_1P8_17
CJ1
VCCIN_AUX_18
CJ12 DA35
VCCIN_AUX_19 VCCPRIM_3P3_1
C CK10 DC28 C
VCCPCHCORE VCCIN_AUX_20 VCCPRIM_3P3_2
CL12 DC30 VCCA_CLKLDO_1P8 requires
VCCIN_AUX_21 VCCPRIM_3P3_3
CM10 DD30
CP1
VCCIN_AUX_22 VCCPRIM_3P3_4 "Very Clean Power Supply"
VCCIN_AUX_23 "GND Shield"
CP10 DV34 INTERNAL RAIL. VCCRTCEXT
VCCIN_AUX_24 DCPRTC
1

CR12
VCCIN_AUX_25 VCCLDOSTD_OUT_0P85 VCCA_CLKLDO_1P8
R1607 CT10 DV46 INTERNAL RAIL.
VCCIN_AUX_26 VCCLDOSTD_0P85
1/20W_100_1%_0201 CU12
VCCIN_AUX_27
CY1 DV16
VCCIN_AUX_28 VCCA_CLKLDO_1P8_1
AK1 DC15 1 1 1 1
2

VCCIN_AUX_29 VCCA_CLKLDO_1P8_2 @

@
R1609 1 2 0_0201_SP VSSPCHCORE_SENSE_R AV9 DV28 INTERNAL RAIL. VCCDPHY_1P24 C1605 C1606 C1607 C1608
[110] VSSPCHCORE_SENSE VCCPCHCORE_SENSE VCCIN_AUX_VSSSENSE VCCDPHY_1P24 1U_10V_K_X5R_0402
R1610 1 2 0_0201_SP AT9 22U_4V_M_X5R_0402 22U_4V_M_X5R_0402 22U_4V_M_X5R_0402
[110] VCCPCHCORE_SENSE VCCIN_AUX_VCCSENSE VCCDSW_1P05 2 2 2 2
@ DD38 INTERNAL RAIL.
R1611 1 2 1/20W_100K_5%_0201 VNNEXT_1P05 VCCDSW_1P05
DD17
VCC_VNNEXT_1P05_1 INTERNAL RAIL.
DD18 BR3 VCC1R05_OUT_FET
BYPASS Power
@ Rail VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET_1
BR4
R1612 1 2 1/20W_100K_5%_0201 V1R05EXT_1P05 VCC1P05_OUT_FET_2
DA15 BT5 VCCST & VCCSTG Power source
VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET_3
DA17
VCC_V1P05EXT_1P05_2 RTCVCC
DA31 INTERNAL RAIL.
VCCPRIM1P05_OUT_PCH_1
1

DB39 DC33
R1613 GPP_B2/VRALERT# VCCPRIM1P05_OUT_PCH_2 VCC1R05_OUT_PCH 1 TP1601 Test_Point_12MIL
DV12 DC31
GPP_F22/VNN_CTRL VCCPRIM1P05_OUT_PCH_3 VCCPDSW_3P3
1/20W_100_1%_0201 DT12
GPP_F23/V1P05_CTRL VCCRTC_CPU R1615 1 2 0.5W_0.02_1%_0603_50PPM/C
DC35
VCCPCHCORE_VID0 DB37 VCCRTC
[110] VCCPCHCORE_VID0 DD37
2

VCCPCHCORE_VID1 DB38 GPP_B0/CORE_VID0 VCCDSW_3P3

[110] VCCPCHCORE_VID1 DA28 1
GPP_B1/CORE_VID1 VCCPGPPR
CY31 C1609
VCCPRIM_3P3_5 VCCPGPPR 1U_25V_K_X5R_0402
CY33
VCCPRIM_3P3_6 2
CV39
VCCPRIM_1P8_18
VID Table :
AP12 RSVD79 1 TP1602 Test_Point_12MIL 1 1
RSVD_1
VID[1] VID[0] VCCPCHCORE
@ C1610 @ C1611
0 0 0.1U_10V_K_X5R_0201 1U_25V_K_X5R_0402
0 TGLLAKE-U_BGA1449 2 2
@
0 1 1.1 RTCVCC
B B
1 0 1.65
1 1 1.8

1 1
C1612 C1613
0.1U_10V_K_X5R_0201 1U_25V_K_X5R_0402
2 2

PCH POWER RAIL DE-COUPLING

VCCRTCEXT VCCLDOSTD_OUT_0P85 VCCDPHY_1P24 VCCDSW_1P05

A 1 1 1 1 A

C1614 C1615 C1616 C1617

0.1U_6.3V_K_X5R_0201 2.2U_6.3V_K_X5R_0402 4.7U_6.3V_M_X5R_0402 1U_10V_K_X5R_0402
2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (1/16): PCH POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 16 of 130

5 4 3 2 1
 5 4 3 2 1

UCPU1R
UCPU1P UCPU1Q 18 OF 21
16 OF 21 17 OF 21

DP53 K34
D VSS_2 VSS_46 D
A27 B19 BY44 CY44 DR11 K48
VSS_223 VSS_289 VSS_109 VSS_169 VSS_3 VSS_47
A32 B2 BY45 CY45 DR16 K5
VSS_224 VSS_290 VSS_110 VSS_170 VSS_4 VSS_48
A45 B23 BY47 CY47 DR22 L22
1 NCTF_C_A53_2 VSS_225 VSS_291 VSS_111 VSS_171 VSS_5 VSS_49
A49 B27 BY49 CY5 DR28 L28
VSS_226 VSS_292 VSS_112 VSS_172 VSS_6 VSS_50
TP1701 AA41 B32 BY9 D27 DR34 L34
VSS_227 VSS_293 VSS_113 VSS_173 VSS_7 VSS_51
Test_Point_40MIL AA48 B36 C13 D32 DR40 L39
VSS_228 VSS_294 VSS_114 VSS_174 VSS_8 VSS_52
AB5 B39 C19 D36 DR46 L41
VSS_229 VSS_295 VSS_115 VSS_175 VSS_9 VSS_53
AB7 B42 C23 D42 DT4 L42
VSS_230 VSS_296 VSS_116 VSS_176 VSS_10 VSS_54
AB8 B48 CA48 D49 DT50 L44
VSS_231 VSS_297 NCTF_C_A53_1 1 VSS_117 VSS_177 VSS_11 VSS_55
AC44 B52 CB41 D5 DU11 L45
VSS_232 VSS_298 VSS_118 VSS_178 VSS_12 VSS_56
AC49 B8 TP1702 CC10 DA30 DU16 L47
VSS_233 VSS_299 VSS_119 VSS_179 VSS_13 VSS_57
AD4 BA48 Test_Point_40MIL CC3 DA33 DU22 L49
VSS_234 VSS_300 VSS_120 VSS_180 VSS_14 VSS_58
AD48 BA53 CC5 DA53 DU28 M1
VSS_235 VSS_301 VSS_121 VSS_181 VSS_15 VSS_59
AD8 BB4 CD44 DC17 DU34 M2
VSS_236 VSS_302 VSS_122 VSS_182 VSS_16 VSS_60
AF4 BB8 CD48 DD15 DU40 M50
VSS_237 VSS_303 VSS_123 VSS_183 VSS_17 VSS_61
AF8 BC1 CD7 DD24 DU46 N22
VSS_238 VSS_304 VSS_124 VSS_184 1NCTF_C_DV1 VSS_18 VSS_62
AG41 BC2 CE49 DD26 DV1 N28
VSS_239 VSS_305 VSS_125 VSS_185 VSS_19 VSS_63
AG42 BD12 CG48 DD28 DV40 N34
VSS_240 VSS_306 VSS_126 VSS_186 TP1703 VSS_20 VSS_64
AG44 BD4 CG51 DD31 DV52 N39
VSS_241 VSS_307 VSS_127 VSS_187 Test_Point_12MIL VSS_21 VSS_65
AG45 BD48 CG52 DD33 DW51 N41
VSS_242 VSS_308 VSS_128 VSS_188 VSS_22 VSS_66
AG47 BD8 CG9 DD35 E13 N48
VSS_243 VSS_309 VSS_129 VSS_189 VSS_23 VSS_67
AG48 BF39 CH41 DD39 E19 P11
VSS_244 VSS_310 VSS_130 VSS_190 VSS_24 VSS_68
AG53 BF4 CH42 DD45 E35 P14
VSS_245 VSS_311 VSS_131 VSS_191 VSS_25 VSS_69
C
AH4 BF41 CH44 DD51 E48 P16 C
VSS_246 VSS_312 VSS_132 VSS_192 VSS_26 VSS_70
AH8 BF42 CH45 DD52 G22 P18
VSS_247 VSS_313 VSS_133 VSS_193 VSS_27 VSS_71
AK12 BF44 CH47 DE3 G28 P20
VSS_248 VSS_314 VSS_134 VSS_194 VSS_28 VSS_72
AK4 BF45 CJ3 DE5 G34 P22
VSS_249 VSS_315 VSS_135 VSS_195 VSS_29 VSS_73
AK48 BF47 CJ5 DF19 G39 P33
VSS_250 VSS_316 VSS_136 VSS_196 VSS_30 VSS_74
AK5 BF5 CJ9 DF37 G48 P35
VSS_251 VSS_317 VSS_137 VSS_197 VSS_31 VSS_75
AK7 BF7 CK39 DG15 G51 P4
VSS_252 VSS_318 VSS_138 VSS_198 VSS_32 VSS_76
AK8 BF8 CK48 DG21 G52 P49
VSS_253 VSS_319 VSS_139 VSS_199 VSS_33 VSS_77
AM1 BG48 CK53 DG27 H12 P8
VSS_254 VSS_320 VSS_140 VSS_200 VSS_34 VSS_78
AM2 BG53 CL9 DG33 H22 R39
VSS_255 VSS_321 VSS_141 VSS_201 VSS_35 VSS_79
AM4 BH1 CN12 DG39 H28 R44
VSS_256 VSS_322 VSS_142 VSS_202 VSS_36 VSS_80
AM8 BH2 CN48 DG45 H34 T19
VSS_257 VSS_323 VSS_143 VSS_203 VSS_37 VSS_81
AN41 BH4 CN51 DG5 H8 T29
VSS_258 VSS_324 VSS_144 VSS_204 VSS_38 VSS_82
AN42 BH8 CN52 DG53 J39 T33
VSS_259 VSS_325 VSS_145 VSS_205 VSS_39 VSS_83
AN44 BK12 CN9 DG6 J49 T4
VSS_260 VSS_326 VSS_146 VSS_206 VSS_40 VSS_84
AN45 BK4 CP3 DJ1 K16 T48
VSS_261 VSS_327 VSS_147 VSS_207 VSS_41 VSS_85
AN47 BK48 CP41 DJ2 K18 T8
VSS_262 VSS_328 VSS_148 VSS_208 VSS_42 VSS_86
AN48 BK8 CP42 DJ4 K20 U19
VSS_263 VSS_329 VSS_149 VSS_209 VSS_43 VSS_87
AN53 BL49 CP44 DK51 K22 U25
VSS_264 VSS_330 VSS_150 VSS_210 VSS_44 VSS_88
AP4 BM1 CP45 DL3 K28 U39
VSS_265 VSS_331 VSS_151 VSS_211 VSS_45 VSS_89
AP8 BM4 CP5 DL5 U49
VSS_266 VSS_332 VSS_152 VSS_212 VSS_90
AT4 BM41 CR48 DM10 V19
VSS_267 VSS_333 VSS_153 VSS_213 VSS_91
AT48 BM42 CR53 DM15 V4
VSS_268 VSS_334 VSS_154 VSS_214 VSS_92
AT51 BM44 CR9 DM21 V8
VSS_269 VSS_335 VSS_155 VSS_215 VSS_93
B AT8 BM45 CT5 DM27 W1 B
VSS_270 VSS_336 VSS_156 VSS_216 VSS_94
AV12 BM47 CU4 DM33 W16
VSS_271 VSS_337 VSS_157 VSS_217 VSS_95
AV39 BM8 CU9 DM39 W26
VSS_272 VSS_338 VSS_158 VSS_218 VSS_96
AV4 BN48 CV10 DM4 W30
VSS_273 VSS_339 VSS_159 VSS_219 VSS_97
AV5 BP41 CV48 DM45 W39
VSS_274 VSS_340 VSS_160 VSS_220 NCTF_C_DW1_2 1 VSS_98
AV7 BP49 CV5 DN1 W41
VSS_275 VSS_341 VSS_161 VSS_221 VSS_99
AV8 BP5 CV51 DN2 TP1704 W42
VSS_276 VSS_342 VSS_162 VSS_222 VSS_100
AW1 BP50 CV52 Test_Point_40MIL W44
VSS_277 VSS_343 VSS_163 VSS_101
AW2 BP7 CY17 W45
VSS_278 VSS_344 VSS_164 VSS_102
AW48 BT44 CY22 W47
VSS_279 VSS_345 VSS_165 VSS_103
AY4 BT48 CY35 W48
VSS_280 VSS_346 VSS_166 VSS_104
AY41 BU49 CY41 Y4
VSS_281 VSS_347 VSS_167 VSS_105
AY42 BV3 CY42 Y49
VSS_282 VSS_348 VSS_168 VSS_106
AY44 BV48 Y50
VSS_283 VSS_349 VSS_107
AY45 BV5 Y8
VSS_284 VSS_350 VSS_108
AY47 BW10 TGLLAKE-U_BGA1449
VSS_285 VSS_351
AY8 BY41
VSS_286 VSS_352 @
AY9 BY42 TGLLAKE-U_BGA1449
VSS_287 VSS_353
B13
VSS_288 @

TGLLAKE-U_BGA1449
@
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (15/16): GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 17 of 130

5 4 3 2 1
 5 4 3 2 1

PROCESSOR CFG STRAPS [14,85] VCCIO_OUT VCCIO_OUT

UCPU1T
20 OF 21
eDP Enable
D
T15 A51 D
CFG_15 RSVD_TP_7
1:Disable MIPI60_CFG14
MIPI60_CFG13
V17
U15
CFG_14 RSVD_TP_8
B51
CFG4 MIPI60_CFG12 K11
CFG_13
C1
* 0:Enable(Default) MIPI60_CFG11
MIPI60_CFG10
MIPI60_CFG9
K12
K9
T17
CFG_12
CFG_11
CFG_10
RSVD_TP_9
RSVD_TP_10
D2

CP39
MIPI60_CFG8 CFG_9 RSVD_TP_11
K7 CU40
MIPI60_CFG7 CFG_8 RSVD_TP_12
H7 AK9
MIPI60_CFG4 R1801 1 2 1/20W_1K_5%_0201 CFG_7 RSVD_12
K8
CFG_6
H9 AH9
MIPI60_CFG4 CFG_5 RSVD_13
E6
MIPI60_CFG3 CFG_4
H5 DW6
MIPI60_CFG2 CFG_3 RSVD_14
E9 DV6
MIPI60_CFG1 CFG_2 RSVD_15
D9
MIPI60_CFG0 CFG_1
E7 DV4
CFG_0 RSVD_TP_13
DW3
CFG_RCOMP RSVD_TP_14
B5
CFG_RCOMP
PEG Deferred Link Training U17
RSVD_TP_15
DU1
DT2
CFG_17 RSVD_TP_16
H11

CFG7 * 1:Enabled Y1
M4
CFG_16

BPM#_3
RSVD_TP_17
RSVD_TP_18
DW2
DV2

MIPI60_BPM_1 AB4 BPM#_2 NCTF_C_A1_1 TP1821 1 Test_Point_40MIL

E1
0:Disabled Y2
BPM#_1
BPM#_0
RSVD_TP_19
RSVD_TP_20
F1 NCTF_C_A1_2 TP1822 1 Test_Point_40MIL

A3 AB2
VCCIO_OUT RSVD_6 RSVD_16
B3
RSVD_7
DR1
TCP0_MBIAS_RCOMP RSVD_TP_21
AR2 DR2
R1802 1 2 1/20W_1K_5%_0201 TCP0_MBIAS_RCOMP RSVD_TP_22
AL10
C RSVD_TP_2 C
AM12 DR53
MIPI60_CFG7 R1803 1 @ 2 1/20W_1K_5%_0201 RSVD_TP_3 RSVD_TP_23
AH12 DW5
RSVD_TP_4 RSVD_TP_24
AJ10
RSVD_TP_5
AR1 DV51
RSVD_TP_6 VSS_1
DW52 NCTF_C_DW53_1 TP1827 1 Test_Point_12MIL
TP_3
BN10 DV53 NCTF_C_DW53_2 TP1828 1 Test_Point_12MIL
RSVD_8 TP_4
BM12 W34
RSVD_9 RSVD_17
DD13 V35
RSVD_10 RSVD_18

1
DF13
R1820 RSVD_11 SKTOCC TP1829 1 Test_Point_40MIL
D52
1/20W_2.2K_1%_0201 SKTOCC#
PEG60 Lane Reversal
TGLLAKE-U_BGA1449
2

@
1:Normal (Default)
CFG14 *
0:Reversal teknisi-indonesia.com
VCCIO_OUT

R1804 1 2 1/20W_1K_5%_0201
UCPU1S
MIPI60_CFG14 R1805 1 2 1/20W_1K_5%_0201 19 OF 21
@

DF53 C53
RSVD_19 RSVD_23
T35
Reserve for FDIM RSVD_24
DF52 E53
RSVD_20 RSVD_25
CF39
B VCCIO_OUT Test_Point_12MIL 1 TP1830 PCH_IST_TP_1 RSVD_26 B
DT52 U35
Test_Point_12MIL 1 TP1831 PCH_IST_TP_0 PCH_IST_TP_1 RSVD_27 UCPU1D
DU53 F53
PCH_IST_TP_0 RSVD_28
B53 4 OF 21
RSVD_29
DF50 AP9
MIPI60_CFG1 R1806 1 2 1/20W_1K_1%_0201 RSVD_21 RSVD_30
DF49 A52
RSVD_22 RSVD_31
DV24
MIPI60_CFG2 R1807 1 2 1/20W_1K_1%_0201 RSVD_2
CY30 BF12 DW47
RSVD_TP_25 RSVD_TP_28 RSVD_3
CY15 V21 DW49
MIPI60_CFG3 R1808 1 2 1/20W_1K_1%_0201 RSVD_TP_26 RSVD_TP_29 RSVD_4
W20 A48
RSVD_TP_30 RSVD_5
D4 U37
RSVD_TP_27 RSVD_TP_31
CD39
MIPI60_CFG9 R1809 1 2 1/20W_1K_1%_0201 RSVD_TP_32
A6 U21 TGLLAKE-U_BGA1449
IST_TP_1 RSVD_TP_33
A4 CB39
MIPI60_CFG10 R1810 1 2 1/20W_1K_1%_0201 IST_TP_0 RSVD_32 @
BB12
RSVD_TP_34
W37
MIPI60_CFG11 R1811 1 2 1/20W_1K_1%_0201 RSVD_TP_35
AY12
RSVD_TP_36
W38
MIPI60_BPM_1 R1812 1 @ 2 1/20W_1K_1%_0201 RSVD_TP_37
U38
RSVD_TP_38
CY28
RSVD_TP_39
MIPI60_CFG0 R1813 1 @ 2 1/20W_1K_1%_0201
TGLLAKE-U_BGA1449
MIPI60_CFG8 R1814 1 @ 2 1/20W_1K_1%_0201
@
MIPI60_CFG12 R1815 1 @ 2 1/20W_1K_1%_0201

MIPI60_CFG13 R1816 1 @ 2 1/20W_1K_1%_0201

MIPI60_CFG0 R1817 1 @ 2 1/20W_1K_1%_0201

A A

MIPI60_CFG9 R1818 1 @ 2 1/20W_1K_1%_0201

Security Classification LC Future Center Secret Data Title

CFG_RCOMP R1819 1 2 1/20W_49.9_1%_0201
Issued Date 2015/01/12 Deciphered Date 2016/01/12 CPU (16/16): CFG/RESERVED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 18 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 19 of 130

5 4 3 2 1
 5 4 3 2 1

RTCVCC RTCVCC [13,16]

D D

RTC CONN.
VCC3SW
RTCVCC

RTC External Circuit

RTCBATT(R2001 D2003 )

2
D2001
RTCVCC CUS357_SOD323-2 2
Trace width = 20mils @ C2001

1
1U_6.3V_M_X5R_0201
1
C C

D2002
D2003 2 1

RB751V40T1G_SOD323-2

2
R2001
1/20W_1K_5%_0201

1
1 2 -RTCRST
-RTCRST [12]
R2002 1/20W_20K_5%_0201
2019/9/27
D2002"SCS00028500" change to "SCS00006S00
" for the RTC leakage current 2
C2002
1U_6.3V_K_X5R_0402_MURATA

2
JCMOS1
1
SHORT PADS
JRTC1 @_JCMOS1_S

1
1 R2001
1 2
2
3
GND1 4
ME@ GND2
HIGHS_WS23020-S0291-HF

1 2 -SRTCRST
-SRTCRST [12]
R2003 1/20W_20K_5%_0201

2
C2003
B B
1U_6.3V_K_X5R_0402_MURATA

2
JME1
1
SHORT PADS
@_JME1_S

1
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 RTC BATTERY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 20 of 130

5 4 3 2 1
 5 4 3 2 1

TABLE of SPI ROM (U2101) RPMC for non-vPro VCC3_SUS_SPI VCC3_SUS

Vendor LCFC P/N Description
Winbond SA0000A1Q00 S IC FL 256M W25R256JVEIQ WSON 8P SPI

1
RB520CM-30T2R_VMN2M2
2
R2101
MXIC SA0000A1R00 S IC FL 256M MX77L25650FZ4I42 WSON 8P @ 1/16W_0_5%_0402
GD SA0000A1S00 S IC FL 256M GD25R256DYIGR WSON 8P SPI

1
D2101
D D

2
Close pin8
2
C2101

0.1U_6.3V_K_X5R_0201_MURATA
1

32MB(256Mb)
U2101
-SPI_CS0 R2106 1 2 0_0402_SP -SPI_CS0_R 1 8 VCC3_SUS_SPI
[7] -SPI_CS0 /CS VCC
SPI_MISO_IO1 R2107 1 @ 2 1/20W_33_5%_0201 SPI_MISO_IO1_0_R 2 7 SPI_IO3_0_R R2108 1 @ 2 1/20W_33_5%_0201 SPI_IO3
[7,98] SPI_MISO_IO1 DO(IO1) /HOLD(IO3) SPI_IO3 [7]
SPI_IO2 R2109 1 @ 2 1/20W_33_5%_0201 SPI_IO2_0_R 3 6 SPI_CLK_0_R R2111 1 @ 2 1/20W_33_5%_0201 SPI_CLK
[7] SPI_IO2 /WP(IO2) CLK SPI_CLK [7,98]
4 5 SPI_MOSI_IO0_R R2110 1 @ 2 1/20W_33_5%_0201 SPI_MOSI_IO0
GND DI(IO0) SPI_MOSI_IO0 [7,98]
C C

W25R256JVEIQ_WSON8_8X6
SA0000A1Q00
@

TABLE of SPI ROM (U2102) non RPMC for vPro

Vendor LCFC P/N Description
U2102
MXIC SA00008J400 S IC FL 256M MX25L25673GM2I-08G SOP 8P
-SPI_CS0_R 1 8 VCC3_SUS_SPI
Winbond SA00008WZ00 S IC FL 256M W25Q256JVEIQ WSON 8P SPI SPI_MISO_IO1_0_R 2 CS# VCC 7 SPI_IO3_0_R
SPI_IO2_0_R 3 SO/SIO1 SIO3 6 SPI_CLK_0_R VCC3_SUS_SPI
GD SA00009R800 S IC FL 256M GD25B256DYIGR WSON 8P SPI 4 SIO2 SCLK 5 SPI_MOSI_IO0_R
GND SI/SIO0
32MB (256Mb) 200MIL SOIC8 Close pin8
MX25L25673GM2I-08G_SO8
MACRONIX MX25L25673GM2I-08G
@
MACRONIX MX25L25673GM2I-10G VPRO@ 2
C2102
32MB (256Mb) 8x6mm WSON8 (Optional) 0.1U_6.3V_K_X5R_0201_MURATA
WINBOND W25Q256JVEIQ 1
B B

VPRO@ U2104
-SPI_CS1 R2112 1 2 1/16W_0_5%_0402 -SPI_CS1_R 1 8 VCC3_SUS_SPI
[7] -SPI_CS1 /CS VCC
SPI_MISO_IO1 R2113 1 @ 2 1/20W_33_5%_0201 SPI_MISO_IO1_1_R 2 7 SPI_IO3_1_R R2115 1 @ 2 1/20W_33_5%_0201 SPI_IO3
SPI_IO2 R2114 1 @ 2 1/20W_33_5%_0201 SPI_IO2_1_R 3 DO(IO1) /HOLD OR /RESET(IO3) 6 SPI_CLK_1_R R2116 1 @ 2 1/20W_33_5%_0201 SPI_CLK
/WP(IO2) CLK 5 SPI_MOSI_IO0_1_R R2117 1 @ 2 1/20W_33_5%_0201 SPI_MOSI_IO0
4 DI(IO0) 9
GND PAD_GND
MX77L12850FZNI40_WSON8_6X5
SA0000B1400
VPRO@

vPro TABLE (VPRO@)

LCFC P/N SD00000LHYT TABLE of U2104
Description 1/20W_33_5%_0201 Vendor P/N LCFC P/N
R2107,R2108,R2109,R2110,R2111 MXIC MX77L12850FZNI40 WSON SA0000B1400
Location R2113,R2114,R2115,R2116,R2117 Winbond W25R128JVPIQ WSON SA0000B2Z00
A GD GD25R127DWIG WSON SA0000B3C00 A
Non-vPro TABLE (NVPRO@)
LCFC P/N SD00000LIYT
Description 1/20W_56_5%_0201
Security Classification LC Future Center Secret Data Title
Location R2107,R2108,R2109,R2110,R2111
Issued Date 2015/01/12 Deciphered Date 2016/01/12 SPI FLASH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 21 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

www.teknisi-indonesia.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 22 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 23 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 24 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 25 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 26 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 27 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 28 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 29 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 30 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 31 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 32 of 130

5 4 3 2 1
 5 4 3 2 1

[5] DDR1_MA[16:0] [3,7,8,10,12,13,34,35,36,37,51,52,53,55,63,64,66,70,73,76,78,85,88,89,91,92,93,97,98,101,127] VCC3B VCC3B

[5] DDR1_DQ0_[7:0] [34,35,36,107] VCC2R5A VCC2R5A

[5] DDR1_DQ1_[7:0] [4,5,14,15,34,35,36,106] VCC1R2A VCC1R2A

[5] DDR1_DQ2_[7:0] [34,35,36,106] VCC0R6B VCC0R6B

[5] DDR1_DQ3_[7:0] [5,34] M_B_VREF_CA M_B_VREF_CA

[5] DDR1_DQ4_[7:0]
VCC1R2A VCC1R2A
[5] DDR1_DQ5_[7:0]
VCC1R2A VCC1R2A
[5] DDR1_DQ6_[7:0]
JDIMM1A JDIMM1B
[5] DDR1_DQ7_[7:0]
D D
1 2 DDR1_MA3 131 132 DDR1_MA2
DDR1_DQ7_2 3 VSS_1 VSS_2 4 DDR1_DQ7_3 DDR1_MA1 133 A3 A2 134 JDDR1_EVENT_N
5 DQ5 DQ4 6 135 A1 EVENT_n/NF 136
DDR1_DQ7_6 7 VSS_3 VSS_4 8 DDR1_DQ7_5 DDR1_CLK0_DP 137 VDD_9 VDD_10 138 DDR1_CLK1_DP
DQ1 DQ0 [5] DDR1_CLK0_DP CK0_t CK1_t/NF DDR1_CLK1_DP [5]
9 10 DDR1_CLK0_DN 139 140 DDR1_CLK1_DN
VSS_5 VSS_6 [5] DDR1_CLK0_DN CK0_c CK1_c/NF DDR1_CLK1_DN [5]
DDR1_DQS7_DN 11 12 141 142
[5] DDR1_DQS7_DN DDR1_DQS7_DP DQS0_C DM0_n/DBl0_n DDR1_PARITY VDD_11 VDD_12 DDR1_MA0
13 14 143 144
[5] DDR1_DQS7_DP DQS0_t VSS_7 [5] DDR1_PARITY Parity A0
15 16 DDR1_DQ7_7
DDR1_DQ7_4 17 VSS_8 DQ6 18
19 DQ7 VSS_9 20 DDR1_DQ7_1 DDR1_BA1 145 146 DDR1_MA10
VSS_10 DQ2 [5] DDR1_BA1 BA1 A10/AP
DDR1_DQ7_0 21 22 147 148
23 DQ3 VSS_11 24 DDR1_DQ5_1 DDR1_CS0 149 VDD_13 VDD_14 150 DDR1_BA0
VSS_12 DQ12 [5] DDR1_CS0 CS0_n BA0 DDR1_BA0 [5]
DDR1_DQ5_2 25 26 DDR1_MA14 151 152 DDR1_MA16
27 DQ13 VSS_13 28 DDR1_DQ5_0 153 A14/WE_n A16/RAS_n 154
DDR1_DQ5_7 29 VSS_14 DQ8 30 DDR1_ODT0 155 VDD_15 VDD_16 156 DDR1_MA15
DQ9 VSS_15 DDR1_DQS5_DN [5] DDR1_ODT0 DDR1_CS1 ODT0 A15/CAS_n DDR1_MA13
31 32 157 158 M_B_VREF_CA
VSS_16 DQS1_c DDR1_DQS5_DN [5] [5] DDR1_CS1 CS1_n A13
33 34 DDR1_DQS5_DP 159 160
DM1_n/DBl1_n DQS1_t DDR1_DQS5_DP [5] VDD_17 VDD_18
35 36 DDR1_ODT1 161 162
DDR1_DQ5_4 VSS_17 VSS_18 DDR1_DQ5_6 [5] DDR1_ODT1 ODT1 C0/CS2_n/NC
37 38 163 164
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 SA2_CHB_P
DDR1_DQ5_3 41 VSS_19 VSS_20 42 DDR1_DQ5_5 167 C1/CS3_n/NC SA2 168
43 DQ10 DQ11 44 DDR1_DQ1_0 169 VSS_53 VSS_54 170 DDR1_DQ1_7
DDR1_DQ4_2 45 VSS_21 VSS_22 46 DDR1_DQ4_3 171 DQ37 DQ36 172
47 DQ21 DQ20 48 DDR1_DQ1_6 173 VSS_55 VSS_56 174 DDR1_DQ1_5
DDR1_DQ4_1 49 VSS_23 VSS_24 50 DDR1_DQ4_4 175 DQ33 DQ32 176
51 DQ17 DQ16 52 DDR1_DQS1_DN 177 VSS_57 VSS_58 178
VSS_25 VSS_26 [5] DDR1_DQS1_DN DQS4_c DM4_n/DBl4_n
DDR1_DQS4_DN 53 54 DDR1_DQS1_DP 179 180
[5] DDR1_DQS4_DN DDR1_DQS4_DP DQS2_c DM2_n/DBl2_n [5] DDR1_DQS1_DP DQS4_t VSS_59 DDR1_DQ1_3
55 56 181 182
[5] DDR1_DQS4_DP DQS2_t VSS_27 VSS_60 DQ39
57 58 DDR1_DQ4_5 DDR1_DQ1_4 183 184
DDR1_DQ4_7 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDR1_DQ1_1
61 DQ23 VSS_29 62 DDR1_DQ4_6 DDR1_DQ1_2 187 VSS_62 DQ35 188
DDR1_DQ4_0 63 VSS_30 DQ18 64 189 DQ34 VSS_63 190 DDR1_DQ0_7
65 DQ19 VSS_31 66 DDR1_DQ6_6 DDR1_DQ0_0 191 VSS_64 DQ45 192
DDR1_DQ6_3 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDR1_DQ0_5
69 DQ29 VSS_33 70 DDR1_DQ6_7 DDR1_DQ0_6 195 VSS_66 DQ41 196
DDR1_DQ6_1 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDR1_DQS0_DN
DQ25 VSS_35 VSS_68 DQS5_c DDR1_DQS0_DN [5]
73 74 DDR1_DQS6_DN 199 200 DDR1_DQS0_DP
VSS_36 DQS3_c DDR1_DQS6_DP DDR1_DQS6_DN [5] DM5_n/DBl5_n DQS5_t DDR1_DQS0_DP [5]
C 75 76 201 202 C
DM3_n/DBl3_n DQS3_t DDR1_DQS6_DP [5] VSS_69 VSS_70
77 78 DDR1_DQ0_3 203 204 DDR1_DQ0_4
DDR1_DQ6_2 79 VSS_37 VSS_38 80 DDR1_DQ6_0 205 DQ46 DQ47 206
81 DQ30 DQ31 82 DDR1_DQ0_1 207 VSS_71 VSS_72 208 DDR1_DQ0_2
DDR1_DQ6_5 83 VSS_39 VSS_40 84 DDR1_DQ6_4 209 DQ42 DQ43 210
85 DQ26 DQ27 86 DDR1_DQ3_3 211 VSS_73 VSS_74 212 DDR1_DQ3_7
JDDR1_CB5 87 VSS_41 VSS_42 88 JDDR1_CB4 213 DQ52 DQ53 214
89 CB5/NC CB4/NC 90 DDR1_DQ3_2 215 VSS_75 VSS_76 216 DDR1_DQ3_6
JDDR1_CB1 91 VSS_43 VSS_44 92 JDDR1_CB0 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDR1_DQS3_DN 219 VSS_77 VSS_78 220
-M_B_DQS8 VSS_45 VSS_46 [5] DDR1_DQS3_DN DDR1_DQS3_DP DQS6_c DM6_n/DBl6_n
95 96 221 222
DQS8_c DM8_n/DBl8_n/NC [5] DDR1_DQS3_DP DQS6_t VSS_79
M_B_DQS8 97 98 223 224 DDR1_DQ3_0
99 DQS8_t VSS_47 100 JDDR1_CB6 DDR1_DQ3_4 225 VSS_80 DQ54 226
JDDR1_CB2 101 VSS_48 CB6/NC 102 227 DQS5 VSS_81 228 DDR1_DQ3_1
103 CB2/NC VSS_49 104 JDDR1_CB7 DDR1_DQ3_5 229 VSS_82 DQ50 230
JDDR1_CB3 105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDR1_DQ2_0
107 CB3/NC VSS_51 108 -DRAMRST DDR1_DQ2_7 233 VSS_84 DQ60 234
VSS_52 RESET_n -DRAMRST [4,35] DQ61 VSS_85
DDR1_CKE0 109 110 DDR1_CKE1 235 236 DDR1_DQ2_2 VCC0R6B
[5] DDR1_CKE0 CKE0 CKE1 DDR1_CKE1 [5] DDR1_DQ2_5 VSS_86 DQ57
111 112 237 238
DDR1_BG1 113 VDD_1 VDD_2 114 DDR1_ACT_N 239 DQ56 VSS_87 240 DDR1_DQS2_DN
[5] DDR1_BG1 BG1 ACT_n DDR1_ACT_N [5] VSS_88 DQS7_c DDR1_DQS2_DN [5]
DDR1_BG0 115 116 DDR1_ALERT_N 241 242 DDR1_DQS2_DP
[5] DDR1_BG0 BG0 ALERT_n DDR1_ALERT_N [5] DM7_n/DBl7_n DQS7_t DDR1_DQS2_DP [5]
117 118 243 244
DDR1_MA12 119 VDD_3 VDD_4 120 DDR1_MA11 DDR1_DQ2_3 245 VSS_89 VSS_90 246 DDR1_DQ2_6
DDR1_MA9 121 A12 A11 122 DDR1_MA7 VCC2R5A VCC3B 247 DQ62 DQ63 248
123 A9 A7 124 DDR1_DQ2_1 249 VSS_91 VSS_92 250 DDR1_DQ2_4
DDR1_MA8 125 VDD_5 VDD_6 126 DDR1_MA5 251 DQ58 DQ59 252
DDR1_MA6 127 A8 A5 128 DDR1_MA4 SMB_CLK_3B 253 VSS_93 VSS_94 254 SMB_DATA_3B
A6 A4 [35,89,93] SMB_CLK_3B SCL SDA SA0_CHB_P SMB_DATA_3B [35,89,93]
129 130 1 255 256
VDD_7 VDD_8 257 VDDSPD SA0 258
C3301 259 VPP_1 VTT 260 SA1_CHB_P
0.1U_25V_K_X5R_0402 VPP_2 SA1
ARGOS_D4ARL-26010-1P40 2 EMC_NS@ 261 262
GND_1 GND_2
ME@
ARGOS_D4ARL-26010-1P40
Close DDR DIMM ME@

B B

VCC1R2A
1

@ R3301 @ R3302 @ R3303 @ R3307

1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201
VCC3B VCC3B VCC3B
2

1
JDDR1_CB0
JDDR1_CB1 R3304 R3305 R3306
JDDR1_CB2 @ 1/16W_10K_5%_0402 1/16W_10K_5%_0402 @ 1/16W_10K_5%_0402
JDDR1_CB3

2
SA0_CHB_P SA1_CHB_P SA2_CHB_P
1

@ R3308 @ R3309 @ R3310 @ R3314

2
1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201
R3311 R3312 R3313
0_0402_SP @ 1/16W_0_5%_0402 0_0402_SP
2

JDDR1_CB4

1
JDDR1_CB5
JDDR1_CB6
JDDR1_CB7
1

A @ R3315 @ R3316 R3317 SPD Address = 52H A

1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201
2

JDDR1_EVENT_N
-M_B_DQS8
M_B_DQS8

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 DDR4 SUB CHANNEL-B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 33 of 130

5 4 3 2 1
 5 4 3 2 1

VCC1R2A PDG LCFC VCC0R6B PDG LCFC

[33,35,36,106] VCC0R6B VCC0R6B
1uF_0402 8 HW:8/PWR:0 1uF_0402 2 HW:2/PWR:0
[4,5,14,15,33,35,36,106] VCC1R2A VCC1R2A
10uF_0603 8 HW:8/PWR:0 10uF_0603 1 HW:1/PWR:0
[33,35,36,107] VCC2R5A VCC2R5A
330uF_B2 1 HW:0/PWR:0
VCC2R5A PDG LCFC [3,7,8,10,12,13,33,35,36,37,51,52,53,55,63,64,66,70,73,76,78,85,88,89,91,92,93,97,98,101,127] VCC3B VCC3B

JDDR1.255 PDG LCFC 1uF_0402 1 HW:1/PWR:0 [5,33] M_B_VREF_CA M_B_VREF_CA

0.1uF_0402 1 HW:1/PWR:0 10uF_0603 1 HW:1/PWR:0

2.2uF_0402 1 HW:1/PWR:0

D D

VCC1R2A

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402
2 2 2 2 2 2 2 2

C3401

C3402

C3403

C3404

C3405

C3406

C3407

C3408
@

1 1 1 1 1 1 1 1

VCC1R2A VCC1R2A

330U_2.5V_M_B2_ESR9M_H1.9
1

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

@ C3417
2 2 2 2 2 2 2 2 +

C3409

C3410

C3411

C3412

C3413

C3414

C3415

C3416
@

C
1 1 1 1 1 1 1 1 2 C

VCC0R6B VCC0R6B VCC2R5A VCC1R2A

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
2 2 2 2 2 2 2 2 2 2
C3418

C3419

C3420

C3421

C3422

EMC_NS@ C3423

EMC_NS@ C3424

EMC_NS@ C3425

EMC_NS@ C3426

EMC_NS@ C3427
1 1 1 1 1 1 1 1 1 1

B B

VCC3B
M_B_VREF_CA
VCC2R5A VCC3B VCC1R2A
2.2U_10V_K_X5R_0402

0.1U_6.3V_K_X5R_0201

2 2

2.2U_10V_K_X5R_0402
C3428

C3429

0.1U_6.3V_K_X5R_0201
2 2

C3436

C3437
47P_25V_J_NPO_0201

100P_25V_J_NPO_0201

47P_25V_J_NPO_0201

100P_25V_J_NPO_0201

47P_25V_J_NPO_0201

100P_25V_J_NPO_0201
1 1 1 1 1 1 1 1
RF@ C3430

RF@ C3431

RF@ C3432

RF@ C3433

RF@ C3434

RF@ C3435
1@ 1

2 2 2 2 2 2

JDDR1.255
Near JDDR1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DDR4 SUB CHANNEL-B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 34 of 130

5 4 3 2 1
 5 4 3 2 1

[3,7,8,10,12,13,33,34,36,37,51,52,53,55,63,64,66,70,73,76,78,85,88,89,91,92,93,97,98,101,127] VCC3B VCC3B

[4] DDR0_MA[16:0]
[33,34,36,107] VCC2R5A VCC2R5A
[4] DDR0_DQ0_[7:0]
[33,34,36,106] VCC0R6B VCC0R6B
[4] DDR0_DQ1_[7:0]
[4,36] M_A_VREF_CA M_A_VREF_CA
[4] DDR0_DQ2_[7:0]
[4,5,14,15,33,34,36,106] VCC1R2A VCC1R2A
[4] DDR0_DQ3_[7:0]

[4] DDR0_DQ4_[7:0]

[4] DDR0_DQ5_[7:0]
VCC1R2A VCC1R2A VCC1R2A VCC1R2A
[4] DDR0_DQ6_[7:0]
JDIMM2A JDIMM2B
D [4] DDR0_DQ7_[7:0] D
1 2 DDR0_MA3 131 132 DDR0_MA2
DDR0_DQ7_2 3 VSS_1 VSS_2 4 DDR0_DQ7_3 DDR0_MA1 133 A3 A2 134 JDDR0_EVENT_N
5 DQ5 DQ4 6 135 A1 EVENT_n/NF 136
DDR0_DQ7_6 7 VSS_3 VSS_4 8 DDR0_DQ7_5 DDR0_CLK0_DP 137 VDD_9 VDD_10 138 DDR0_CLK1_DP
DQ1 DQ0 [4] DDR0_CLK0_DP CK0_t CK1_t/NF DDR0_CLK1_DP [4]
9 10 DDR0_CLK0_DN 139 140 DDR0_CLK1_DN
DDR0_DQS7_DN VSS_5 VSS_6 [4] DDR0_CLK0_DN CK0_c CK1_c/NF DDR0_CLK1_DN [4]
11 12 141 142
[4] DDR0_DQS7_DN DQS0_C DM0_n/DBl0_n VDD_11 VDD_12
DDR0_DQS7_DP 13 14 DDR0_PARITY 143 144 DDR0_MA0
[4] DDR0_DQS7_DP DQS0_t VSS_7 [4] DDR0_PARITY Parity A0
15 16 DDR0_DQ7_7
DDR0_DQ7_4 17 VSS_8 DQ6 18
19 DQ7 VSS_9 20 DDR0_DQ7_1 DDR0_BA1 145 146 DDR0_MA10
DDR0_DQ7_0 VSS_10 DQ2 [4] DDR0_BA1 BA1 A10/AP
21 22 147 148
23 DQ3 VSS_11 24 DDR0_DQ5_1 DDR0_CS0 149 VDD_13 VDD_14 150 DDR0_BA0
DDR0_DQ5_2 VSS_12 DQ12 [4] DDR0_CS0 DDR0_MA14 CS0_n BA0 DDR0_MA16 DDR0_BA0 [4]
25 26 151 152
27 DQ13 VSS_13 28 DDR0_DQ5_0 153 A14/WE_n A16/RAS_n 154
DDR0_DQ5_7 29 VSS_14 DQ8 30 DDR0_ODT0 155 VDD_15 VDD_16 156 DDR0_MA15
DQ9 VSS_15 [4] DDR0_ODT0 ODT0 A15/CAS_n
31 32 DDR0_DQS5_DN DDR0_CS1 157 158 DDR0_MA13 M_A_VREF_CA
VSS_16 DQS1_c DDR0_DQS5_DN [4] [4] DDR0_CS1 CS1_n A13
33 34 DDR0_DQS5_DP 159 160
DM1_n/DBl1_n DQS1_t DDR0_DQS5_DP [4] DDR0_ODT1 VDD_17 VDD_18
35 36 161 162
VSS_17 VSS_18 [4] DDR0_ODT1 ODT1 C0/CS2_n/NC
DDR0_DQ5_4 37 38 DDR0_DQ5_6 163 164
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 SA2_CHA_P
DDR0_DQ5_3 41 VSS_19 VSS_20 42 DDR0_DQ5_5 167 C1/CS3_n/NC SA2 168
43 DQ10 DQ11 44 DDR0_DQ1_0 169 VSS_53 VSS_54 170 DDR0_DQ1_7
DDR0_DQ4_2 45 VSS_21 VSS_22 46 DDR0_DQ4_3 171 DQ37 DQ36 172
47 DQ21 DQ20 48 DDR0_DQ1_6 173 VSS_55 VSS_56 174 DDR0_DQ1_5
DDR0_DQ4_1 49 VSS_23 VSS_24 50 DDR0_DQ4_4 175 DQ33 DQ32 176
51 DQ17 DQ16 52 DDR0_DQS1_DN 177 VSS_57 VSS_58 178
DDR0_DQS4_DN VSS_25 VSS_26 [4] DDR0_DQS1_DN DDR0_DQS1_DP DQS4_c DM4_n/DBl4_n
53 54 179 180
[4] DDR0_DQS4_DN DQS2_c DM2_n/DBl2_n [4] DDR0_DQS1_DP DQS4_t VSS_59
DDR0_DQS4_DP 55 56 181 182 DDR0_DQ1_3
[4] DDR0_DQS4_DP DQS2_t VSS_27 VSS_60 DQ39
57 58 DDR0_DQ4_5 DDR0_DQ1_4 183 184
DDR0_DQ4_7 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDR0_DQ1_1
61 DQ23 VSS_29 62 DDR0_DQ4_6 DDR0_DQ1_2 187 VSS_62 DQ35 188
DDR0_DQ4_0 63 VSS_30 DQ18 64 189 DQ34 VSS_63 190 DDR0_DQ0_7
65 DQ19 VSS_31 66 DDR0_DQ6_6 DDR0_DQ0_0 191 VSS_64 DQ45 192
DDR0_DQ6_3 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDR0_DQ0_5
69 DQ29 VSS_33 70 DDR0_DQ6_7 DDR0_DQ0_6 195 VSS_66 DQ41 196
DDR0_DQ6_1 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDR0_DQS0_DN
DQ25 VSS_35 DDR0_DQS6_DN VSS_68 DQS5_c DDR0_DQS0_DP DDR0_DQS0_DN [4]
C 73 74 199 200 C
VSS_36 DQS3_c DDR0_DQS6_DN [4] DM5_n/DBl5_n DQS5_t DDR0_DQS0_DP [4]
75 76 DDR0_DQS6_DP 201 202
DM3_n/DBl3_n DQS3_t DDR0_DQS6_DP [4] VSS_69 VSS_70
77 78 DDR0_DQ0_3 203 204 DDR0_DQ0_4
DDR0_DQ6_2 79 VSS_37 VSS_38 80 DDR0_DQ6_0 205 DQ46 DQ47 206
81 DQ30 DQ31 82 DDR0_DQ0_1 207 VSS_71 VSS_72 208 DDR0_DQ0_2
DDR0_DQ6_5 83 VSS_39 VSS_40 84 DDR0_DQ6_4 209 DQ42 DQ43 210
85 DQ26 DQ27 86 DDR0_DQ3_3 211 VSS_73 VSS_74 212 DDR0_DQ3_7
JDDR0_CB5 87 VSS_41 VSS_42 88 JDDR0_CB4 213 DQ52 DQ53 214
89 CB5/NC CB4/NC 90 DDR0_DQ3_2 215 VSS_75 VSS_76 216 DDR0_DQ3_6
JDDR0_CB1 91 VSS_43 VSS_44 92 JDDR0_CB0 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDR0_DQS3_DN 219 VSS_77 VSS_78 220
VSS_45 VSS_46 [4] DDR0_DQS3_DN DQS6_c DM6_n/DBl6_n
-M_A_DQS8 95 96 DDR0_DQS3_DP 221 222
M_A_DQS8 DQS8_c DM8_n/DBl8_n/NC [4] DDR0_DQS3_DP DQS6_t VSS_79 DDR0_DQ3_0
97 98 223 224
99 DQS8_t VSS_47 100 JDDR0_CB6 DDR0_DQ3_4 225 VSS_80 DQ54 226
JDDR0_CB2 101 VSS_48 CB6/NC 102 227 DQS5 VSS_81 228 DDR0_DQ3_1
103 CB2/NC VSS_49 104 JDDR0_CB7 DDR0_DQ3_5 229 VSS_82 DQ50 230
JDDR0_CB3 105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDR0_DQ2_0
107 CB3/NC VSS_51 108 -DRAMRST DDR0_DQ2_7 233 VSS_84 DQ60 234
DDR0_CKE0 VSS_52 RESET_n DDR0_CKE1 -DRAMRST [4,33] DQ61 VSS_85 DDR0_DQ2_2
109 110 235 236 VCC0R6B
[4] DDR0_CKE0 CKE0 CKE1 DDR0_CKE1 [4] DDR0_DQ2_5 VSS_86 DQ57
111 112 237 238
DDR0_BG1 113 VDD_1 VDD_2 114 DDR0_ACT_N 239 DQ56 VSS_87 240 DDR0_DQS2_DN
[4] DDR0_BG1 BG1 ACT_n DDR0_ACT_N [4] VSS_88 DQS7_c DDR0_DQS2_DN [4]
DDR0_BG0 115 116 DDR0_ALERT_N 241 242 DDR0_DQS2_DP
[4] DDR0_BG0 BG0 ALERT_n DDR0_ALERT_N [4] DM7_n/DBl7_n DQS7_t DDR0_DQS2_DP [4]
117 118 243 244
DDR0_MA12 119 VDD_3 VDD_4 120 DDR0_MA11 DDR0_DQ2_3 245 VSS_89 VSS_90 246 DDR0_DQ2_6
DDR0_MA9 121 A12 A11 122 DDR0_MA7 VCC2R5A VCC3B 247 DQ62 DQ63 248
123 A9 A7 124 DDR0_DQ2_1 249 VSS_91 VSS_92 250 DDR0_DQ2_4
DDR0_MA8 125 VDD_5 VDD_6 126 DDR0_MA5 251 DQ58 DQ59 252
DDR0_MA6 127 A8 A5 128 DDR0_MA4 SMB_CLK_3B 253 VSS_93 VSS_94 254 SMB_DATA_3B
A6 A4 [33,89,93] SMB_CLK_3B SCL SDA SA0_CHA_P SMB_DATA_3B [33,89,93]
129 130 255 256
VDD_7 VDD_8 257 VDDSPD SA0 258
259 VPP_1 VTT 260 SA1_CHA_P
1 VPP_2 SA1
ARGOS_D4ARL-26010-1P40 C3501 261 262
0.1U_25V_K_X5R_0402 GND_1 GND_2
ME@ 2 EMC_NS@ ARGOS_D4ARL-26010-1P40
ME@
Close DDR DIMM
B B

VCC1R2A
1

@ R3502 @ R3503 @ R3507 @ R3511

1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201
VCC3B VCC3B VCC3B
2

1
JDDR0_CB0
JDDR0_CB1 R3504 R3505 R3506
JDDR0_CB2 @ 1/16W_10K_5%_0402 @ 1/16W_10K_5%_0402 @ 1/16W_10K_5%_0402
JDDR0_CB3

2
SA0_CHA_P SA1_CHA_P SA2_CHA_P
1

@ R3512 @ R3513 @ R3514 @ R3515

2
1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201
R3508 R3509 R3510
0_0402_SP 0_0402_SP 0_0402_SP
2

JDDR0_CB4

1
JDDR0_CB5
JDDR0_CB6
JDDR0_CB7
1

A @ R3516 @ R3517 R3518 A

1/20W_240_1%_0201 1/20W_240_1%_0201 1/20W_240_1%_0201 SPD Address = 50H
2

JDDR0_EVENT_N
-M_A_DQS8
M_A_DQS8

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 DDR4 SUB CHANNEL-A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 35 of 130

5 4 3 2 1
 5 4 3 2 1

VCC1R2A PDG LCFC VCC0R6B PDG LCFC

1uF_0402 8 HW:8/PWR:0 1uF_0402 2 HW:2/PWR:0 [33,34,35,106] VCC0R6B VCC0R6B

10uF_0603 8 HW:8/PWR:0 10uF_0603 1 HW:1/PWR:0 [33,34,35,107] VCC2R5A VCC2R5A

330uF_B2 1 HW:0/PWR:0 [3,7,8,10,12,13,33,34,35,37,51,52,53,55,63,64,66,70,73,76,78,85,88,89,91,92,93,97,98,101,127] VCC3B VCC3B

VCC2R5A PDG LCFC
[4,35] M_A_VREF_CA M_A_VREF_CA
JDDR1.255 PDG LCFC 1uF_0402 1 HW:1/PWR:0
[4,5,14,15,33,34,35,106] VCC1R2A VCC1R2A
0.1uF_0402 1 HW:1/PWR:0 10uF_0603 1 HW:1/PWR:0
2.2uF_0402 1 HW:1/PWR:0

D D

VCC1R2A

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402
2 2 2 2 2 2 2 2

C3601

C3602

C3603

C3604

C3605

C3606

C3607

C3608
@

1 1 1 1 1 1 1 1

VCC1R2A VCC1R2A

330U_2.5V_M_B2_ESR9M_H1.9
1

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

@ C3617
C 2 2 2 2 2 2 2 2 C
+

C3609

C3610

C3611

C3612

C3613

C3614

C3615

C3616
1 1 1 1 1 1 1 1 2

VCC0R6B VCC0R6B VCC2R5A VCC1R2A

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

1U_6.3V_K_X5R_0402

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
2 2 2 2 2 2 2 2 2 2
C3618

C3619

C3620

C3622

C3623

EMC_NS@ C3624

EMC_NS@ C3625

EMC_NS@ C3626

EMC_NS@ C3627

EMC_NS@ C3628
1 1 1 1 1 1 1 1 1 1

B B

VCC3B
M_A_VREF_CA
VCC2R5A VCC3B VCC1R2A
2.2U_10V_K_X5R_0402

0.1U_6.3V_K_X5R_0201

2 2

2.2U_10V_K_X5R_0402
C3629

C3630

0.1U_6.3V_K_X5R_0201
2 2

C3638

C3639
47P_25V_J_NPO_0201

100P_25V_J_NPO_0201

47P_25V_J_NPO_0201

100P_25V_J_NPO_0201

47P_25V_J_NPO_0201

100P_25V_J_NPO_0201
1 1 1 1 1 1 1 1
RF@ C3631

RF@ C3632

RF@ C3633

RF@ C3635

RF@ C3636

RF@ C3637
1@ 1

2 2 2 2 2 2

JDDR1.255
Near JDDR1
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DDR4 SUB CHANNEL-A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 36 of 130

5 4 3 2 1
 5 4 3 2 1

VCC1R8VIDEO_AON Place Under GPU

4.7U_6.3V_M_X5R_0201

4.7U_6.3V_M_X5R_0201

4.7U_6.3V_M_X5R_0201
DIS@

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
R3701
1/20W_10K_5%_0201
1 1 1 1 1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

2
C3701 C3702 C3703 C3704 C3705 C3706 C3707 C3708 C3709 C3710
D3701 DIS@ 1 2 RB521CM-30T2R_VMN2M
[13,51,64,66,73,76] -PLTRST_FAR 2 2 2 2 2 2 2 2 2 2

D3702 DIS@ 1 2 RB521CM-30T2R_VMN2M -GPU_PEX_RST

[7] -GPU_RST -GPU_PEX_RST [40]
VCC1R0VIDEO

1
Place Near GPU
D @ R3750 D
1/20W_100K_5%_0201
UGPU1A

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
1/14 PCI_EXPRESS

GP107S TU117S
Test_Point_20MIL 2 2 2 2 2
TU117S GP107S
TP3701 AA22 DIS@ DIS@ DIS@ DIS@ DIS@
1 PEX_WAKE_N AA14 PEX_DVDD PEX_CVDD C3711 C3712 C3713 C3714 C3715
NC
PEX_WAKE_N
-GPU_PEX_RST AC7 AB23 1 1 1 1 1
PEX_RST_N PEX_DVDD_2 AC24
-CLKREQ_PCIE5_VGA AC6 PEX_DVDD_3 AD25
PEX_CLKREQ_N PEX_DVDD_4 AE26
AE8 PEX_DVDD_5 AE27
[12] PCIE5_CLK_100M PEX_REFCLK PEX_DVDD_6
AD8
[12] -PCIE5_CLK_100M PEX_REFCLK_N
DIS@ C3716 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L0_RXP_C AC9
[10] PCIE5_L0_RXP PCIE5_L0_RXN_C PEX_TX0
DIS@ C3717 1 2 0.22U_6.3V_K_X5R_0201 AB9 VCC1R8VIDEO_MAIN
[10] PCIE5_L0_RXN PEX_TX0_N
DIS@ C3718 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L0_TXP_C AG6 Place Under GPU
[10] PCIE5_L0_TXP PCIE5_L0_TXN_C PEX_RX0
DIS@ C3719 1 2 0.22U_6.3V_K_X5R_0201 AG7 AA10
[10] PCIE5_L0_TXN PEX_RX0_N PEX_HVDD_1 AA12
PEX_HVDD_2

4.7U_6.3V_M_X5R_0201

4.7U_6.3V_M_X5R_0201

4.7U_6.3V_M_X5R_0201
DIS@ C3720 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L1_RXP_C AB10 AA13
[10] PCIE5_L1_RXP PEX_TX1 PEX_HVDD_3

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
DIS@ C3721 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L1_RXN_C AC10 AA16
[10] PCIE5_L1_RXN PEX_TX1_N PEX_HVDD_4 AA18
DIS@ C3722 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L1_TXP_C AF7 PEX_HVDD_5 AA19
[10] PCIE5_L1_TXP PEX_RX1 PEX_HVDD_6 1 1 1 1 1 1 1 1 1 1
DIS@ C3723 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L1_TXN_C AE7 AA20 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
[10] PCIE5_L1_TXN PEX_RX1_N PEX_HVDD_7 AA21 C3730 C3724 C3731 C3725 C3732 C3726 C3733 C3734 C3727 C3735
DIS@ C3728 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L2_RXP_C AD11 PEX_HVDD_8 AB22
[10] PCIE5_L2_RXP PCIE5_L2_RXN_C PEX_TX2 PEX_HVDD_9 2 2 2 2 2 2 2 2 2 2
DIS@ C3729 1 2 0.22U_6.3V_K_X5R_0201 AC11 AC23
[10] PCIE5_L2_RXN PEX_TX2_N PEX_HVDD_10 AD24
DIS@ C3736 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L2_TXP_C AE9 PEX_HVDD_11 AE25
[10] PCIE5_L2_TXP PCIE5_L2_TXN_C PEX_RX2 PEX_HVDD_12
DIS@ C3737 1 2 0.22U_6.3V_K_X5R_0201 AF9 AF26
[10] PCIE5_L2_TXN PEX_RX2_N PEX_HVDD_13 AF27
DIS@ C3738 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L3_RXP_C AC12 PEX_HVDD_14
[10] PCIE5_L3_RXP PCIE5_L3_RXN_C PEX_TX3
DIS@ C3739 1 2 0.22U_6.3V_K_X5R_0201 AB12
[10] PCIE5_L3_RXN PEX_TX3_N
Place Near GPU
DIS@ C3740 1 2 0.22U_6.3V_K_X5R_0201 PCIE5_L3_TXP_C AG9
[10] PCIE5_L3_TXP PCIE5_L3_TXN_C PEX_RX3
DIS@ C3741 1 2 0.22U_6.3V_K_X5R_0201 AG10
[10] PCIE5_L3_TXN PEX_RX3_N
C C

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
AB13
Place Near CPU Place Near GPU AC13 PEX_TX4
PEX_TX4_N

teknisi-indonesia.com
2 2 2 2 2
AF10 DIS@ DIS@ DIS@ DIS@ DIS@
AE10 PEX_RX4 C3742 C3743 C3744 C3745 C3746
PEX_RX4_N
AD14 1 1 1 1 1
AC14 PEX_TX5 AA8
PEX_TX5_N PEX_PLL_HVDD_1 AA9
AE12 PEX_PLL_HVDD_2
AF12 PEX_RX5
PEX_RX5_N

1U_6.3V_M_X5R_0201
AC15
AB15 PEX_TX6
PEX_TX6_N 1
DIS@
AG12 C3747
AG13 PEX_RX6
PEX_RX6_N 2
AB16
AC16 PEX_TX7
PEX_TX7_N
AF13
AE13 PEX_RX7
PEX_RX7_N
AD17
AC17 PEX_TX8
PEX_TX8_N
AE15
AF15 PEX_RX8
PEX_RX8_N
AC18
AB18 PEX_TX9
PEX_TX9_N
AG15
PEX_RX9
PEX LANES 15 - 4 ARE DEFEATURED
AG16
PEX_RX9_N PEX DVDD PEX HVDD PEX PLL HVDD
AB19
VCC1R8VIDEO_AON AC19 PEX_TX10 Valule NV Q'ty LCFC Q'ty Valule NV Q'ty LCFC Q'ty Valule NV Q'ty LCFC Q'ty
B PEX_TX10_N B
AF16
1uF Under 6 Under 7 1uF Under 4 Under 7 1uF Under 1 Under 1
AE16 PEX_RX10
PEX_RX10_N 4.7uF Under 3 Under 3 4.7uF Under 3 Under 3
AD20
AC20 PEX_TX11 10uF Near 2 Near 3 10uF Near 2 Near 3
VCC3_SUS PEX_TX11_N
22uF Near 2 Near 2 22uF Near 2 Near 2
1

DIS@ AE18
R3702 AF18 PEX_RX11
PEX_RX11_N
1/20W_10K_5%_0201
AC21
AB21 PEX_TX12
2

PEX_TX12_N
5

1 AG18
P

[40,50,117,118] GFXCORE_D_PWRGD B PEX_RX12

4 AG19
Y DGFX_PWRGD [11] PEX_RX12_N
2
[118] 1R2VIDEO_PWRGD A
G

AD23
DIS@ AE23 PEX_TX13
3

U3701 PEX_TX13_N
MC74VHC1G09DFT2G_SC70-5 AF19
VCC1R8VIDEO_MAIN AE19 PEX_RX13
PEX_RX13_N
AF24
PEX_TX14
1

AE24
PEX_TX14_N
1

@ DIS@
R3708 R3709 AE21
1/20W_0_5%_0201 AF21 PEX_RX14
1/20W_10K_5%_0201 PEX_RX14_N
2

AG24
2

AG25 PEX_TX15
PEX_TX15_N
VCC3B AG21
AG22 PEX_RX15
PEX_RX15_N
VCC1R8VIDEO_AON
AF25 PEX_TERMP
PEX_TERMP
1

DIS@
1

DIS@ N18S-G5-A1_BGA603 R3705

A A
R3746 DIS@ 1/20W_2.49K_1%_0201
1

DIS@ 1/20W_10K_5%_0201
R3704
2

1/20W_10K_5%_0201
2
2
2

-CLKREQ_PCIE5_VGA 3 1
-CLKREQ_PCIE5 [12]

Q3701 Security Classification LC Future Center Secret Data Title

SSM3K15AMFV_2-1L1B
DIS@
Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S-G5(1/7) PEG I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 37 of 130

5 4 3 2 1
 5 4 3 2 1

[44] FBA_D[63:0]

UGPU1B
2/14 FBA
FBA_D0 E18
FBA_D1 F18 FBA_D0
FBA_D2
FBA_D3
E16
F17
FBA_D1
FBA_D2 N18S-G5
D
FBA_D4
FBA_D5
D20
D21
FBA_D3
FBA_D4 Package : GB2E-64 D
FBA_D6
FBA_D7
F20
E21
FBA_D5
FBA_D6 NV Symbol : TU117S
FBA_D8 E15 FBA_D7
FBA_D9 D15 FBA_D8
FBA_D10 F15 FBA_D9
FBA_D11 F13 FBA_D10
FBA_D12 C13 FBA_D11
FBA_D13 B13 FBA_D12
FBA_D14 E13 FBA_D13 C27
FBA_D15 FBA_D14 FBA_CMD0 FBA_CMD_0 [44]
D13 C26
FBA_D16 FBA_D15 FBA_CMD1 FBA_CMD_1 [44]
B15 E24
FBA_D17 FBA_D16 FBA_CMD2 FBA_CMD_2 [44]
C16 F24
FBA_D18 FBA_D17 FBA_CMD3 FBA_CMD_3 [44]
A13 D27
FBA_D19 FBA_D18 FBA_CMD4 FBA_CMD_4 [44]
A15 D26
FBA_D20 FBA_D19 FBA_CMD5 FBA_CMD_5 [44]
B18 F25
FBA_D21 FBA_D20 FBA_CMD6 FBA_CMD_6 [44]
A18 F26
FBA_D22 FBA_D21 FBA_CMD7 FBA_CMD_7 [44]
A19 F23
FBA_D23 FBA_D22 FBA_CMD8 FBA_CMD_8 [44]
C19 G22
FBA_D24 FBA_D23 FBA_CMD9 FBA_CMD_9 [44]
B24 G23
FBA_D25 FBA_D24 FBA_CMD10 FBA_CMD_10 [44]
C23 G24
FBA_D26 FBA_D25 FBA_CMD11 FBA_CMD_11 [44]
A25 F27
FBA_D27 FBA_D26 FBA_CMD12 FBA_CMD_12 [44]
A24 G25
FBA_D28 FBA_D27 FBA_CMD13 FBA_CMD_13 [44]
A21 G27
FBA_D29 FBA_D28 FBA_CMD14 FBA_CMD_14 [44]
B21 G26
FBA_D30 FBA_D29 FBA_CMD15 FBA_CMD_15 [44]
C20 M24
FBA_D31 FBA_D30 FBA_CMD16 FBA_CMD_16 [44]
C21 M23
FBA_D32 FBA_D31 FBA_CMD17 FBA_CMD_17 [44]
R22 K24
FBA_D33 FBA_D32 FBA_CMD18 FBA_CMD_18 [44]
R24 K23
FBA_D34 FBA_D33 FBA_CMD19 FBA_CMD_19 [44]
T22 M27
FBA_D35 FBA_D34 FBA_CMD20 FBA_CMD_20 [44]
R23 M26
FBA_D36 FBA_D35 FBA_CMD21 FBA_CMD_21 [44]
N25 M25
FBA_D37 FBA_D36 FBA_CMD22 FBA_CMD_22 [44]
N26 K26
FBA_D38 FBA_D37 FBA_CMD23 FBA_CMD_23 [44]
N23 K22
FBA_D39 FBA_D38 FBA_CMD24 FBA_CMD_24 [44]
N24 J23
FBA_D40 FBA_D39 FBA_CMD25 FBA_CMD_25 [44]
V23 J25
FBA_D41 FBA_D40 FBA_CMD26 FBA_CMD_26 [44]
V22 J24
FBA_D42 FBA_D41 FBA_CMD27 FBA_CMD_27 [44]
T23 K27
FBA_D43 FBA_D42 FBA_CMD28 FBA_CMD_28 [44]
U22 K25
FBA_D44 FBA_D43 FBA_CMD29 FBA_CMD_29 [44] VCC1R2VIDEO
C Y24 J27 C
FBA_D45 FBA_D44 FBA_CMD30 FBA_CMD_30 [44]
AA24 J26
FBA_D46 FBA_D45 FBA_CMD31 FBA_CMD_31 [44]
Y22 B19
FBA_D47 FBA_D46 GP107S FBA_CMD32 FBA_CMD_32 [44]
AA23 F22
FBA_D48 FBA_D47 FBA_CMD34 FBA_CMD33 FBA_CMD_33 [44]
AD27 J22
FBA_D49 AB25 FBA_D48 FBA_CMD35
FBA_D50 AD26 FBA_D49 FBA_DEBUG1 @ R3801 1 2 1/16W_60.4_1%_0402
FBA_D51 AC25 FBA_D50
FBA_D52 AA27 FBA_D51
FBA_D53 AA26 FBA_D52
FBA_D54 W26 FBA_D53
FBA_D55 Y25 FBA_D54
FBA_D56 R26 FBA_D55
FBA_D57 T25 FBA_D56
FBA_D58 N27 FBA_D57
FBA_D59 R27 FBA_D58 D24
FBA_D60 FBA_D59 FBA_CLK0 FBA_CLK0 [44]
V26 D25
FBA_D61 FBA_D60 FBA_CLK0_N -FBA_CLK0 [44]
V27 N22
FBA_D62 FBA_D61 FBA_CLK1 FBA_CLK1 [44]
W27 M22
FBA_D63 FBA_D62 FBA_CLK1_N -FBA_CLK1 [44]
W25
FBA_D63

D19
[44] FBA_DBI0 FBA_DQM0
D14 D18
[44] FBA_DBI1 FBA_DQM1 FBA_WCK01 FBA_WCK01 [44]
C17 C18
[44] FBA_DBI2 FBA_DQM2 GP107S FBA_WCK01_N -FBA_WCK01 [44]
C22 A17
[44] FBA_DBI3 FBA_DQM3 N/A FBA_WCKB01 FBA_WCKB01 [44]
P24 A14
[44] FBA_DBI4 FBA_DQM4 N/A FBA_WCKB01_N -FBA_WCKB01 [44]
W24
[44] FBA_DBI5 FBA_DQM5
AA25 D17
[44] FBA_DBI6 FBA_DQM6 FBA_WCK23 FBA_WCK23 [44]
U25 D16
[44] FBA_DBI7 FBA_DQM7 FBA_WCK23_N -FBA_WCK23 [44]
A23
N/A FBA_WCKB23 FBA_WCKB23 [44]
A20
N/A FBA_WCKB23_N -FBA_WCKB23 [44]
E19
[44] FBA_EDC0 FBA_DQS_WP0
C15
[44] FBA_EDC1 FBA_DQS_WP1
B16 T24
[44] FBA_EDC2 FBA_DQS_WP2 FBA_WCK45 FBA_WCK45 [44]
B22 U24
[44] FBA_EDC3 FBA_DQS_WP3 FBA_WCK45_N -FBA_WCK45 [44]
R25 AC27
[44] FBA_EDC4 FBA_DQS_WP4 N/A FBA_WCKB45 FBA_WCKB45 [44]
W23 Y27
[44] FBA_EDC5 FBA_DQS_WP5 N/A FBA_WCKB45_N -FBA_WCKB45 [44]
AB26
B [44] FBA_EDC6 FBA_DQS_WP6 B
T26
[44] FBA_EDC7 FBA_DQS_WP7 V24
FBA_WCK67 FBA_WCK67 [44]
TU117S GP107S V25
FBA_WCK67_N -FBA_WCK67 [44]
F19 U27
OPT_GND_0 FBA_DQS_RN0 N/A FBA_WCKB67 FBA_WCKB67 [44]
C14 P27
OPT_GND_1 FBA_DQS_RN1 N/A FBA_WCKB67_N -FBA_WCKB67 [44]
A16
A22 OPT_GND_2 FBA_DQS_RN2

P25 OPT_GND_3 FBA_DQS_RN3

W22 OPT_GND_4 FBA_DQS_RN4

AB27 OPT_GND_5 FBA_DQS_RN5

OPT_GND_6 FBA_DQS_RN6
1.5A
T27
OPT_GND_7 FBA_DQS_RN7
VCC1R8VIDEO_MAIN
Place Under GPU
Place Near GPU FL3801
F16 FB_PLL_AVDD DIS@ 1 2 MPZ1608S300AT_2P
FB_PLL_AVDD_1

22U_10V_M_X5R_0603
4.7U_6.3V_M_X5R_0201

4.7U_6.3V_M_X5R_0201
P22 1 1
FB_PLL_AVDD_2 DIS@ DIS@
H22 C3801 C3802
FB_REFPLL_AVDD 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
2 2 1 1 1
DIS@ DIS@ DIS@
C3803 C3804 C3805
2 2 2

FB_VREF D23 1 1
FB_VREF DIS@ DIS@
C3806 C3807
N18S-G5-A1_BGA603 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
2 2
DIS@
1

1
DIS@ DIS@
C3808 R3804
3.9P_25V_C_COG_0201 1/20W_49.9_1%_0201
2
2

A A

PLL AVDD
Valule NV Q'ty LCFC Q'ty
1uF Under 3 Under 4
4.7uF Near 2 Near 2
22uF Near 1 Near 1 Title
Security Classification LC Future Center Secret Data
Beed : 30ohm/100Mhz
(ESR=0.010ohm) Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S-G5(2/7) VRAM I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 38 of 130

5 4 3 2 1
 5 4 3 2 1

30ohm@100MHz ESR=0.01
D VCC1R8VIDEO_MAIN Place Near GPU Place Under UGPU1.N6 D
FL3901
1 2 N3901

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
4.7U_6.3V_M_X5R_0201
MPZ1608S300AT_2P

22U_10V_M_X5R_0603
DIS@

1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C3901 C3902 C3903 C3904 C3905 C3906
2 2 2 2 2 2

UGPU1L
9/14 XTAL_PLL

Place Under UGPU1.N6 Place Under UGPU1.L6/F11 L6

M6 XS_PLLVDD
F11 SP_PLLVDD
N6 GPCPLL_AVDD
VID_PLLVDD

TU117S GP107S
EXT_REFCLK_FL A10 C10 N3903
EXT_REFCLK_FL XTAL_SSIN XTAL_OUTBUFF

C11 B10
XTAL_IN XTAL_OUT
N18S-G5-A1_BGA603

1
DIS@ DIS@
DIS@ R3902
R3901 R3903 1 @ 2 1/20W_1M_5%_0201 27MHZ_OUT 1/20W_100K_5%_0201
1/20W_10K_5%_0201

1
2

2
DIS@
DIS@ R3904
Y3901 1/20W_1.8K_5%_0201
C 27MHZ_10PF_7R27000002 C

2
4 3 N3904
NC2 3

27MHZ_IN 1 2
1 NC1
1 1
DIS@ DIS@
C3908 C3909
15P_25V_J_NPO_0201 15P_25V_J_NPO_0201
2 2

Y3901 CRYSTAL 27MHz- 7pF 20ppm

Vendor P/N LCFC P/N
TXC 7R27000002 SJ10000X300
KDS 7AF02700A06 SJ10000Y400
Murata XRCGB27M000F2P2CR0 SJ10000YD00

UGPU1J
4/14 IFPAB

DVI HDMI DP
SL/DL

AC4
IFPA_L3_N AC3
TXC/TXC
IFPA_L3
AA6
B IFPAB_RSET Y3 B
TXD0/0
IFPA_L2_N Y4
IFPA_L2

TXD1/1 AA2
W7 IFPA_L1_N AA3
IFPAB_PLLVDD IFPA_L1

TXD2/2 AA1
IFPA_L0_N AB1
IFPA_L0

AA5
IFPA_AUX_SDA_N AA4
IFPA_AUX_SCL

AB4
IFPB_L3_N AB5
TXC
IFPB_L3

W6 TXD0/3 AB2
IFP_IOVDD_1 IFPB_L2_N AB3
Y6 IFPB_L2
IFP_IOVDD_2
TXD1/4 AD2
IFPB_L1_N AD3
IFPB_L1

TXD2/5 AD1
IFPB_L0_N AE1
IFPB_L0

AD5
IFPB_AUX_SDA_N AD4
IFPB_AUX_SCL

IFPAB
A A
N18S-G5-A1_BGA603
DIS@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S-G5(3/7) DIGITA / XTAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 39 of 130

5 4 3 2 1
 5 4 3 2 1

VCC1R8VIDEO_AON
I2C Specification
GPU does "Not support multiple masters" on its I2C buses.
1, The default I2CS address is 0x9E.This address cannot be used by another device on the same bus.
2, The GPU has an alternative I2CS address (0x9C).
VCC1R8VIDEO_AON 3, This alternative address is enabled by using the SMB_ALT_ADDR strap(see GPU straps).
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
R4001 R4002 R4003 R4004 R4005 R4006 R4007 R4008 R4009

1
1
DIS@
C4001
VCC1R8VIDEO_AON 1U_6.3V_M_X5R_0201
2

1/20W_2.2K_5%_02012

1/20W_2.2K_5%_02012

1/20W_2.2K_5%_02012

1/20W_2.2K_5%_02012

1/20W_2.2K_5%_02012

1/20W_2.2K_5%_02012

1/20W_10K_5%_02012

1/20W_100K_5%_02012

1/20W_100K_5%_02012
D D

1
DIS@ UGPU1M VCC1R8VIDEO_AON
R4010 8/14 MISC1
1/20W_10K_5%_0201
DIS@
U4001

2
TU117S GP107S
1 8 DIS@ R4011 1 2 GFXCORE_D_PWRGD
Q4001 F10 2 GND EN 7 N4108 1/20W_200K_5%_0201
SSM3K15AMFV_2-1L1B TS_AVDD NC D9 GPU_I2CS_SCL 3 VREF1 VREF2 6
I2CS_SCL GPU_I2CS_SDA SCL1 SCL2 I2C_CLK_EC [53,85]
D8 4 5
I2CS_SDA SDA1 SDA2 I2C_DATA_EC [53,85]
1 3 -OVERT A6 1
[85,100,101,105] -PWRSHUTDOWN OVERT GPU_I2CC_SCL
AE2 A9 PCA9306DQER_X2SON8P_1P4x1 DIS@
TS_VREF I2CC_SCL B9 GPU_I2CC_SDA C4002
DIS@ I2CC_SDA 100P_25V_J_NPO_0201
2
2

E12
THERMDN C9 GPU_I2CB_SCL
F12 I2CB_SCL C8 GPU_I2CB_SDA
THERMDP I2CB_SDA

[37] -GPU_PEX_RST

TU117S GP107S
F3
F4 ADC_IN NC
C6 VIDEO_PWM_VID
ADC_IN_N NC GPIO0 GC6_FB_EN VIDEO_PWM_VID [117]
B2
GPIO1 -GPU_EVENT GC6_FB_EN [9,118]
D6 DIS@ D4001 2 1 RB521CM-30T2R_VMN2M
GPIO2 -GPU_EVENT [11]
C7
GPIO3 F9 1R8VIDEO_MAIN_ON
GPIO4 A3
GPIO5 A4 VGA_CORE_PSI
GPIO6 VGA_CORE_PSI [117]
B6
GPIO7 E9
GPIO8 F8 N4106 DIS@ D4002 2 1 RB521CM-30T2R_VMN2M
GPIO9 -VIDEO_THERM_ALERT [85]
C5 R4029 1 2 1/20W_0_5%_0201
GPIO10 E7 @
GPIO11 D7 AC_DETECT DIS@ D4003 2 1 RB521CM-30T2R_VMN2M
GPIO12 -VIDEO_POWER_LIMIT [85]
B4
GPIO13 B3
C
GPIO14 C3 DIS@ R4030 1 2 1/20W_0_5%_0201 C
GPIO15 GPU_GPIO12 [102]
D5
GPIO16 D4
GPIO17 C2 FP_FUSE
GPIO18 F7
GPIO19 E6
GPIO20 C4
GPIO21 A7
GPIO22 B7
GPIO23

N18S-G5-A1_BGA603
DIS@

Enable: Vh:2.0V Vl:0.8V

VCC3_SUS
VCC3_SUS VCC3_SUS

Enable: Vh:1.5V Vl:0.7V

2

VCC3_SUS
2

2
@
R4025 DIS@ DIS@ DIS@ DIS@
1/20W_10K_5%_0201 VCC1R8VIDEO_AON R4016 R4017 R4014 R4015
1/20W_10K_5%_0201 1/20W_10K_5%_0201 DIS@ 1/20W_10K_5%_0201 1/20W_10K_5%_0201
1

U4002
1

1
1R8VIDEO_AON_ON N4110 1 5
[7,119] 1R8VIDEO_AON_ON IN B VCC
2

B VCC1R0VIDEO_PWRGD B
VCC1R0VIDEO_PWRGD [118]
DIS@ 2
IN A
3

R4018 DIS@
2

1/20W_10K_5%_0201 Q4003 3 4
GND OUT Y GFX_PWR_EN [50]

3
DIS@ DIS@
1

R4026 N4109 1 LSK3541G1ET2L_VMT3 Q4002

2

1/20W_10K_5%_0201 NL17SZ08DFT2G_SC70-5 VCC1R0VIDEO

1

1
DIS@ N4111 1 LSK3541G1ET2L_VMT3
1

2
Q4005 DIS@
SSM3K15AMFV_2-1L1B R4019

1
1R8VIDEO_MAIN_ON 2 1/20W_100K_5%_0201

2
2 Q4004
3

DTC015TMT2L_VMT3

3
DIS@
1R8VIDEO_AON_ON DIS@
D4004
2 1

RB751S40T1G_SOD523-2
VCC3_SUS
DIS@
U4003
VCC1R8VIDEO_AON Delay core power disable for around 100us to make
VCC3_SUS 1 5
DIS@
[50,119] 1R8_MAIN_PWRGD IN B VCC sure PCIE power drop earlier than core power.
U4005 U4004 GFX_PWR_EN 2 DIS@
A2 A1 IN A D4005
VIN VOUT FP_FUSE_GPU [42]
1 5 3 4 N4115 2 1
FP_FUSE [37,50,117,118] GFXCORE_D_PWRGD IN B VCC GND OUT Y GFXCORE_D_EN [117]
B2 B1
ON GND GFX_PWR_EN 2 RB751S40T1G_SOD523-2
TPS22902BYFPR_WCSP4 IN A NL17SZ08DFT2G_SC70-5
1

1
C4003

R4028

DIS@ 3 4 1 2
GND OUT Y 1R0VIDEO_EN [120]

1
R4027 @
1

1/16W_10K_1%_0402 1 @ @ R4020 R4022

1

DIS@ DIS@ NL17SZ08DFT2G_SC70-5 R4021 1/20W_1K_1%_0201 1/20W_100K_5%_0201

A A
DIS@ DIS@ 1/20W_100K_5%_0201
2

2
R4023

2
2 1/20W_100K_5%_0201
2
2.2U_6.3V_K_X5R_0402_YAGEO

1/20W_2.21K_1%_0201

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S-G5(4/7) GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 40 of 130

5 4 3 2 1
 5 4 3 2 1

VCC1R8VIDEO_AON VCC1R8VIDEO_AON

UGPU1K
10/14 MISC2
D D
1

1
X76@ X76@ X76@ @ @ @ @ @ @
R4101 R4102 R4103 R4104 R4105 R4106 R4107 R4108 R4109
1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 D12 -SPI_ROM_CS_GPU 1/20W_100K_1%_0201 1/20W_10K_1%_0201 1/20W_100K_1%_0201
ROM_CS_N
2

2
B12 SPI_ROM_SI_GPU
ROM_SI A12 SPI_ROM_SO_GPU
STRAP0 D1 ROM_SO C12 SPI_ROM_SCLK_GPU
STRAP1 D2 STRAP0 ROM_SCLK
STRAP2 E4 STRAP1
STRAP3 E3 STRAP2
STRAP4 D3 STRAP3
STRAP5 C1 STRAP4
STRAP5

1
DIS@ DIS@ DIS@
1

1
R4110 R4111 R4112
X76@ X76@ X76@ DIS@ DIS@ DIS@ D11 1/20W_100K_1%_0201 1/20W_10K_1%_0201 1/20W_100K_1%_0201
R4113 R4114 R4115 R4116 R4117 R4118 BUFRST_N

2
1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201 1/20W_100K_1%_0201
2

2
N18S-G5-A1_BGA603
DIS@

C C

www.teknisi-indonesia.com
VCC1R8VIDEO_AON VCC1R8VIDEO_AON VCC1R8VIDEO_AON
TABLE of VBIOS ROM (UVBIOS)
Vendor LCFC P/N Description

0.1U_10V_K_X5R_0201
Winbond SA000080E00 S IC FL 8M W25Q80EWSNIG SOIC 8P SPI ROM
MXIC SA00009WK00 S IC FL 8M MX25U8035FM1I SOP 8P
1

1
1
DIS@ DIS@ DIS@ DIS@
R4119 R4120 C4101 R4121
GD SA000086910 S IC FL 8M GD25LQ80CTIGR SOP 8P 150MIL
1/16W_10K_5%_0402 1/16W_10K_5%_0402 1/16W_10K_5%_0402
2
2

2
DIS@
UVBIOS
-SPI_ROM_CS_GPU DIS@ R4122 1 2 1/16W_33_5%_0402 -SPI_ROM_CS 1 8
SPI_ROM_SO_GPU DIS@ R4123 1 2 1/16W_0_5%_0402 SPI_ROM_SO 2 CS# VCC 7
3 DO HOLD# 6 SPI_ROM_SCLK DIS@ R4124 1 2 1/16W_33_5%_0402 SPI_ROM_SCLK_GPU
4 WP# CLK 5 SPI_ROM_SI DIS@ R4125 1 2 1/16W_33_5%_0402 SPI_ROM_SI_GPU
GND DI
W25Q80EWSNIG_SO8

N18-G5 VX76 Config (VRAM + Resistance)

B B

Memory Density
STRAP 2 STRAP 1 STRAP 0
Vendor Manufacturer P/N RAMCFG Setting Number H L H L H L
R4103 R4115 R4102 R4114 R4101 R4113
MT61K256M32JE-14:A
Micron A-die SA00009L510
1 (0x0001) No ASM ASM No ASM ASM ASM No ASM

8Gb (256M x 32)

K4Z80325BC-HC14
SAMSUNG C-die SA00009L410
0 (0x0000) No ASM ASM No ASM ASM No ASM ASM

H56C8H24AIR-S2C
Hynix A-die SA0000B4E00
2 (0x0010) No ASM ASM ASM No ASM No ASM ASM

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S-G5(5/7) STRAP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 41 of 130

5 4 3 2 1
 5 4 3 2 1

VCCGFXCORE_D
Place Under GPU

1 1 1 1 1 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ UGPU1C UGPU1G UGPU1H
C4201 C4202 C4203 C4204 C4205 C4206 C4207 C4208 11/14 VDD 1 of 2 7/14 VDD 2 of 2 6/14 XVDD
1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 K10
2 2 2 2 2 1 1 1 K12 VDD_01
K14 VDD_02 L11 G1 N4
K16 VDD_03 L17 VDD_06 G2 XVDD_1 XVDD_36 N5
K18 VDD_04 M14 VDD_09 G3 XVDD_2 XVDD_37 N7
L13 VDD_05 P10 VDD_12 G4 XVDD_3 XVDD_38 P3
L15 VDD_07 P12 VDD_19 G5 XVDD_4 XVDD_39 P4
M10 VDD_08 P16 VDD_20 G6 XVDD_5 XVDD_40 P6
M12 VDD_10 P18 VDD_22 G7 XVDD_6 XVDD_41 R1
D D
M16 VDD_11 T14 VDD_23 H3 XVDD_7 XVDD_42 R2
2 2 2 2 2 2 2 2 2 VDD_13 VDD_30 XVDD_8 XVDD_43
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ M18 U11 H4 R3
C4209 C4210 C4211 C4212 C4213 C4214 C4215 C4216 C4217 N11 VDD_14 U17 VDD_33 H6 XVDD_9 XVDD_44 R4
10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 N13 VDD_15 VDD_36 J1 XVDD_10 XVDD_45 R5
1 1 1 1 1 1 1 1 1 N15 VDD_16 J2 XVDD_11 XVDD_46 R6
N17 VDD_17 J3 XVDD_12 XVDD_47 R7
P14 VDD_18 J4 XVDD_13 XVDD_48 T1
R11 VDD_21 J5 XVDD_14 XVDD_49 T2
R13 VDD_24 J6 XVDD_15 XVDD_50 T3
R15 VDD_25 J7 XVDD_16 XVDD_51 T4
R17 VDD_26 K1 XVDD_17 XVDD_52 T5
Place Near GPU VDD_27 XVDD_18 XVDD_53
T10 K2 T6
T12 VDD_28 K3 XVDD_19 XVDD_54 T7
T16 VDD_29 K4 XVDD_20 XVDD_55 U3
2 2 2 2 2 2 2 2 2 VDD_31 XVDD_21 XVDD_56
DIS@ DIS_NS@ DIS@ DIS@ DIS@ DIS_NS@ DIS@ DIS_NS@ DIS@ T18 N18S-G5-A1_BGA603 K5 U4
C4218 C4219 C4220 C4221 C4222 C4223 C4224 C4225 C4226 U13 VDD_32 K6 XVDD_22 XVDD_57 U6
VDD_34 DIS@ XVDD_23 XVDD_58
22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 U15 K7 V1
1 1 1 1 1 1 1 1 1 V10 VDD_35 L3 XVDD_24 XVDD_59 V2
V12 VDD_37 L4 XVDD_25 XVDD_60 V3
V14 VDD_38 M1 XVDD_26 XVDD_61 V4
V16 VDD_39 M2 XVDD_27 XVDD_62 V5
V18 VDD_40 M3 XVDD_28 XVDD_63 V6
VDD_41 M4 XVDD_29 XVDD_64 V7
M5 XVDD_30 XVDD_65 W1
1 XVDD_31 XVDD_66
2 2 M7 W2
DIS_NS@ DIS@ + DIS@ F2 N1 XVDD_32 XVDD_67 W3
VDD_SENSE GPU_VDD_SENSE [117] XVDD_33 XVDD_68
C4227 C4228 C4229 F1 N2 W4
GND_SENSE GPU_GND_SENSE [117] XVDD_34 XVDD_69
22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 330U_D2_2V_R9M N3
1 1 2 XVDD_35

trace width: 16mils

differential voltage sensing.
N18S-G5-A1_BGA603 differential signal routing. N18S-G5-A1_BGA603
DIS@ DIS@
VCC1R2VIDEO
C Place Under GPU C
UGPU1E
12/14 FBVDDQ

B26
C25 FBVDDQ_01
1 1 1 1 1 1 1 1 2 2 FBVDDQ_02
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ E23
C4232 C4233 C4234 C4230 C4235 C4236 C4237 C4238 C4231 C4239 E26 FBVDDQ_03
1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 F14 FBVDDQ_04
2 2 2 2 2 2 2 2 1 1 F21 FBVDDQ_05
G13 FBVDDQ_06
G14 FBVDDQ_07
G15 FBVDDQ_08
G16 FBVDDQ_09
G18 FBVDDQ_10
G19 FBVDDQ_11
G20 FBVDDQ_12
Place Near GPU FBVDDQ_13
G21
L22 FBVDDQ_14
L24 FBVDDQ_19
L26 FBVDDQ_20
2 2 2 2 FBVDDQ_21
DIS@ DIS@ DIS@ DIS@ M21
C4240 C4241 C4242 C4243 N21 FBVDDQ_22
10U_6.3V_M_X5R_0402 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 R21 FBVDDQ_23
1 1 1 1 T21 FBVDDQ_24
V21 FBVDDQ_25
W21 FBVDDQ_26
H24 FBVDDQ_27
H26 FBVDDQ_15
J21 FBVDDQ_16
FBVDDQ_17
NVVDD FBVDD 1V8_AON K21
FBVDDQ_18

Valule NV Q'ty LCFC Q'ty Valule NV Q'ty LCFC Q'ty Valule NV Q'ty LCFC Q'ty
1uF Under 5 Under 5 1uF Under 8 Under 8 1uF Under 2 Under 2
10uF Under 12 Under 12 10uF Under 2 Under 2 1uF Near 3 Near 3
B 22uF Near 10 Near 10 10uF Near 1 Near 1 4.7uF Near 3 Near 3 B

330uF Near 0 Near 1 22uF Near 3 Near 3

UGPU1F
14/14 VDD18 VCC1R2VIDEO
GP107S TU117S VCC1R8VIDEO_AON
G8
VDD18 VDD18_1 G9
VDD18
VDD18_2
N18S-G5 Cancel VDD18 conection in Rev Sch and PDG

1
G10 Place Under GPU Place Near GPU DIS@
1V8_AON_1 G12 R4201
1V8_AON_2
1/16W_40.2_1%_0402
1 1 1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

2
C4244 C4245 C4246 C4247 C4248 C4249 C4250 C4251
GP107S TU117S
1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 4.7U_6.3V_M_X5R_0201 4.7U_6.3V_M_X5R_0201 4.7U_6.3V_M_X5R_0201
NC AB6 2 2 2 2 2 2 2 2 D22 FB_CAL_PD_VDDQ
FP_FUSE_SRC FB_CAL_PD_VDDQ

C24 FB_CAL_PU_GND
FB_CAL_PU_GND

B25 N4203
FB_CAL_TERM_GND

1
DIS@ DIS@ DIS@
R4202 R4203
1/16W_40.2_1%_0402 1/16W_40.2_1%_0402

2
N18S-G5-A1_BGA603
DIS@
FP_FUSE_GPU [40]

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S-G5(5/7) POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 42 of 130

5 4 3 2 1
 5 4 3 2 1

UGPU1I
13/14 GND

A2 K11
AB17 GND_001 GND_059 K13
AB20 GND_006 GND_060 K15
AB24 GND_007 GND_061 K17
AC2 GND_008 GND_062 L10
D AC22 GND_010 GND_063 L12 UGPU1N D
AC26 GND_011 GND_064 L14 3/14 JTAG
AC5 GND_012 GND_065 L16
AC8 GND_013 GND_066 L18
AD12 GND_014 GND_067 L5 R4301 1 @ 21/20W_10K_5%_0201 N4301 AE5
AD13 GND_015 GND_071 M11 TP3802 1Test_Point_20MIL N4302 AE6 JTAG_TCK
A26 GND_016 GND_072 M13 TP3801 1Test_Point_20MIL N4303 AF6 JTAG_TDI
AD15 GND_002 GND_073 M15 TP3803 1Test_Point_20MIL N4304 AD6 JTAG_TDO
AD16 GND_017 GND_074 M17 R4302 2 DIS@ 11/20W_10K_5%_0201 N4305 AG4 JTAG_TMS
AD18 GND_018 GND_075 N10 R4303 2 DIS@ 11/20W_10K_5%_0201 N4306 AD9 JTAG_TRST_N
AD19 GND_019 GND_076 N12 NVJTAG_SEL
AD21 GND_020 GND_077 N14
AD22 GND_021 GND_078 N16
AE11 GND_022 GND_079 N18
AE14 GND_023 GND_080 P11
AE17 GND_024 GND_081 P13
AE20 GND_025 GND_082 P15
AB11 GND_026 GND_083 P17
AF1 GND_004 GND_084 P23
AF11 GND_027 GND_086 P26
AF14 GND_028 GND_087 R10
AF17 GND_029 GND_089 R12
AF20 GND_030 GND_090 R14
AF23 GND_031 GND_091 R16
C
N18S-G5-A1_BGA603 C
AF5 GND_032 GND_092 R18
GND_033 GND_093 DIS@
AF8 T11
AG2 GND_034 GND_094 T13
AG26 GND_035 GND_095 T15
AB14 GND_036 GND_096 T17
B1 GND_005 GND_097 U10
B11 GND_037 GND_098 U12 UGPU1D
B14 GND_038 GND_099 U14 5/14 NC
B17 GND_039 GND_100 U16
B20 GND_040 GND_101 U18
B23 GND_041 GND_102 U23
B27 GND_042 GND_104 U26
B5 GND_043 GND_105 V11 AA15
B8 GND_044 GND_107 V13 AB8 NC_2
E11 GND_045 GND_108 V15 AD10 NC_4
E14 GND_046 GND_109 V17 AD7 NC_5
E17 GND_047 GND_110 Y2 AE22 NC_6
E2 GND_048 GND_111 Y23 AE3 NC_7
E20 GND_049 GND_112 Y26 AE4 NC_8
E22 GND_050 GND_113 Y5 AF2 NC_9
E25 GND_051 GND_114 AA7 AF22 NC_10
E5 GND_052 GND_003 AB7 AF3 NC_11
E8 GND_053 GND_009 AF4 NC_12
GND_054 AG3 NC_13
B B
D10 NC_14
E10 NC_15
F6 NC_16
OPTIONAL GND:
W5 NC_21
F5 NC_22
NC_20
XVDD AREA
H2 P2
H5 GND_055 GND_085 P5
L2 GND_058 GND_088 U2
GND_068 GND_103 U5
GND_106
N18S-G5-A1_BGA603
PCB
ADR/CMD DIS@

PWR
H23 REFERENCE L23
H25 GND_056 GND_069 L25
GND_057 GND_070

N18S-G5-A1_BGA603
DIS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S-G5(7/7) GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 43 of 130

5 4 3 2 1
 5 4 3 2 1

GPU [38] FBA_D[0..63]

UV1C X76@
UV1D X76@ UV1A X76@ UV1B X76@
Please do not stuff any capcaitor on VREFC pin.
NORMAL NORMAL H3 K1 VREFC
VCC1R2VIDEO [38] FBA_CMD_0 CA0_A VREFC
G11
FBA_D4 [38] FBA_CMD_9 CA1_A
B4 x16 x8 G4
FBA_D6 DQ0_A FBA_D28 [38] FBA_CMD_8 CA2_A
A11 A1 A3 U4 H12
VSS_1 VDD_1 FBA_D5 DQ1_A FBA_D31 DQ0_B [38] FBA_CMD_32 CA3_A
A13 A14 B3 V3 H5
VSS_2 VDD_2 DQ2_A DQ1_B [38] FBA_CMD_7 CA4_A

1
D A2 E10 FBA_D7 B2 FBA_D30 U3 H10 DIS@ D
VSS_3 VDD_3 FBA_D0 DQ3_A FBA_D25 DQ2_B [38] FBA_CMD_11 CA5_A
A4 E5 E3 U2 J12 R4401
VSS_4 VDD_4 FBA_D1 DQ4_A FBA_D24 DQ3_B [38] FBA_CMD_15 CA6_A
B1 H13 E2 P3 J11 1/16W_1K_1%_0402
VSS_5 VDD_5 FBA_D3 DQ5_A FBA_D26 DQ4_B [38] FBA_CMD_14 CA7_A
B14 H2 F2 P2 J4
VSS_6 VDD_6 FBA_D2 DQ6_A FBA_D29 DQ5_B [38] FBA_CMD_3 CA8_A
C10 L13 G2 N2 J3
[38] FBA_CMD_1

2
C12 VSS_7 VDD_7 L2 DQ7_A FBA_D27 M2 DQ6_B J5 CA9_A
VSS_8 VDD_8 DQ7_B [38] FBA_CMD_6 CABI_n_A
C3 P10 C2 G10
VSS_9 VDD_9 [38] FBA_EDC0 EDC0_A [38] FBA_CMD_10 CKE_n_A
C5 P5 D2 T2
VSS_10 VDD_10 [38] FBA_DBI0 DBI0_n_A [38] FBA_EDC3 EDC0_B
D1 V1 R2 N5
VSS_11 VDD_11 [38] FBA_DBI3 DBI0_n_B TCK
D12 V14 D4
VSS_12 VDD_12 [38] FBA_WCK01 WCK0_t_A
D14 D5 R4 F10
VSS_13 [38] -FBA_WCK01 WCK0_c_A [38] FBA_WCKB23 WCK0_t_B TDI
D3 R5 N10
VSS_14 [38] -FBA_WCKB23 WCK0_c_B TDO
E11
E4 VSS_15 x16 x8 FBA_D16 U11 F5
F1 VSS_16 FBA_D12 B11 FBA_D18 V12 DQ8_B L3 TMS
NC
VSS_17 FBA_D10 DQ8_A FBA_D19 DQ9_B [38] FBA_CMD_4 CA0_B
F12 A12 NC U12 M11
VSS_18 FBA_D13 DQ9_A FBA_D17 DQ10_B [38] FBA_CMD_12 CA1_B
F14 B10 B12 NC U13 M4
VSS_19 VDDQ_1 FBA_D9 DQ10_A FBA_D23 DQ11_B [38] FBA_CMD_5 CA2_B
F3 B5 B13 NC P12 L12
VSS_20 VDDQ_2 FBA_D15 DQ11_A FBA_D22 DQ12_B [38] FBA_CMD_13 FBA_CMD_7 CA3_B
G1 C1 E12 NC P13 L5
G12 VSS_21 VDDQ_3 C11 FBA_D14 E13 DQ12_A FBA_D21 N13 DQ13_B FBA_CMD_11 L10 CA4_B
NC
G14 VSS_22 VDDQ_4 C14 FBA_D8 F13 DQ13_A FBA_D20 M13 DQ14_B FBA_CMD_15 K12 CA5_B
NC
G3 VSS_23 VDDQ_5 C4 FBA_D11 G13 DQ14_A DQ15_B FBA_CMD_14 K11 CA6_B
NC
H11 VSS_24 VDDQ_6 E1 DQ15_A T13 FBA_CMD_3 K4 CA7_B
VSS_25 VDDQ_7 [38] FBA_EDC2 EDC1_B FBA_CMD_1 CA8_B
H4 E14 C13 GND R13 K3
VSS_26 VDDQ_8 [38] FBA_EDC1 EDC1_A [38] FBA_DBI2 DBI1_n_B FBA_CMD_6 CA9_B CH_A0_ZQ_A
L11 F11 D13 K5 J14 R4402 1 DIS@ 2 1/20W_121_1%_0201
VSS_27 VDDQ_9 [38] FBA_DBI1 DBI1_n_A NC
FBA_CMD_10 CABI_n_B ZQ_A
L4 F4 R11 M10
VSS_28 VDDQ_10 [38] FBA_WCK23 WCK1_t_B CKE_n_B
M1 H1 D11 NC R10 K14 CH_A0_ZQ_B R4403 1 DIS@ 2 1/20W_121_1%_0201
VSS_29 VDDQ_11 [38] FBA_WCKB01 WCK1_t_A [38] -FBA_WCK23 WCK1_c_B ZQ_B
M12 H14 D10 NC
VSS_30 VDDQ_12 [38] -FBA_WCKB01 WCK1_c_A
M14 J13
M3 VSS_31 VDDQ_13 J2
N1 VSS_32 VDDQ_14 K13 K4Z80325BC-HC14_FBGA180 K4Z80325BC-HC14_FBGA180
N12 VSS_33 VDDQ_15 K2 J1
VSS_34 VDDQ_16 [38] FBA_CMD_2 RESET_n
N14 L1
N3 VSS_35 VDDQ_17 L14
P11 VSS_36 VDDQ_18 N11
P4 VSS_37 VDDQ_19 N4 K10
VSS_38 VDDQ_20 [38] -FBA_CLK0 CK_c
R1 P1 J10
VSS_39 VDDQ_21 [38] FBA_CLK0 CK_t
R12 P14 G5
R14 VSS_40 VDDQ_22 T1 CA10_A, NC1
C R3 VSS_41 VDDQ_23 T11 M5 C
T10 VSS_42 VDDQ_24 T14 CA10_B, NC2
T12 VSS_43 VDDQ_25 T4
T3 VSS_44 VDDQ_26 U10
T5 VSS_45 VDDQ_27 U5
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
VSS_50 K4Z80325BC-HC14_FBGA180
V2 VCC1R8VIDEO_AON
V4 VSS_51
VSS_52
A10
VPP_1 A5
VPP_2 V10
VPP_3 V5
VPP_4

K4Z80325BC-HC14_FBGA180

UV2C X76@
UV2A X76@ UV2B X76@ Please do not stuff any capcaitor on VREFC pin.

UV2D X76@ NORMAL NORMAL H3 K1 VREFC

VCC1R2VIDEO [38] FBA_CMD_20 CA0_A VREFC
G11
FBA_D37 [38] FBA_CMD_28 CA1_A
B4 x16 x8 G4
FBA_D38 DQ0_A FBA_D59 [38] FBA_CMD_21 CA2_A
A3 U4 H12
FBA_D36 DQ1_A FBA_D57 DQ0_B [38] FBA_CMD_29 CA3_A
B3 V3 H5
FBA_D32 DQ2_A FBA_D56 DQ1_B [38] FBA_CMD_23 CA4_A
A11 A1 B2 U3 H10
VSS_1 VDD_1 FBA_D34 DQ3_A FBA_D58 DQ2_B [38] FBA_CMD_27 CA5_A
A13 A14 E3 U2 J12
VSS_2 VDD_2 FBA_D39 DQ4_A FBA_D61 DQ3_B [38] FBA_CMD_30 CA6_A
A2 E10 E2 P3 J11
VSS_3 VDD_3 FBA_D35 DQ5_A FBA_D60 DQ4_B [38] FBA_CMD_31 CA7_A
A4 E5 F2 P2 J4
VSS_4 VDD_4 FBA_D33 DQ6_A FBA_D63 DQ5_B [38] FBA_CMD_19 CA8_A
B1 H13 G2 N2 J3
VSS_5 VDD_5 DQ7_A FBA_D62 DQ6_B [38] FBA_CMD_17 CA9_A
B14 H2 M2 J5
VSS_6 VDD_6 DQ7_B [38] FBA_CMD_22 CABI_n_A
C10 L13 C2 G10
VSS_7 VDD_7 [38] FBA_EDC4 EDC0_A [38] FBA_CMD_26 CKE_n_A
C12 L2 D2 T2
B VSS_8 VDD_8 [38] FBA_DBI4 DBI0_n_A [38] FBA_EDC7 EDC0_B B
C3 P10 R2 N5
VSS_9 VDD_9 [38] FBA_DBI7 DBI0_n_B TCK
C5 P5 D4
VSS_10 VDD_10 [38] FBA_WCK45 WCK0_t_A
D1 V1 D5 R4 F10
VSS_11 VDD_11 [38] -FBA_WCK45 WCK0_c_A [38] FBA_WCKB67 WCK0_t_B TDI
D12 V14 R5 N10
VSS_12 [38] -FBA_WCKB67 WCK0_c_B TDO
D14 VDD_12
D3 VSS_13 x16 x8 FBA_D54 U11 F5
VSS_14 FBA_D47 B11 FBA_D48 V12 DQ8_B L3 TMS
E11 DQ8_A
NC
DQ9_B [38] FBA_CMD_16 CA0_B
E4 VSS_15 FBA_D46 A12 NC FBA_D50 U12 M11
VSS_16 FBA_D42 DQ9_A FBA_D53 DQ10_B [38] FBA_CMD_25 CA1_B
F1 B12 NC U13 M4
VSS_17 FBA_D43 DQ10_A FBA_D52 DQ11_B [38] FBA_CMD_24 CA2_B
F12 B13 NC P12 L12
VSS_18 FBA_D40 DQ11_A FBA_D49 DQ12_B [38] FBA_CMD_33 FBA_CMD_23 CA3_B
F14 B10 E12 NC P13 L5
VSS_19 VDDQ_1 FBA_D45 E13 DQ12_A FBA_D51 N13 DQ13_B FBA_CMD_27 L10 CA4_B
F3 B5 DQ13_A
NC
DQ14_B CA5_B
G1 VSS_20 VDDQ_2 C1 FBA_D41 F13 NC FBA_D55 M13 FBA_CMD_30 K12
VSS_21 VDDQ_3 FBA_D44 G13 DQ14_A DQ15_B FBA_CMD_31 K11 CA6_B
G12 C11 DQ15_A
NC
CA7_B
G14 VSS_22 VDDQ_4 C14 T13 FBA_CMD_19 K4
VSS_23 VDDQ_5 [38] FBA_EDC6 EDC1_B FBA_CMD_17 CA8_B
G3 C4 C13 GND R13 K3
VSS_24 VDDQ_6 [38] FBA_EDC5 EDC1_A [38] FBA_DBI6 DBI1_n_B FBA_CMD_22 CA9_B CH_A1_ZQ_A
H11 E1 D13 K5 J14 R4408 1 DIS@ 2 1/20W_121_1%_0201
VSS_25 VDDQ_7 [38] FBA_DBI5 DBI1_n_A NC
FBA_CMD_26 CABI_n_B ZQ_A
H4 E14 R11 M10
VSS_26 VDDQ_8 [38] FBA_WCK67 WCK1_t_B CKE_n_B
L11 F11 D11 NC R10 K14 CH_A1_ZQ_B R4409 1 DIS@ 2 1/20W_121_1%_0201
VSS_27 VDDQ_9 [38] FBA_WCKB45 WCK1_t_A [38] -FBA_WCK67 WCK1_c_B ZQ_B
L4 F4 D10 NC
VSS_28 VDDQ_10 [38] -FBA_WCKB45 WCK1_c_A
M1 H1
M12 VSS_29 VDDQ_11 H14
M14 VSS_30 VDDQ_12 J13 K4Z80325BC-HC14_FBGA180 K4Z80325BC-HC14_FBGA180
M3 VSS_31 VDDQ_13 J2 J1
VSS_32 VDDQ_14 [38] FBA_CMD_18 RESET_n
N1 K13
N12 VSS_33 VDDQ_15 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 K10 CK_c
VSS_36 VDDQ_18 [38] -FBA_CLK1
P11 N11 J10
VSS_37 VDDQ_19 [38] FBA_CLK1 CK_t
P4 N4 G5
VSS_38 VDDQ_20 CA10_A, NC1
R1 P1
R12 VSS_39 VDDQ_21 P14 M5
VSS_40 VDDQ_22 CA10_B, NC2
R14 T1
VSS_41 VDDQ_23 VCC1R2VIDEO
R3 T11
T10 VSS_42 VDDQ_24 T14
T12 VSS_43 VDDQ_25 T4
T3 VSS_44 VDDQ_26 U10
T5 VSS_45 VDDQ_27 U5 FBA_CMD_10 DIS@ R4404 2 1 1/20W_10K_5%_0201
U1 VSS_46 VDDQ_28
A A
U14 VSS_47 FBA_CMD_26 DIS@ R4405 2 1 1/20W_10K_5%_0201 K4Z80325BC-HC14_FBGA180
V11 VSS_48 VCC1R8VIDEO_AON
V13 VSS_49
V2 VSS_50 FBA_CMD_2 DIS@ R4406 2 1 1/20W_10K_5%_0201
V4 VSS_51
VSS_52 FBA_CMD_18 DIS@ R4407 2 1 1/20W_10K_5%_0201
A10
VPP_1 A5
VPP_2 V10
VPP_3 V5
VPP_4 Title
Security Classification LC Future Center Secret Data
K4Z80325BC-HC14_FBGA180 Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S:GDDR6 VRAM CH_A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 44 of 130

5 4 3 2 1
 5 4 3 2 1

VCC1R2VIDEO VCC1R2VIDEO

Place Near GPU Place Near GPU

1 1 1 1 1 1 1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C4501 C4502 C4503 C4504 C4505 C4506 C4507 C4508 C4509 C4510 C4511 C4512
1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
2 2 2 2 2 2 2 2 2 2 2 2

D D

1 1 1 1 1 1 1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C4513 C4514 C4515 C4516 C4517 C4518 C4519 C4520 C4521 C4522 C4523 C4024
1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
2 2 2 2 2 2 2 2 2 2 2 2

1 1 1 1 1 1 1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C4525 C4526 C4527 C4528 C4529 C4530 C4531 C4532 C4533 C4534 C4535 C4536
1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201
2 2 2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C4537 C4538 C4539 C4540 C4541 C4542 C4543 C4544
10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402
1 1 1 1 1 1 1 1

C Place Under GPU Place Under GPU C

2 2 2 2 2 2 2 2 2 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C4545 C4546 C4547 C4548 C4549 C4550 C4551 C4552 C4553 C4554 C4555 C4556
22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603
1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2
DIS@ DIS@ DIS@ DIS@
C4557 C4558 C4559 C4560
10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402
1 1 1 1

VCC1R8VIDEO_AON VCC1R8VIDEO_AON
Place Near GPU Place Near GPU

1 1 1 1 1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C4561 C4562 C4563 C4564 C4565 C4566 C4567 C4568 C4569 C4570
B 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 4.7U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 1U_6.3V_M_X5R_0201 4.7U_6.3V_M_X5R_0201 B
2 2 2 2 2 2 2 2 2 2

VDD/VDDQ VDD/VDDQ
Valule NV Q'ty LCFC Q'ty
Valule NV Q'ty LCFC Q'ty
1uF Near 18 Near 18
1uF Near 18 Near 18
10uF Near 4 Near 4
10uF Near 4 Near 4
10uF Under 2 Under 2
10uF Under 2 Under 2
22uF Under 6 Under 6
22uF Under 6 Under 6

VPP VPP
Valule NV Q'ty LCFC Q'ty
Valule NV Q'ty LCFC Q'ty
1uF Near 4 Near 4
1uF Near 4 Near 4
4.7uF Near 1 Near 1
4.7uF Near 1 Near 1
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 N18S: VRAM CH_A_CAP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 45 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

www.teknisi-indonesia.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 Video
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 46 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 Video
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 47 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 Video
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 48 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 Video
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 49 of 130

5 4 3 2 1
 5 4 3 2 1

VCC1R8_SUS VCC1R8_SUS [7,9,11,16,51,78,85,108,110,116,117]

VCC1R8VIDEO_MAIN VCC1R8VIDEO_MAIN [37,38,39]

VCC1R8_SUS to VCC1R8VIDEO_MAIN / VCC1R8VIDEO_MEM

D D

VCC3_SUS VCC1R8VIDEO_AON
VCC1R8VIDEO_MAIN

80 mils

1
R5001 1 DIS@
1/16W_10K_5%_0402 C5001 U5001
@ TPS22971YZPT_DSBGA8 80 mils
10U_6.3V_M_X5R_0402 A2 A1

2
2 VIN1 VOUT1
B2 B1
VIN2 VOUT2
C2 C1
CT PG
D2 D1
ON GND DIS@
1

1
DIS@ C5003 @
DIS@ R5012
C GFXCORE_D_PWRGD 2 1 DIS_1V8_ON 0.1U_25V_K_X5R_0201 1/16W_10_5%_0402 C
[37,40,117,118] GFXCORE_D_PWRGD 2
1
D5001 @

2
RB521CM-30T2R_VMN2M C5002
0.1U_25V_K_X5R_0402

1
DIS@ DIS@ 2
GFX_PWR_EN 2 1 R5006
[40] GFX_PWR_EN
1/16W_100K_5%_0402
D5002
RB521CM-30T2R_VMN2M

VCC3_SUS

VCC1R8VIDEO_MAIN

1
R5011
1/16W_10K_5%_0402

1
DIS@
R5010

2
1

1/16W_10K_5%_0402
R5009 DIS@
1/16W_10K_5%_0402 1R8_MAIN_PWRGD [40,119]

2
DIS@
B B
2

3
D
Q5004_5 5 DIS@
G Q5004B
UM6K33N_UMT6
S

4
6

D
Q5004_2 2 DIS@
G Q5004A
UM6K33N_UMT6
S
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 R19M-P25:Load SW VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 50 of 130

5 4 3 2 1
 5 4 3 2 1

LOGO_LED Side A PWRBTN

VCC3M VCC3P
LCDVDD Circuit [85] LED_LOGO
LED_LOGO R5101 1 2 1/16W_2.4K_1%_0402 LED_LOGO_CONN VCC5M VCC3SW

Close connector

1
U5101 EMC@ R5102
W= 60 mil 5 1 W= 60 mil D5101 1/16W_2.2K_5%_0402
IN OUT PESD5V0U2BT_SOT23-3
From PCH 2

2
GND
1 1 JPWR1
PANEL_POWER_ON 4 3 C5101
[3] PANEL_POWER_ON EN OC 4.7U_10V_K_X5R_0603 C5102 1
1 1
G524B1T11U_SOT23-5 2200P_50V_K_X7R_0402 -LED_PWR 2
2 2 EMC_NS@ [85] -LED_PWR 2
C5103 SA000074R00 -PWRSWITCH 3
[62,85] -PWRSWITCH 3
1U_6.3V_K_X5R_0402_MURATA 4
2 4
5
VCC3B GND1 6
D JSW1 GND2 D
Bottom Side
1 2 -PWRSWITCH HIGHS_FC1AF041-2201H

2
SHORT PADS ME@
PU +3VL at EC side.

1
@_JSW1_S D5102
R5105 PESD5V0U2BT_SOT23-3
1/20W_100K_5%_0201 EMC@
TABLE of POWER SWITCH (U5101) Size CTL
Status (GPP_C19)
Vendor LCFC P/N Description

1
GMT SA000074R00 S IC G524B1T11U SOT23 5P POWER SWITCH Size CTL
15@ 0 (GND Low)
SA0000AGK00 S IC RT9742NGJ5 TSOT-23-5 5P PWR SW R5106
RICHTEK

1
SILERGY SA000074P00 S IC SY6288C20AAC SOT23 5P POWER SWITCH R5106
14@ 1 (NC High) DMIC
@ 1/20W_100K_5%_0201 R5105

LCD_Self_test

2
VCC3B VCC1R8_SUS

[3] PANEL_BKLT_CTRL_CPU
PANEL_BKLT_CTRL_CPU D5103 2 1 RB520CM-30T2R_VMN2M2 PANEL_BKLT_CTRL
Device U5102

[3,85] LCD_SELF_TEST_ON
LCD_SELF_TEST_ON D5104 2 1 RB520CM-30T2R_VMN2M2
DMIC_CLK0_D 1
B VCCA
5
PCH
VCC3B VCC3B

2
R5103 2
VCCB
3 4
VCC3P GND A PCH_DMIC_CLK0 [9]
1/20W_10K_5%_0201 1 1
F5104 F5105
F5103

1
1 2 1 2 VCC3B_DMIC C5128 C5129
1 2 VCC3LCD 0.1U_6.3V_K_X5R_0201 2N7001TDCKR_SC70-5 0.1U_6.3V_K_X5R_0201
2A_32V_ERBRD2R00X 2A_32V_ERBRD2R00X 2 2

3A_32V_ERBRD3R00X

TPCAM_PW
TPNL_VDD For the Lx90 issue
VCC3B VCC3B VCC3B For the Lx90 issue
VCC1R8_SUS VCC3B
VCC3B
PCH
1

U5103
1

1
R5120
R5130 R5129 R5122 1/16W_10K_5%_0402 R5108 1 5
1/16W_10K_5%_0402 1/16W_10K_5%_0402 1/16W_10K_5%_0402 @ 1/16W_10K_5%_0402
[9] PCH_DMIC_DATA0
2
B VCCA
Device
2

VCCB
2

2
-TCH_PNL_RST 3 4 DMIC_DATA0_D
GND A
1 1
C
1
C5119 VSYS15 eDP/CMOS/LOGO-LED CONN. C5130 C5131
C

LPSS_I2C1_SCL_PNL LPSS_I2C1_SDA_PNL -TCH_PNL_INT @ 0.1U_6.3V_K_X5R_0201 2N7001TDCKR_SC70-5 0.1U_6.3V_K_X5R_0201

0.1U_10V_K_X5R_0402_MURATA F5102 2 2
2A, 80 mil JLCD1
2 1 2 VBL15 1 51
W= 80 mil 1 GND_1
1 2 52
C5125 3 2 GND_2 53
3A_32V_ERBRD3R00X 4.7U_25V_K_X5R_0805_H1.25 4 3 GND_3 54
R5109 1 2 0_0603_SP VCC3B_DMIC_CONN 5 4 GND_4 55
2 VCC3B_DMIC 5 GND_5
R5110 1 2 0_0603_SP VCC3B_CMOS 6 56
TPCAM_PW 6 GND_6
W= 40 mil 7 57
8 7 GND_7 58
9 8 GND_8 59
W= 60 mil 9 GND_9
Size CTL 10 60
[8] Size CTL LCD_SELF_TEST_ON R5111 LCD_SELF_TEST_ON_CONN 10 GND_10
1 2 0_0402_SP 11 61
LED_LOGO_CONN 12 11 GND_11 62
BACKLIGHT_ON 13 12 GND_12
[85] BACKLIGHT_ON 13
PANEL_BKLT_CTRL 14
PANEL_BKLT_CTRL 14
-INT_MIC_DTCT 15
[11] -INT_MIC_DTCT 15
DMIC_DATA0_D R5219 1 2 1/16W_33_5%_0402 DMIC_DATA0_CONN 16
DMIC_DATA0_D DMIC_CLK0_D DMIC_CLK0_CONN 16
R5218 1 2 0_0402_SP 17
DMIC_CLK0_D 17
18
EDP_AUXN C5104 1 2 0.1U_6.3V_K_X5R_0201 EDP_AUXN_CONN 19 18
[3] EDP_AUXN EDP_AUXP EDP_AUXP_CONN 19
C5105 1 2 0.1U_6.3V_K_X5R_0201 20
[3] EDP_AUXP EDP_HPD_CONN 20
21
22 21
EDP_TXN0 C5107 1 2 0.1U_6.3V_K_X5R_0201 EDP_TXN0_CON 23 22
[3] EDP_TXN0 EDP_TXP0 EDP_TXP0_CON 23
C5108 1 2 0.1U_6.3V_K_X5R_0201 24
[3] EDP_TXP0 24
25
EDP_TXN1 C5109 1 2 0.1U_6.3V_K_X5R_0201 EDP_TXN1_CON 26 25
[3] EDP_TXN1 EDP_TXP1 EDP_TXP1_CON 26
C5110 1 2 0.1U_6.3V_K_X5R_0201 27
[3] EDP_TXP1 27
28
R5116 1 2 0_0402_SP -CAM_FW_WR_EN_CONN 29 28
[85] -CAM_FW_WR_EN 29
L5101 EMC@ 30
USB2_P7_DN 1 2 USB2_P7_DN_CONN 31 30
[10] USB2_P7_DN 1 2 USB2_P7_DP_CONN 31
32
RGB 33 32
USB2_P7_DP 4 3 34 33
[10] USB2_P7_DP 4 3 34
35
36 35
EXC24CH900U_4P 37 36
SM070003X00 R5117 1 2 0_0201_SP LPSS_I2C1_SDA_PNL_CONN 38 37
[8] LPSS_I2C1_SDA_PNL 38
R5118 1 2 0_0201_SP LPSS_I2C1_SCL_PNL_CONN 39
Touch Panel [8] LPSS_I2C1_SCL_PNL
40 39
41 40
R5119 1 2 0_0201_SP -TCH_PNL_INT_CONN 42 41
[7] -TCH_PNL_INT TPNL_VDD 42
43
R5127 1 @ 2 1/16W_0_5%_0402 VCC3SW 44 43
[13,37,64,66,73,76] -PLTRST_FAR -TCH_PNL_RST_CONN 44
R5128 1 2 0_0402_SP 45
[8] -TCH_PNL_RST -LID_CLOSE 45
46
B [85] -LID_CLOSE 46 B
47
VCC3B_TOUCHPANEL R5135 2 1 1/20W_10K_5%_0201 48 47
VCC3_SUS 48
-TOUCH_DETECT 49
[8] -TOUCH_DETECT TCH_PNL_EN_CONN 49
1 2 50
50
1

1
R5124 1 1 1 1 C5127 R5114 @ I-PEX_20439-050E-01

1
RF@ C5114 C5126 EMC@ D5105 ME@
1/16W_100K_5%_0402

10P_50V_J_NPO_0402

1/16W_100K_5%_0402
C5113 RB520CM-30T2R_VMN2M2 R5115
680P_50V_K_X7R_0402

680P_50V_K_X7R_0402
R5113 1 2 0_0402_SP EMC@ EMC_NS@ @ 1/16W_100K_5%_0402
2 2 2 2
0.1U_10V_K_X7R_0402
2

2
1
RF@ VCC3B
C5111
0.1U_10V_K_X7R_0402 1 1
2 RF@
C5115 C5116
0.1U_10V_K_X7R_0402 10U_0402_6.3V6-M
Close to eDP connector. 2 2

1 2 TCH_PNL_EN_CONN
[8] TCH_PNL_EN

1
20190116
R5121 R5123
For eDP_HPD input/output voltage mismatch 0_0201_SP
Add Cap for IR CAM voltage drop issue
1/16W_100K_5%_0402
VCC3_SUS VCC3P

2
For touch panel enable.
1

R5132 R5133

1/16W_10K_5%_0402 1/16W_4.7K_5%_0402 RF
EDP_HPD
EDP_HPD [3]
2

VBL15 VCC3LCD LED_LOGO_CONN

RF@ 1 RF@ 1 RF@ 1 RF@ RF@ 1 RF@

3

1
D C5117 C5118 C5121 C5122 C5123 C5124
5 Q5101B 0.1U_16V_K_X7R_0402_MURATA 47P_50V_J_NPO_0402 100P_50V_J_NPO_0402 47P_50V_J_NPO_0402 0.1U_16V_K_X7R_0402_MURATA 100P_50V_J_NPO_0402
G

2
DMN5L06DWK-7 2N SOT363-6 2 2 2 2
2

S
4
6

D R5136
EDP_HPD_CONN 2 Q5101A @ 1/20W_100K_5%_0201
G
DMN5L06DWK-7 2N SOT363-6
1

S SB00001HM00
1
1

R5131

A 1/16W_100K_5%_0402 R5134 1 2 1/16W_0_5%_0402 A

2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12
LCD CAMERA/MIC/TOUCH SREEN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 51 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3M

1/16W_10K_5%_0402
D D

2
R5201
1
B_ON D5201 1 2 VCC3_TOUCHPANEL_ON
[72,78,86,106,125,127] B_ON
RB521CM-30T2R_VMN2M-2
D5202 1 2
[11] TOUCHPANEL_ON
RB521CM-30T2R_VMN2M-2

C VCC3B C
VCC3B_TOUCHPANEL

W= 60 mil

1
R5202 U5201
1/16W_10K_5%_0402 @ 5 1 VCC3B_TOUCHPANEL
IN OUT
2
2 GND
VCC3_TOUCHPANEL_ON 4 3
EN OC
G524B1T11U_SOT23-5
SA000074R00

B B

Touch@ for MODS Touch panel

TABLE of POWER SWITCH (U5201)

Vendor LCFC P/N Description
GMT SA000074R00 S IC G524B1T11U SOT23 5P POWER SWITCH
RICHTEK SA0000AGK00 S IC RT9742NGJ5 TSOT-23-5 5P PWR SW
SILERGY SA000074P00 S IC SY6288C20AAC SOT23 5P POWER SWITCH
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 LCD CAMERA/MIC/TOUCH SREEN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 52 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3B VCC3B [3,7,8,10,12,13,33,34,35,36,37,51,52,55,63,64,66,70,73,76,78,85,88,89,91,92,93,97,98,101,127] VCC3B

VCC1R2M_PS8409
Close Pin43 , Pin46 Close Pin6 , Pin11

4.7U_10V_K_X5R_0402

0.01U_25V_K_X7R_0402

0.01U_25V_K_X7R_0402

0.01U_25V_K_X7R_0402
0.1U_6.3V_K_X7R_0402

0.1U_6.3V_K_X7R_0402

0.1U_6.3V_K_X7R_0402

0.1U_6.3V_K_X7R_0402

0.1U_6.3V_K_X7R_0402

0.1U_6.3V_K_X7R_0402
1 1 1 1 1 1 1 1 1 1

C5305

C5306

C5307

C5308

C5309

C5310

C5311

C5326

C5327

C5328
VCC1R2M_PS8409

VCC3B VCC3B 2 2 2 2 2 2 2 2 2 2

U5301
TPS74801DRCR_SON-10_3X3
D D
3 6 R5305
R5301 4 PG GND1 7 1/20W_2.49K_1%_0201
1 2 U5301_5 5 BIAS SS 8 U5301_8 1 2 R5306
EN FB 0_0603_SP Close Pin24 Close Pin1
1/20W_100K_1%_0201
2 9 U5301_9 1 2
IN2 OUT1

0.01U_25V_K_X7R_0402

0.01U_25V_K_X7R_0402
0.1U_6.3V_K_X7R_0402

0.1U_6.3V_K_X7R_0402

0.1U_6.3V_K_X7R_0402
GND2
1 10 1 1 1 1 1
IN1 OUT2

C5312

C5313

C5314

C5324

C5325
11
1

1
EMC_NS@ 2 2 2 2 2
1 1
@ C5302 R5304 C5304
C5301 22P_25V_J_NPO_0201 1/20W_4.99K_1%_0201 10U_6.3V_M_X5R_0402
10U_6.3V_M_X5R_0402 2
2 2

2
Close Pin15 , Pin18 Close Pin30

VCC3B VCC3B VCC1R2M_PS8409

C C

teknisi-indonesia.com

1
R5307
1/16W_10K_5%_0402

24

30

43
46

15
18

11
1

6
U5302
C5315 VCC3B VCC3B

VDD33_1
VDD33_2

VDD12_1
VDD12_2

VDDRX12_1
VDDRX12_2

VDDTX12_1
VDDTX12_2

VDDA12
1U_25V_K_X5R_0402
2

2
VCC3B @
R5311
RESETB_R 35 37 1/20W_4.7K_1%_0201
4 RESETB POWERSWITCH
PDB

1
R5323 1 @ 2 1/16W_47K_5%_0402 R5308 1 @ 2 1/16W_4.7K_5%_0402 DCIN_ENB 3 27 PRE @ R5309 1 2 1/20W_4.7K_1%_0201
DCIN_ENB PRE
R5324 1 @ 2 1/16W_47K_5%_0402 HDMI_REDRIVER_EQ 5 32 HDMI_ID_R @ R5310 1 2 1/20W_4.7K_1%_0201
EQ HDMI_ID
DDIB_2P C5316 1 2 0.1U_6.3V_K_X5R_0201 DDIB_2P_C 38 23 HDMI_DATA0P
[3] DDIB_2P DDIB_2N DDIB_2N_C IN_D2p OUT_D2p HDMI_DATA0N HDMI_DATA0P [54]
C5317 1 2 0.1U_6.3V_K_X5R_0201 39 22
[3] DDIB_2N IN_D2n OUT_D2n HDMI_DATA0N [54]
DDIB_1P C5318 1 2 0.1U_6.3V_K_X5R_0201 DDIB_1P_C 41 20 HDMI_DATA1P
[3] DDIB_1P IN_D1p OUT_D1p HDMI_DATA1P [54]
DDIB_1N C5319 1 2 0.1U_6.3V_K_X5R_0201 DDIB_1N_C 42 19 HDMI_DATA1N
[3] DDIB_1N DDIB_0P DDIB_0P_C IN_D1n OUT_D1n HDMI_DATA2P HDMI_DATA1N [54]
C5320 1 2 0.1U_6.3V_K_X5R_0201 44 17
[3] DDIB_0P DDIB_0N DDIB_0N_C IN_D0p OUT_D0p HDMI_DATA2N HDMI_DATA2P [54]
C5321 1 2 0.1U_6.3V_K_X5R_0201 45 16
[3] DDIB_0N DDIB_3P DDIB_3P_C IN_D0n OUT_D0n HDMI_CLKP HDMI_DATA2N [54]
C5322 1 2 0.1U_6.3V_K_X5R_0201 47 14
[3] DDIB_3P IN_CLKp OUT_CLKp HDMI_CLKP [54]
DDIB_3N C5323 1 2 0.1U_6.3V_K_X5R_0201 DDIB_3N_C 48 13 HDMI_CLKN
[3] DDIB_3N IN_CLKn OUT_CLKn HDMI_CLKN [54]
R5312 1 @ 2 1/20W_0_5%_0201 I2C_CLK_8409_R 29
[40,85] I2C_CLK_EC I2C_DATA_8409_R CSCL I2C_ADDR
R5313 1 2 1/20W_0_5%_0201 28 31
[40,85] I2C_DATA_EC CSDA I2C_ADDR
@
DDIB_CTRLCLK R5319 1 2 0_0201_SP DDIB_CTRLCLK_R 34 7 HDMI_DDC_CLK
[3] DDIB_CTRLCLK SCL_SRC/AUXP SCL_SNK HDMI_DDC_CLK [54]

1
DDIB_CTRLDATA R5320 1 2 0_0201_SP DDIB_CTRLDATA_R 33 8 HDMI_DDC_DATA @
[3] DDIB_CTRLDATA SDA_SRC/AUXN SDA_SNK HDMI_DDC_DATA [54]
R5315
B B
HDMI_HPD R5314 1 2 1/16W_1K_5%_0402 HDMI_HPD_R 40 21 HDMI_HPD_CONN 1/20W_4.7K_1%_0201
[3] HDMI_HPD HPD_SRC HPD_SNK HDMI_HPD_CONN [54]
2 12

2
25 TESTMODEB CEC_EN 9
NC HDMI_CEC
10
RSV1

EPAD

REXT
26
RSV2
TABLE I2C Address
I2C_ADDR PS8409AQFN48GTR2-A2_QFN48_6X6
49

36
1

1
LOW 0x10-0x2F R5317
R5316 R5318
HIGH 0x90-0x9F;0xD0-0xDF Logic @ 1/20W_100K_5%_0201 REXT 1 2 @ 1/20W_100K_5%_0201
2

2
1/16W_4.99K_1%_0402

VCC3B
2
G
S

DDIB_CTRLCLK R5325 1 @ 2 1/20W_0_5%_0201 3 1 R5327 1 @ 2 1/20W_0_5%_0201 HDMI_DDC_CLK

A A
Q5301
RUM002N05MGT2L_VMT3
@
2
G
S

DDIB_CTRLDATA R5326 1 2 1/20W_0_5%_0201 3 1 R5328 1 2 1/20W_0_5%_0201 HDMI_DDC_DATA

@ @ Title
Security Classification LC Future Center Secret Data
Q5302
RUM002N05MGT2L_VMT3 Issued Date 2015/01/12 Deciphered Date 2016/01/12 HDMI Re-Timer
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 53 of 130

5 4 3 2 1
 A B C D E

EXC24CH900U_4P
HDMI_DATA0N 4 3 HDMI_DATA0N_CONN
[53] HDMI_DATA0N 4 3

HDMI_DATA0P 1 2 HDMI_DATA0P_CONN
[53] HDMI_DATA0P 1 2
L5401 EMC@

EXC24CH900U_4P
HDMI_DATA2N 4 3 HDMI_DATA2N_CONN
[53] HDMI_DATA2N 4 3

HDMI_DATA2P 1 2 HDMI_DATA2P_CONN
[53] HDMI_DATA2P 1 2
1 L5402 EMC@ 1

EXC24CH900U_4P
HDMI_DATA1N 4 3 HDMI_DATA1N_CONN
[53] HDMI_DATA1N 4 3

HDMI_DATA1P 1 2 HDMI_DATA1P_CONN
[53] HDMI_DATA1P 1 2
L5403 EMC@

EXC24CH900U_4P
HDMI_CLKN 4 3 HDMI_CLKN_CONN
[53] HDMI_CLKN 4 3

HDMI_CLKP 1 2 HDMI_CLKP_CONN
[53] HDMI_CLKP 1 2
L5404 EMC@

D5401 RCLAMP0524PATCT_SLP2510P8-10-9

HDMI_DDC_DATA 9 1 HDMI_DDC_DATA
HDMI_DDC_CLK 8 2 HDMI_DDC_CLK
HDMI_HPD_CONN 7 4 HDMI_HPD_CONN
6 5

EMC@
3

VCC5B_HDMI

2 2

D5402 RCLAMP0524PATCT_SLP2510P8-10-9

2
VCC5B R5401
0_0603_SP
HDMI_DATA0N_CONN 9 1 HDMI_DATA0N_CONN
HDMI_DATA0P_CONN 8 2 HDMI_DATA0P_CONN

1
HDMI_CLKN_CONN 7 4 HDMI_CLKN_CONN
HDMI_CLKP_CONN 6 5 HDMI_CLKP_CONN U5401
1 6
IN OUT
5
4 ILIM
FAULT TABLE of Transformer (U5401)

4.7U_6.3V_M_X5R_0402
0.1U_6.3V_K_X7R_0201
EMC@ 3 2
3

EN GND
Vendor LCFC P/N Description

1/20W_61.9K_1%_0201
1 1

1
C5401
TI SA00008F300 S IC TPS2553DDBVR SOT-23 6P USB POWER SW

R5402

C5402
TPS2553DDBVR_SOT23-6
D5403 RCLAMP0524PATCT_SLP2510P8-10-9 2 2 GMT SA00007CY00 S IC G517AL1TB1U SOT-23 6P HDMI POWER SW
DII SA00008NJ00 S IC AP2553W6-7 SOT-26 6P USB POWER SW

2
HDMI_DATA1N_CONN 9 1 HDMI_DATA1N_CONN
HDMI_DATA1P_CONN 8 2 HDMI_DATA1P_CONN
HDMI_DATA2N_CONN 7 4 HDMI_DATA2N_CONN
HDMI_DATA2P_CONN 6 5 HDMI_DATA2P_CONN

EMC@
3

VCC5B_HDMI

VCC5B_HDMI
3 3

JHDMI1

18 15 HDMI_DDC_CLK HDMI_DDC_CLK 1/20W_2.2K_1%_0201 2 1 R5403

+5V_Power SCL HDMI_DDC_DATA HDMI_DDC_CLK [53]
16
SDA HDMI_DDC_DATA [53] HDMI_DDC_DATA 1/20W_2.2K_1%_0201 2 1 R5404
HDMI_DATA0P_CONN 7
HDMI_DATA0N_CONN 9 TMDS_Data0+ 13 HDMI_HPD_CONN 1/20W_100K_1%_0201 1 2 R5405
HDMI_DATA1P_CONN 4 TMDS_Data0- CEC 17 @
HDMI_DATA1N_CONN 6 TMDS_Data1+ DDC/CEC_Ground 19 HDMI_HPD_CONN
HDMI_DATA2P_CONN TMDS_Data1- Hot_Plug_Detect HDMI_HPD_CONN [53]
1
HDMI_DATA2N_CONN 3 TMDS_Data2+
TMDS_Data2-
1
EMC@ 8 14
C5403 5 TMDS_Data0_Shield Utility
0.1U_10V_K_X5R_0201 2 TMDS_Data1_Shield
2 TMDS_Data2_Shield
20
11 GND1 21
HDMI_CLKP_CONN 10 TMDS_Clock_Shield GND2 22
HDMI_CLKN_CONN 12 TMDS_Clock+ GND3 23
TMDS_Clock- GND4

ALLTO_C128AF-K1935-L
ME@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 HDMI CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 54 of 130

A B C D E
 5 4 3 2 1

VCC3P3_SX_TBTB VCC3P3_SX_TBTB [56]

VCC3B VCC3B [3,7,8,10,12,13,33,34,35,36,37,51,52,53,63,64,66,70,73,76,78,85,88,89,91,92,93,97,98,101,127]

VCC3M VCC3M [4,13,16,51,52,56,59,84,85,86,88,102,103,104,105,106,110,116,118,119,120,123,124,125,126,127,128]

VCC3P3_SX_TBTB VCC3B VCC3M

D D

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201
2

2
R5502

R5503

R5504
R5505 R5506
1/20W_10K_5%_0201 1/20W_10K_5%_0201

1
U5501A

TCP1_TX0_DP C5501 1 2 0.22U_6.3V_K_X5R_0201 TCP1_TX0_DP_C J1 G12 TBTB_TX1P

[3] TCP1_TX0_DP TCP1_TX0_DN TCP1_TX0_DN_C ASSRXP1 BSSTXP1 TBTB_TX1N TBTB_TX1P [62]
C5502 1 2 0.22U_6.3V_K_X5R_0201 J2 G11
[3] TCP1_TX0_DN ASSRXN1 BSSTXN1 TBTB_TX1N [62]
TCP1_RX0_DP C5503 1 2 0.22U_6.3V_K_X5R_0201 TCP1_RX0_DP_C G1 J12 TBTB_RX1P
[3] TCP1_RX0_DP ASSTXP1 BSSRXP1 TBTB_RX1P [62]
TCP1_RX0_DN C5504 1 2 0.22U_6.3V_K_X5R_0201 TCP1_RX0_DN_C G2 J11 TBTB_RX1N
[3] TCP1_RX0_DN ASSTXN1 BSSRXN1 TBTB_RX1N [62]
TCP1_TX1_DP C5505 1 2 0.22U_6.3V_K_X5R_0201 TCP1_TX1_DP_C C1 E12 TBTB_TX2P
[3] TCP1_TX1_DP ASSRXP2 BSSTXP2 TBTB_TX2P [62]
TCP1_TX1_DN C5506 1 2 0.22U_6.3V_K_X5R_0201 TCP1_TX1_DN_C C2 E11 TBTB_TX2N
[3] TCP1_TX1_DN ASSRXN2 BSSTXN2 TBTB_TX2N [62]
TCP1_RX1_DP C5507 1 2 0.22U_6.3V_K_X5R_0201 TCP1_RX1_DP_C E1 C12 TBTB_RX2P
[3] TCP1_RX1_DP TCP1_RX1_DN TCP1_RX1_DN_C ASSTXP2 BSSRXP2 TBTB_RX2N TBTB_RX2P [62]
C5508 1 2 0.22U_6.3V_K_X5R_0201 E2 C11
[3] TCP1_RX1_DN ASSTXN2 BSSRXN2 TBTB_RX2N [62]
TCP1_LSTX M7 M10 TBTB_SBU1
[3] TCP1_LSTX PA_LSTX_SBU1 BSBU1 TBTB_SBU1 [62]
TCP1_LSRX L7 L10 TBTB_SBU2
[3] TCP1_LSRX PA_LSRX_SBU2 BSBU2 TBTB_SBU2 [62]
TCP1_AUX_DP L8
[3] TCP1_AUX_DP PA_AUX_P
TCP1_AUX_DN M8
[3] TCP1_AUX_DN PA_AUX_N

RT_SPI_CLK C7 E7 I2C3_DATA_PD
-RT_SPI_CS EE_CLK I2C_SDA I2C3_CLK_PD I2C3_DATA_PD [59]
B6 C9
EE_CS_N I2C_SCL I2C3_CLK_PD [59]
RT_SPI_MOSI C6 A10 -I2C3_INT_PD
EE_DI I2C_INT -I2C3_INT_PD [59]
RT_SPI_MISO B4 B10 RT_FORCE_PWR
EE_DO FORCE_PWR -RT_FLASH_BUSY RT_FORCE_PWR [9,59]
A9
VCC3P3_LC_TBTB FLASH_BUSY_N B9 U5501A_B9
R5507 1 2 1/20W_10K_5%_0201 U5501A_A3 A3 POC_GPIO_5 A8 U5501A_A8
C C
R5508 1 2 1/20W_10K_5%_0201 U5501A_C3 C3 TDI POC_GPIO_6 B8 -RT_PERST
TMS PERST_N -RT_PERST [13]
R5509 1 2 1/20W_10K_5%_0201 U5501A_B5 B5 A7 SML0_CLK
U5501A_C5 TCK SMBUS_SCL SML0_DATA SML0_CLK [7,73]
R5510 1 2 1/20W_10K_5%_0201 C5 B7
TDO SMBUS_SDA U5501A_A4 SML0_DATA [7,73]
A4
POC_GPIO_10 A5 U5501A_A5
POC_GPIO_11 A6 U5501A_A6
POC_GPIO_12
M11
THERMDA
M12 L11 -RT_B_RESET
TEST_EDM RESET_N -RT_B_RESET [59]
B2
FUSE_VQPS_64

1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201
A11 L9 RT_B_XTAL_25_IN
A12 MONDC XTAL_25_IN M9 RT_B_XTAL_25_OUT
L12 NC_A12 XTAL_25_OUT
MONDC_SVR
U5501A_B3 B3 L4 U5501A_L4 R5511 1 2 1/20W_4.75K_0.5%_0201
B11 TEST_PWR_GOOD RBIAS L5 U5501A_L5
TEST_EN RSENSE

2
A1
A2 ATEST_P R5515
ATEST_N

2
1/20W_10K_5%_0201

@ @

1
2

JHL8040RSLMN7A1_BGA105

R5513

R5514

R5521
R5512

1
1/20W_100_5%_0201
VCC3M
1
2

D5501
RB520CM-30T2R_VMN2M2
1

B B

VCC3M_RT_SPI
1/20W_2.2K_5%_0201

1/20W_2.2K_5%_0201

1/20W_3.3K_5%_0201
2

2
RT_B_XTAL_25_OUT
DG_BBR1_FORCE_PWR:
R5519 R5520 1 2 0_0201_SP
C5509 1/20W_3.3K_5%_0201 Connect to EC/PCH for FW update
0.1U_6.3V_K_X5R_0201 RT_B_XTAL_25_IN '0' - by default
1
'1' - for debug only/FW update
R5516 1

R5517 1

R5518 1

Y5501
8

U5502 1 4 3 3 1
9 NC2
VCC

NC C5510 Y5501_1 1 2 C5511

27P_25V_J_C0G_0201 1 NC1 TABLE : Functional Strap
27P_25V_J_C0G_0201
-RT_SPI_CS 1 5 RT_SPI_MOSI 2 25MHZ_18PF_7R25080003 2
/CS DI(IO0) POC_GPIO_10 (Flash Share Strap)
RT_SPI_MISO 2 6 RT_SPI_CLK HIGH Flash is shared between 2 Re-timers
DO(IO1) CLK
U5502_3 3 7 U5502_7 LOW Flash isn't shared. 1 Flash per Re-timer LOGIC
GND

/WP(IO2) /HOLD(IO3)

W25Q80DVUXIE_USON8_2X3
4

TABLE : Functional Strap

POC_GPIO_11 (Master/Slave Strap in Flash Sare Mode)
1MB (8Mb) TABLE of crystal (Y5501)
Winbond W25Q80DVUXIE USON 8P SPI ROM HIGH Set Re-timer to be Master on shared flash SPI I/F LOGIC
GigaDevice GD25Q80CEIGR USON 8P SPI ROM Vendor LCFC P/N Description
LOW Set Re-timer to be Slave on shared flash SPI I/F
TXC SJ10000PS00 S CRYSTAL 25MHZ 18PF +-30PPM 7R25080003
Harmony SJ10000XR00 S CRYSTAL 25MHZ 18PF X2CL025000DI1H-HU
A
Siward SJ10000WC00 S CRYSTAL 25MHZ 18PF XTL501300-U11-421 A

-RT_SPI_CS 1 VCC3M_RT_SPI 1
TP5501 Test_Point_12MIL TP5503 Test_Point_12MIL
RT_SPI_MISO 1 TP5502 Test_Point_12MIL RT_SPI_CLK 1 TP5504 Test_Point_12MIL
RT_SPI_MOSI 1 TP5505 Test_Point_12MIL

TABLE of BB ROM (U6104)

Vendor LCFC P/N Description Security Classification LC Future Center Secret Data Title
Winbond SA00007AF00 S IC FL 8M W25Q80DVUXIE USON 8P SPI ROM Issued Date 2015/01/12 Deciphered Date 2016/01/12 BURNSIDE BRIDGE PORT B (1/2)
GD SA00009ZX00 S IC FL 8M GD25Q80CEIGR USON 8P SPI ROM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 55 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3M VCC3M [4,13,16,51,52,55,59,84,85,86,88,102,103,104,105,106,110,116,118,119,120,123,124,125,126,127,128]

VCC3P3_SX_TBTB VCC3P3_SX_TBTB [55]

VCC3M VCC3M

D D

VCC3P3_SX_TBTB VCC3P3_SX_TBTB VCC3P3A_SX_TBTB

R5601 1 2 0_0402_SP
U5602 L5601
A2 A1 U5602_A1 1 2
VIN1 VOUT1 1UH_LQM18PN1R0MFHD_20% 2 2 2 2 2 2
B2 B1
VIN2 VOUT2
6

U5601 C5603 C5604 C5605 C5607 C5608 C5609

U5602_C2 C2 C1 2.2U_10V_K_X5R_0402 22U_6.3V_M_X5R_0603 22U_6.3V_M_X5R_0603 2.2U_10V_K_X5R_0402 2.2U_10V_K_X5R_0402 2.2U_10V_K_X5R_0402
Vcc

2 CT PG 1 1 1 1 1 1
[59] RT_B_PWR_EN A
5 4 RT_B_PWR_ON D2 D1
1 NC Y ON GND
[13,86] -PCH_SLP_SUS B
Gnd

TPS22971YZPT_DSBGA8

74AUP1G08GS_XSON6 1 1
3

C5601 C5602
1U_6.3V_K_X5R_0402 1200P_25V_K_X7R_0201_MURATA
2 2

R5602 1 2 1/20W_0_5%_0201

C C

VCC3P3_LC_TBTB VCC0P9_SVR_TBTB VCC3P3_SX_TBTB VCC3P3_SX_TBTB VCC3P3A_SX_TBTB VCC0P9_SVR_TBTB

U5501B

E6
VCC3P3_ANA_TBTB L2 VCC3P3_SX
E5 VCC3P3_ANA J5
VCC3P3_LC NC_J5 M4
E3 VCC3P3_SVR_2 M5
G3 VCC0P9_SVR_1 VCC3P3_SVR_3
2 2 VCC0P9_SVR_2 J7
C5610 C5611 F6 VCC3P3A L5602
G6 VCC0P9_SVR_ANA_1 L1 U5501B_L1 1 2
2.2U_10V_K_X5R_0402 2.2U_10V_K_X5R_0402 VCC0P9_SVR_ANA_2 SVR_IND_1
1 1 M1
SVR_IND_2 0.68UH_DFE201610E-R68M-P2_3.1A_20%

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402
E9 Itemp=3.1A
G9 VCC0P9_SVR_PB_ANA_1 M2
VCC0P9_SVR_PB_ANA_2 SVR_VSS_1 Isat=4.3A 2 2 2 2 2 2
M3
VCC0P9_LC_TBTB J3 SVR_VSS_2
VCC0P9_LC

C5619

C5620

C5621

C5622

C5623

C5624
L3 Share Same GND plane
VCC0P9_LVR_TBTB L6 NC_L3 and connect to M2 & M3 1 1 1 1 1 1
VCC0P9_LVR pins (SVR_VSS) of BB

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
M6 J6
B VCC0P9_LVR_SENSE NC_J6 B
2 2 2 2 NEAR PIN

C5615

C5616

C5617

C5618
2 2 2 B1 G7
B12 VSS_ANA_1 VSS_ANA_13 H1
C5612 C5613 C5614 D1 VSS_ANA_2 VSS_ANA_14 H2 1 1 1 1
10U_6.3V_M_X5R_0402 D2 VSS_ANA_3 VSS_ANA_15 H11
2.2U_10V_K_X5R_0402 2.2U_10V_K_X5R_0402 VSS_ANA_4 VSS_ANA_16
1 1 1 D11 H12
D12 VSS_ANA_5 VSS_ANA_17 J9
F1 VSS_ANA_6 VSS_ANA_18 K1
F2 VSS_ANA_7 VSS_ANA_19 K2
F7 VSS_ANA_8 VSS_ANA_20 K11
F9 VSS_ANA_9 VSS_ANA_21 K12
F11 VSS_ANA_10 VSS_ANA_22 Share Same GND
F12 VSS_ANA_11 F3
VSS_ANA_12 VSS_1 F5
VSS_2 G5
VSS_3

JHL8040RSLMN7A1_BGA105

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BURNSIDE BRIDGE PORT B (2/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 56 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 PCIE RE-DRIVER-1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 57 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 PCIE RE-DRIVER-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 58 of 130

5 4 3 2 1
 5 4 3 2 1

VCC5M_PD VCC5M_PD [104]

VINT20_IN VINT20_IN [60,100,102]

VCC3M VCC3M [4,13,16,51,52,55,56,84,85,86,88,102,103,104,105,106,110,116,118,119,120,123,124,125,126,127,128]

VCC3_LDO_PD VCC3_LDO_PD [62,63,85]

TBTB_VBUS20 TBTB_VBUS20 [60,62]

VINT20_IN VCC3M VCC3_LDO_PD

D D
USBC_PD_VBUS20 TBTB_VBUS20

VCC3_LDO_PD
VCC3_LDO_PD

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402
2 2 2

C5901

C5902

1
C5903
R5923 R5907
1 1 1 1/20W_200K_1%_0201
0_0201_SP

2
NSR20F30NXT5G_DSN2-2

NSR20F30NXT5G_DSN2-2
1

1
1U_25V_K_X5R_0402

1U_25V_K_X5R_0402
LDO_1V5
2 2

1
EMC@

EMC@
D5901

C5904

D5902

C5905
VCC5M_PD @
R5906 R5908
1 1 1/20W_200K_1%_0201 1/20W_200K_1%_0201

2
2

2
32

37

34

24
23
22
21

16
15
14
13
3
U5901

VSYS

VIN_3V3

LDO_1V5

LDO_3V3

PA_VBUS_2
PA_VBUS_3
PA_VBUS_4

PB_VBUS_1
PB_VBUS_2
PB_VBUS_3
PB_VBUS_4
PA_VBUS_1
1 1 11
12 PP5V_1
C C
C12785 C12788 17 PP5V_2 33
10U_6.3V_M_X5R_0402 10U_6.3V_M_X5R_0402 20 PP5V_3 ADCIN1
2 2 25 PP5V_4 35 ADCIN2
26 PP5V_5 ADCIN2
PP5V_6
31 USBC_PD_CC1 USBC_PD_CC1 [63]
PA_CC1 30 USBC_PD_CC2
PA_CC2 USBC_PD_CC2 [63]

6 TBTB_PD_CC1 TBTB_PD_CC1 [62]

USBC_PD_GATE_VSYS 5 PB_CC1 7 TBTB_PD_CC2
[60] USBC_PD_GATE_VSYS PA_GATE_VSYS PB_CC2 TBTB_PD_CC2 [62]
USBC_PD_GATE_VBUS 19
[60] USBC_PD_GATE_VBUS PA_GATE_VBUS
VCC3SW_EC VCC3_LDO_PD

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
TBTB_GATE_VSYS 4
[60] TBTB_GATE_VSYS PB_GATE_VSYS
TBTB_GATE_VBUS 18
[60] TBTB_GATE_VBUS PB_GATE_VBUS

1/20W_10K_5%_0201

1/20W_10K_5%_0201
1/20W_2.2K_5%_0201

1/20W_2.2K_5%_0201

1/20W_2.2K_5%_0201

1/20W_2.2K_5%_0201
2 2 2 2

C5906

C5907

C5908

C5909

2
R5910

R5936

R5937

R5911

R5912

R5913
1 1 1 1

TPS65994

1
Need test point bot t o m

[63] AUX_SBU_SEL
AUX_SBU_SEL 45 43 -PD_I2C_INT_R R5914 1 2 0_0402_SP -PD_I2C_INT To EC
-PD_I2C_INT [85]
GPIO0 I2C_EC_IRQ
38 42 I2C_CLK_PD_R R5915 1 2 0_0402_SP I2C_CLK_PD
GPIO1 I2C_EC_SCL I2C_CLK_PD [85]
40 I2C_DATA_PD_R R5916 1 2 0_0402_SP I2C_DATA_PD I2C_DATA_PD [85]
9 I2C_EC_SDA
GPIO2 Slave
-RT_B_RESET 28
B [55] -RT_B_RESET GPIO3 -PMC_ALERT_R -PMC_ALERT B
39 R5917 1 2 0_0402_SP
RT_FORCE_PWR I2C2s_IRQ -PMC_ALERT [13]
2
[9,55] RT_FORCE_PWR GPIO4 41 SML1_CLK_R R5918 1 2 0_0402_SP SML1_CLK
I2C2s_SCL SML1_CLK [7,93]
44 SML1_DATA_R R5919 1 2 0_0402_SP SML1_DATA SML1_DATA [7,93]
46 I2C2s_SDA
GPIO5 Slave
RT_B_PWR_EN 29
[56] RT_B_PWR_EN GPIO6 47 -I2C3_INT_PD_R R5920 1 2 0_0402_SP -I2C3_INT_PD To BB
-I2C3_INT_PD [55]
27 I2C3m_IRQ
GPIO7 1 I2C3_CLK_PD_R R5921 1 2 0_0402_SP I2C3_CLK_PD
I2C3m_SCL I2C3_CLK_PD [55]
-USB_TCSS_OC0 10 48 I2C3_DATA_PD_R R5922 1 2 0_0402_SP I2C3_DATA_PD I2C3_DATA_PD [55]
[10] -USB_TCSS_OC0 GPIO8 I2C3m_SDA_1
Master
Thermal Pad

-PROCHOT R5924 1 2 1/20W_0_5%_0201 -PROCHOT_PD 8

[6,85,102,108] -PROCHOT GPIO9
@ VCC3_LDO_PD
Need test point bot t o m
GND
1/20W_100K_5%_0201

1/20W_100K_5%_0201

0.1U_6.3V_K_X5R_0201

1/20W_0_5%_0201

1/20W_0_5%_0201
36

49

1
SN2001025RSLR_VQFN48_6X6 1

R5931

R5932
C5910
2
@

2
@ @
U5902
1 8
A0 VCC
2 7 I2C3_WP_PD_U5902
A1 WP
1

3 6 I2C3_CLK_PD_U5902
A2 SCL
TABLE I2C Addressing
1/20W_10K_5%_0201

1/20W_10K_5%_0201

1/20W_10K_5%_0201

4 5 I2C3_DATA_PD_U5902
GND1 SDA
Master: EC TBTB PORT 0x24
R5926 2

R5927 2

9 I2C1
GND2
R5928

R5929

R5930

Slave: PD TBTC PORT 0x20

1
AT24C256CMAHL Master: PMC TBTB PORT T.B.D.
A @ R5933 I2C2 A
2

@ @ @ Slave: PD TBTC PORT T.B.D.

1/20W_10K_5%_0201
Master: PD TBTB PORT T.B.D.

2
@ I2C3
Slave: RT TBTC PORT T.B.D.

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 THUNDERBOLT PD(TPS65994-AA)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 59 of 130

5 4 3 2 1
 5 4 3 2 1

VINT20_IN VINT20_IN [59,100,102]

TBTB_VBUS20 TBTB_VBUS20 [59,62]

USBC_PD_VBUS20 USBC_PD_VBUS20 [59,63]

TBTB_VBUS20_F VINT20_IN
D TBTB_VBUS20_F D

USBC_PD_VBUS20_F USBC_PD_VBUS20_F

Q6001
TBTB_VBUS20 TBTB_VBUS20_F CSD87501L_LGA10_3P37X1P47

A1 A2
B1 S1_1 S2_1 B2 J6001
F6001 C1 S1_2 S2_2 C2 JUMP_43X79
1 2 D1 G1 G2 D2 Q6001_1 1 2
E1 S1_3 S2_3 E2 1 2
2 S1_4 S2_4
5A_32V_0438005.WR @
C6001
1U_25V_K_X5R_0402

Q6001_C1

Q6001_C2
1

2
C6002
10U_25V_M_X5R_0603

1
2

2
C R6001 C
R6002
0_0201_SP 0_0201_SP

1
TBTB_GATE_VBUS
teknisi-indonesia.com
[59] TBTB_GATE_VBUS
TBTB_GATE_VSYS
[59] TBTB_GATE_VSYS

USBC_PD_VBUS20 USBC_PD_VBUS20_F Q6002

CSD87501L_LGA10_3P37X1P47

B A1 A2 B
B1 S1_1 S2_1 B2 J6002
F6002 C1 S1_2 S2_2 C2 JUMP_43X79
1 2 D1 G1 G2 D2 Q6002_1 1 2
E1 S1_3 S2_3 E2 1 2
5A_32V_0438005.WR S1_4 S2_4
@

Q6002_C1

Q6002_C2
2

2
C6003 C6004
1U_25V_K_X5R_0402 10U_25V_M_X5R_0603

1
1

2
R6003 R6004
0_0201_SP 0_0201_SP
1

USBC_PD_GATE_VBUS 1
[59] USBC_PD_GATE_VBUS
USBC_PD_GATE_VSYS
[59] USBC_PD_GATE_VSYS
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 TYPEC_DCIN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 60 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 TYPEC PORT (BLANK)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 61 of 130

5 4 3 2 1
 A B C D E

VCC3_LDO_PD

1 VCC3_LDO_PD

C6202

1
1U_6.3V_M_X5R_0201 R6201
2
1/20W_100K_5%_0201
L6201 EMC@
U6201 BLM18KG300TN1D_2P

2
1 2
C4 B4 TBTB_VBUS20
VPWR FLT L6202 EMC@
TBTB_SBU1 D1 B1 TBTB_SBU1_CONN BLM18KG300TN1D_2P
[55] TBTB_SBU1 TBTB_SBU2 SBU1 C_SBU1 TBTB_SBU2_CONN TBTB_VBUS20_CONN
D2 A1 1 2
[55] TBTB_SBU2 SBU2 C_SBU2
TBTB_PD_CC1 D3 A2 TBTB_PD_CC1_CONN
[59] TBTB_PD_CC1 TBTB_PD_CC2 CC1 C_CC1
D4 B2 2 2 2 2
[59] TBTB_PD_CC2 CC2 RPD_G1 EMC@ EMC@ EMC@ EMC@
A3 TBTB_PD_CC2_CONN C6203 C6204 C6205 C6206
C_CC2 B3 100P_50V_J_NPO_0402
RPD_G2 1000P_50V_K_X7R_0402 100P_50V_J_NPO_0402 1000P_50V_K_X7R_0402
1 1 1 1 1 1
C1
C6201 GND1 C2
1 2 A4 GND2 C3
VBIAS GND3

0.1U_50V_K_X7R_0603
SN1904020YBFR_DSBGA16
SA0000APZ00
INSTALL_U6201_S

TBTB_SBU1_CONN R6223 1 2 1/20W_2M_5%_0201

TBTB_SBU2_CONN R6224 1 2 1/20W_2M_5%_0201

TBTB_VBUS20_CONN
TBTB_VBUS20_CONN
JDOCK1

GND1 GND2
GND5 GND6

GND3 GND4
GND5 GND7 GND8
GND9

2 2

A1 B12
TBTB_TX1P_CONN A2 GND1 GND4 B11 TBTB_RX1P_CONN
TBTB_TX1N_CONN A3 TX1+ RX1+ B10 TBTB_RX1N_CONN
A4 TX1- RX1- B9
TBTB_PD_CC1_CONN A5 VBUS1 VBUS4 B8 TBTB_SBU2_CONN
USB2_P8_DP A6 CC1 SBU2 B7 USB2_P8_DN
USB2_P8_DN A7 D1+ D2- B6 USB2_P8_DP
TBTB_SBU1_CONN A8 D1- D2+ B5 TBTB_PD_CC2_CONN
A9 SBU1 CC2 B4
TBTB_RX2N_CONN A10 VBUS2 VBUS3 B3 TBTB_TX2N_CONN
TBTB_RX2P_CONN A11 RX2- TX2- B2 TBTB_TX2P_CONN
A12 RX2+ TX2+ B1
VCC3LAN GND2 GND3

GND6

0.35A_6V_0603L035YR
GND7 GND10 GND8
GND11 GND12

2
F6201 GND9 GND10
GND13 GND14

1
MDI_2N_CONN 1 8 MDI_3N_CONN
MDI_2P_CONN 2 MDI_2N MDI_3N 9 MDI_3P_CONN
-DOCK_LINKUP_SYS R6208 1 2 1/16W_330_5%_0402 -DOCK_LINKUP_SYS_LED 3 MDI_2P MDI_3P 10
[74] -DOCK_LINKUP_SYS DOCK_4 -LINK_LED GND
4 11 -PWRSWITCH
-DOCK_ACTIVITY_SYS -DOCK_ACTIVITY_SYS_LED -ACT_LED -PWRSWITCH -DOCK_RJ45_DET -PWRSWITCH [51,85]
R6209 1 2 1/16W_330_5%_0402 5 12
[74] -DOCK_ACTIVITY_SYS MDI_1N_CONN LED_PWR -DOCK_RJ45_DET MDI_0N_CONN -DOCK_RJ45_DET [74]
6 13
MDI_1P_CONN 7 MDI_1N MDI_0N 14 MDI_0P_CONN
MDI_1P MDI_0P

HIGHS_DK11197-D20A1-1H
ME@

3 3

D6201 EMC@ D6202 EMC@

TBTB_TX1P_C 1 2 2 1 TBTB_RX1P_C
1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

D6203 EMC@ D6204 EMC@

EXC24CH900U_4P
DOCK_MDI_0+ 4 3 MDI_0P_CONN TBTB_TX1N_C 1 2 2 1 TBTB_RX1N_C
[74] DOCK_MDI_0+ 4 3 1 2 2 1

Follow CML PDG DOCK_MDI_0- 1 2 MDI_0N_CONN PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

[74] DOCK_MDI_0- 1 2
R6233 1 2 1/20W_2.2_5%_0201 TBTB_TX1N_C C6215 1 2 0.22U_10V_K_X5R_0201 TBTB_TX1N_CONN L6203 EMC@ D6205 EMC_NS@ D6206 EMC_NS@
[55] TBTB_TX1N
TBTB_PD_CC2_CONN 1 2 2 1 TBTB_SBU1_CONN
R6234 1 2 1/20W_2.2_5%_0201 TBTB_TX1P_C C6217 1 2 0.22U_10V_K_X5R_0201 TBTB_TX1P_CONN L6204 EMC@ 1 2 2 1
[55] TBTB_TX1P DOCK_MDI_1+ MDI_1P_CONN
4 3
[74] DOCK_MDI_1+ 4 3 PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

DOCK_MDI_1- 1 2 MDI_1N_CONN D6207 EMC@ D6208 EMC@

[74] DOCK_MDI_1- 1 2
R6235 1 2 1/20W_2.2_5%_0201 TBTB_TX2P_C C6219 1 2 0.22U_10V_K_X5R_0201 TBTB_TX2P_CONN EXC24CH900U_4P USB2_P8_DP 1 2 2 1 USB2_P8_DN
[55] TBTB_TX2P [10] USB2_P8_DP 1 2 2 1 USB2_P8_DN [10]
D6209 EMC@
R6236 1 2 1/20W_2.2_5%_0201 TBTB_TX2N_C C6220 1 2 0.22U_10V_K_X5R_0201 TBTB_TX2N_CONN L6205 EMC@ PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 MDI_0P_CONN 1
[55] TBTB_TX2N DOCK_MDI_2+ MDI_2P_CONN MDI_0N_CONN D1+ MDI_0P_CONN
4 3 2 10
[74] DOCK_MDI_2+ 4 3 D1- NC4 MDI_0N_CONN
D6210 EMC_NS@ D6211 EMC_NS@ 3 9
8 GND1 NC3 7 MDI_1P_CONN
DOCK_MDI_2- 1 2 MDI_2N_CONN TBTB_SBU2_CONN 1 2 2 1 TBTB_PD_CC1_CONN MDI_1P_CONN 4 GND2 NC2 6 MDI_1N_CONN
[74] DOCK_MDI_2- 1 2 1 2 2 1 MDI_1N_CONN D2+ NC1
5
R6237 1 2 1/20W_2.2_5%_0201 TBTB_RX1N_C C6221 1 2 0.33U_25V_K_X5R_0201 TBTB_RX1N_CONN EXC24CH900U_4P D2-
[55] TBTB_RX1N
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 TPD4EUSB30DQAR_SON10

R6238 1 2 1/20W_2.2_5%_0201 TBTB_RX1P_C C6222 1 2 0.33U_25V_K_X5R_0201 TBTB_RX1P_CONN EXC24CH900U_4P D6212 EMC@ D6213 EMC@
[55] TBTB_RX1P DOCK_MDI_3+ MDI_3P_CONN
4 3 D6214 EMC@
[74] DOCK_MDI_3+ 4 3 TBTB_RX2N_C TBTB_TX2N_C MDI_2P_CONN
1 2 2 1 1
1 2 2 1 MDI_2N_CONN 2 D1+ 10 MDI_2P_CONN
DOCK_MDI_3- 1 2 MDI_3N_CONN 3 D1- NC4 9 MDI_2N_CONN
[74] DOCK_MDI_3- 1 2 GND1 NC3 MDI_3P_CONN
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 8 7
R6239 1 2 1/20W_2.2_5%_0201 TBTB_RX2P_C C6223 1 2 0.33U_25V_K_X5R_0201 TBTB_RX2P_CONN L6206 EMC@ MDI_3P_CONN 4 GND2 NC2 6 MDI_3N_CONN
[55] TBTB_RX2P MDI_3N_CONN D2+ NC1
D6215 EMC@ D6216 EMC@ 5
D2-
R6240 1 2 1/20W_2.2_5%_0201 TBTB_RX2N_C C6224 1 2 0.33U_25V_K_X5R_0201 TBTB_RX2N_CONN TBTB_RX2P_C 1 2 2 1 TBTB_TX2P_C TPD4EUSB30DQAR_SON10
[55] TBTB_RX2N 1 2 2 1
1/20W_220K_5%_0201

1/20W_220K_5%_0201

1/20W_220K_5%_0201

1/20W_220K_5%_0201

4 PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 4
1/20W_220K_5%_0201

1/20W_220K_5%_0201

1/20W_220K_5%_0201

1/20W_220K_5%_0201

1
1

R6229

R6230

R6231

R6232
R6225

R6226

R6227

R6228

2
2

Security Classification LC Future Center Secret Data Title

EVT EA test to check signal. Issued Date 2015/01/12 Deciphered Date 2016/01/12 DOCKING CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 62 of 130

A B C D E
 5 4 3 2 1

VCC3B
VCC3_LDO_PD
VCC3_LDO_PD
L6301 EMC@
AUX_PBIAS BLM18KG300TN1D_2P
[3] AUX_PBIAS

0.1U_25V_M_X7R_0603
1 1 2
AUX_NBIAS USBC_PD_VBUS20
[3] AUX_NBIAS

1/16W_100K_1%_0402

1/16W_100K_1%_0402
1 C6301 L6302 EMC@

1
C6325
1U_6.3V_K_X5R_0201 BLM18KG300TN1D_2P

1
2 1 2 TYPEC_VBUS20_CONN

R6326

R6325
R6304
2 1/20W_10K_5%_0201
U6302
1 1 1 1

2
W=10 mil U6301 W=10 mil C6306 C6307 C6308 C6309

2
8 7 1000P_50V_K_X7R_0402 100P_50V_J_NPO_0402 100P_50V_J_NPO_0402 1000P_50V_K_X7R_0402
VCC NC C4 B4 EMC@ EMC@ EMC@ EMC@
VPWR FLT 2 2 2 2
D D
TCP2_AUX_DP C6321 1 2 0.1U_10V_K_X7R_0402 TCP2_AUX_DP_C R6327 1 2 0_0402_SP TCP2_AUX_DP_R 2 3 TPC2_SBU1 D1 B1 USBC_PD_SBU1_CONN
[3] TCP2_AUX_DP HSD+ D+ SBU1 C_SBU1
TPC2_SBU2 D2 A1 USBC_PD_SBU2_CONN
TCP2_AUX_DN C6322 1 2 0.1U_10V_K_X7R_0402 TCP2_AUX_DN_C R6328 1 2 0_0402_SP TCP2_AUX_DN_R 6 5 SBU2 C_SBU2
[3] TCP2_AUX_DN HSD- D- USBC_PD_CC1 D3 A2 USBC_PD_CC1_CONN
[59] USBC_PD_CC1 CC1 C_CC1
USBC_PD_CC2

100P_50V_J_NPO_0402

100P_50V_J_NPO_0402
[59] USBC_PD_CC2 D4 B2
1 4 CC2 RPD_G1
OE# GND A3 USBC_PD_CC2_CONN
1 1 C_CC2

C6323

C6324
B3
TS3USB31ERSER_UQFN8_1P5X1P5 RPD_G2
VCC3B C1
2 2 GND1 C2
A4 GND2 C3
VBIAS GND3

1/16W_100K_1%_0402
1

R6329

0.1U_50V_K_X5R_0402
2 SN1904020YBFR_DSBGA16

C6310
SA0000APZ00

2
INSTALL_U6301_S
1 TYPEC_VBUS20_CONN

AUX_SBU_SEL
[59] AUX_SBU_SEL

GND3

GND2

GND1
ME@
JUSBC1

GND7

GND6

GND5
TABLE of PROTECTOR (U6301)
Vendor LCFC P/N Description
TI SA0000APZ00 S IC SN1904020YBFR PORT PROTECTION B12 A1
GND4 GND1
USBC_PD_RX0P_CONN B11 A2 USBC_PD_TX0P_CONN
SSRXP1 SSTXP1
USBC_PD_RX0N_CONN B10 A3 USBC_PD_TX0N_CONN
SSRXN1 SSTXN1
B9 A4
C VBUS1 VBUS2 C
USBC_PD_SBU2_CONN B8 A5 USBC_PD_CC1_CONN
SBU2 CC1
USB2_P6_DN_CONN B7 A6 USB2_P6_DP_CONN
DN2 DP1
USB2_P6_DP_CONN B6 A7 USB2_P6_DN_CONN
DP2 DN1
USBC_PD_CC2_CONN B5 A8 USBC_PD_SBU1_CONN
CC2 SBU1
B4 A9
VBUS3 VBUS4
USBC_PD_TX1N_CONN B3 A10 USBC_PD_RX1N_CONN
SSTXN2 SSRXN2
USBC_PD_TX1P_CONN B2 A11 USBC_PD_RX1P_CONN
SSTXP2 SSRXP2
USBC_PD_SBU1_CONN R6307 1 2 1/20W_2M_5%_0201 B1 A12
GND3 GND2

USBC_PD_SBU2_CONN R6309 1 2 1/20W_2M_5%_0201

GND10

GND9

GND8
HIGHS_UB11247-0500C-1H

GND6

GND5

GND4
FL6301 EMC@
USB2_P6_DN_CONN 4 3 USB2_P6_DN
4 3 USB2_P6_DN [10]

USB2_P6_DP_CONN 1 2 USB2_P6_DP
1 2 USB2_P6_DP [10]
EXC24CH900U_4P

B D6301 EMC@ D6302 EMC@ B

USBC_PD_TX0P_CONN 1 2 1 2 USBC_PD_RX0P_CONN
TCP2_TX0_DN R6311 1 2 0_0402_SP USBC_PD_TX0N_C C6313 1 2 0.1U_6.3V_K_X7R_0201 USBC_PD_TX0N_CONN 1 2 1 2
[3] TCP2_TX0_DN
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
TCP2_TX0_DP R6312 1 2 0_0402_SP USBC_PD_TX0P_C C6314 1 2 0.1U_6.3V_K_X7R_0201 USBC_PD_TX0P_CONN
[3] TCP2_TX0_DP
D6303 EMC@ D6304 EMC@

USBC_PD_TX0N_CONN 1 2 1 2 USBC_PD_RX0N_CONN
1 2 1 2

TCP2_TX1_DP R6313 1 2 0_0402_SP USBC_PD_TX1P_C C6315 1 2 0.1U_6.3V_K_X7R_0201 USBC_PD_TX1P_CONN PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

[3] TCP2_TX1_DP
D6305 EMC_NS@ D6310 EMC_NS@
TCP2_TX1_DN R6314 1 2 0_0402_SP USBC_PD_TX1N_C C6316 1 2 0.1U_6.3V_K_X7R_0201 USBC_PD_TX1N_CONN
[3] TCP2_TX1_DN USBC_PD_CC2_CONN USBC_PD_CC1_CONN
1 2 2 1
1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

TCP2_RX0_DN R6315 1 2 0_0402_SP USBC_PD_RX0N_C C6317 1 2 0.33U_25V_K_X5R_0201 USBC_PD_RX0N_CONN D6307 EMC@ D6308 EMC@
[3] TCP2_RX0_DN
USB2_P6_DP_CONN 1 2 1 2 USB2_P6_DN_CONN
TCP2_RX0_DP R6316 1 2 0_0402_SP USBC_PD_RX0P_C C6318 1 2 0.33U_25V_K_X5R_0201 USBC_PD_RX0P_CONN 1 2 1 2
[3] TCP2_RX0_DP
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

D6311 EMC@ D6312 EMC@

TCP2_RX1_DP R6317 1 2 0_0402_SP USBC_PD_RX1P_C C6319 1 2 0.33U_25V_K_X5R_0201 USBC_PD_RX1P_CONN
[3] TCP2_RX1_DP USBC_PD_RX1N_CONN USBC_PD_TX1N_CONN
1 2 1 2
1 2 1 2
TCP2_RX1_DN R6318 1 2 0_0402_SP USBC_PD_RX1N_C C6320 1 2 0.33U_25V_K_X5R_0201 USBC_PD_RX1N_CONN
[3] TCP2_RX1_DN
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
1/20W_220K_5%_0201

1/20W_220K_5%_0201

1/20W_220K_5%_0201

1/20W_220K_5%_0201

D6313 EMC@ D6314 EMC@

1

1
R6321

R6322

R6323

R6324

USBC_PD_RX1P_CONN 1 2 1 2 USBC_PD_TX1P_CONN
1 2 1 2

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
2

A A

EVT EA test to check signal.

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 TYPE-C CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 63 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3B VCC3B_SSD VCC3B VCC3B

D D

2
R6408 R6401

2
1/8W_0_5%_0805 0_0805_SP R6403
R6402 1/20W_10K_5%_0201
1/20W_10K_5%_0201

1
1
JSSD2
76
GND15
1 2 VCC3B_R_SSD
3 GND1 3.3V_1 4
5 GND2 3.3V_2 6 D6401
[10] PCIE4_L3_RXN PERn3 N/C_2
7 8 -PLP_INT 2 1
[10] PCIE4_L3_RXP PERp3 N/C_3 -PWRSW_EC [13,86]
9 10
C6401 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L3_TXN_C 11 GND3 DAS/DSS#(I/O)/LED1#(I)(0/3.3V) 12 RB520CM-30T2R_VMN2M2
[10] PCIE4_L3_TXN PETn3 3.3V_3
C6402 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L3_TXP_C 13 14
[10] PCIE4_L3_TXP PETp3 3.3V_4
15 16
17 GND4 3.3V_5 18
[10] PCIE4_L2_RXN PERn2 3.3V_6
19 20
[10] PCIE4_L2_RXP PERp2 N/C_4
-SSD_DTCT 21 22
[85] -SSD_DTCT GND5 N/C_5
C6403 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L2_TXN_C 23 24

teknisi-indonesia.com
[10] PCIE4_L2_TXN PETn2 N/C_6
C6404 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L2_TXP_C 25 26 @ TP6401
[10] PCIE4_L2_TXP PETp2 N/C_7
27 28 Test_Point_20MIL
29 GND6 N/C_8 30 -PLP_FDBK 1
[10] PCIE4_L1_RXN PERn1 N/C_9
31 32
[10] PCIE4_L1_RXP PERp1 N/C_10
33 34
C6405 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L1_TXN_C 35 GND7 N/C_11 36
[10] PCIE4_L1_TXN PCIE4_L1_TXP_C PETn1 N/C_12 SATA1_DEVSLP
C6406 1 2 0.22U_6.3V_K_X5R_0201 37 38
[10] PCIE4_L1_TXP PETp1 DEVSLP(O) SATA1_DEVSLP [10]
39 40
41 GND8 N/C_13 42
[10] PCIE4_L0_RXN PERn0/SATA-B+ N/C_14
43 44
[10] PCIE4_L0_RXP PERp0/SATA-B- N/C_15
45 46
C6407 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L0_TXN_C 47 GND9 N/C_16 48
C C
[10] PCIE4_L0_TXN PETn0/SATA-A- N/C_17
C6408 1 2 0.22U_6.3V_K_X5R_0201 PCIE4_L0_TXP_C 49 50 -SSD_RTD3_RST
[10] PCIE4_L0_TXP PETp0/SATA-A+ PERST#(O)(0/3.3V) or N/C
51 52 -CLKREQ_PCIE4
-PCIE4_CLK_100M GND10 CLKREQ#(I/O)(0/3.3V) or N/C -CLKREQ_PCIE4 [12]
53 54
[12] -PCIE4_CLK_100M PCIE4_CLK_100M REFCLKn PEWAKE#(I/O)(0/3.3V) or N/C
55 56
[12] PCIE4_CLK_100M REFCLKp N/C_18
57 58
GND11 N/C_19

67 68
69 N/C_1 SUSCLK(32kHz)(O)(0/3.3) 70
71 PEDET(NC-PCIe/GND-SATA) 3.3V_7 72
73 GND12 3.3V_8 74
[7] M2_CARD_DET GND13 3.3V_9
75
GND14 77
GND16
1

R6404 ARGOS_NASM0-S6705-TSH4
@ 1/20W_0_5%_0201 ME@
VCC3B VCC3B
1 1
2

C6409 C6410
10U_0402_6.3V6-M 10U_0402_6.3V6-M
2 2

1
R6405
@ 1/20W_10K_5%_0201

2
U6401

-PLTRST_FAR 1 5
[13,37,51,66,73,76] -PLTRST_FAR IN B VCC
2
B [8] -SSD_RTD3_RST_CPU IN A B
3 4 -SSD_RTD3_RST
GND OUT Y

NL17SZ08DFT2G_SC70-5

1
@
R6406
@ 1/20W_100K_5%_0201

2
-PLTRST_FAR R6407 1 2 1/20W_0_5%_0201 -SSD_RTD3_RST

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 M.2 SOCKET 3 MODULE I/F-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 64 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 65 of 130

5 4 3 2 1
 5 4 3 2 1

VCC5M VCC5M [51,69,70,72,84,85,103,107,108,109,110,116,117,118,119,120,125,126,127]

VCC3M VCC3M [4,13,16,51,52,55,56,59,84,85,86,88,102,103,104,105,106,110,116,118,119,120,123,124,125,126,127,128]

D D
VCC3B VCC3B [3,7,8,10,12,13,33,34,35,36,37,51,52,53,55,63,64,70,73,76,78,85,88,89,91,92,93,97,98,101,127]

TYPE-A NGFF SLOT FOR WLAN

3.2H CONNECTOR
VCC3B

2
R6613
1/20W_10K_5%_0201
VCC3B
1

VCC3WLAN

JWLAN1
C C
1 2
USB2_P10_DP 3 GND1 3.3VAUX1 4
[10] USB2_P10_DP USB_D+ 3.3VAUX2

1
USB2_P10_DN 5 6 R6604 R6605
[10] USB2_P10_DN USB_D- KEY A LED1# 1

1/16W_49.9K_1%_0402
7 8
GND2 NC

1/16W_49.9K_1%_0402
9 10 C6607 @ @
NC NC
4.7U_6.3V_K_X5R_0603
11 NC NC 12 2
13 14

2
NC NC
15 16
NC LED2#
17 18
19 MLDIR_SENSE GND16 20
21 DP_ML3N DP_AUXN 22
23 DP_ML3P DP_AUXP 24
25 GND3 GND13 26 R6606 1 @ 2 1/16W_0_5%_0402
DP_ML2N DP_ML1N UART_RX [8,84]
27 28
29 DP_ML2P DP_ML1P 30 R6607 1 @ 2 1/16W_0_5%_0402
GND4 GND14 UART_TX [8,84]
31 32
33 DP_HPD DP_ML0N 34
PCIE12_TXP C6603 1 2 0.1U_6.3V_K_X5R_0201 PCIE12_TXP_C 35 GND5 DP_ML0P 36
[10] PCIE12_TXP PETP0 GND15
PCIE12_TXN C6604 1 2 0.1U_6.3V_K_X5R_0201 PCIE12_TXN_C 37 38 -CL_RST_WLAN
[10] PCIE12_TXN PETN0 RESERVED1 -CL_RST_WLAN [7]
39 40 CL_DATA_WLAN
GND6 RESERVED2 CL_DATA_WLAN [7]
PCIE12_RXP R6614 1 2 0_0201_SP PCIE12_RXP_R 41 42 CL_CLK_WLAN
[10] PCIE12_RXP PERP0 RESERVED3 CL_CLK_WLAN [7]
PCIE12_RXN R6615 1 2 0_0201_SP PCIE12_RXN_R 43 44
[10] PCIE12_RXN PERN0 COEX3
45 46
PCIE12_CLK_100M 47 GND7 COEX2 48
B [12] PCIE12_CLK_100M B
-PCIE12_CLK_100M 49 REFCLKP0 COEX1 50 SUS_CLK
[12] -PCIE12_CLK_100M REFCLKN0 SUSCLK SUS_CLK [12]
51 52 PRERST0_N R6608 1 2 0_0402_SP -PLTRST_FAR
GND8 PERST0# -PLTRST_FAR [13,37,51,64,73,76]
-CLKREQ_PCIE12 53 54 BDC_ON_R
[12] -CLKREQ_PCIE12 CLKREQ0# W_DISABLE2#
55 56 -WLAN_RF_KILL
PEWAKE0# W_DISABLE1# -WLAN_RF_KILL [8]
57 58
59 GND9 I2C_DATA 60
PU +3VALW, To EC -EC_WLAN_WAKE R6602 1 2 0_0402_SP -WLAN_WAKE 61 PETP1 I2C_CLK 62
[85] -EC_WLAN_WAKE PETN1 ALERT#
63 64 EC_TX_WLAN R6609 1 2 1/16W_100_1%_0402 EC_TX
GND10 RESERVED4 EC_TX [86]
R6603 1 @ 2 1/16W_0_5%_0402 65 66
[13] -PCIE_WAKE PERP1 PERST1#
67 68 NEED CHECK SPEC
PERN1 CLKREQ1#

1
69 70 R6610 1 2 0_0402_SP BDC_ON
PU +3VALW, To PCH PCIE_WAKE# 71 GND11 PEWAKE1# 72 R81068
BDC_ON [9]
73 REFCLKP1 3.3VAUX4 74 R6611 1 2 1/16W_100_1%_0402 EC_RX
REFCLKN1 3.3VAUX5 EC_RX [86]
75
GND12 1/16W_100K_5%_0402

2
76 77
PEG1 PEG2
ARGOS_NASA0-S6705-TSH4
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 WLAN NGFF CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 66 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 M.2 SOCKET 2 MODULE I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 67 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 68 of 130

5 4 3 2 1
 5 4 3 2 1

VCC5M VCC5M [51,70,72,84,85,103,107,108,109,110,116,117,118,119,120,125,126,127]

USB_PWR_S2 USB_PWR_S2

USB AOU

USB3P2_TXN C6901 1 2 0.1U_10V_K_X7R_0402 USB3P2_TXN_C R6901 1 2 0_0201_SP USB3P2_TXN_CONN

D [10] USB3P2_TXN D

VCC5M USB_PWR_S2 USB3P2_TXP C6902 1 2 0.1U_10V_K_X7R_0402 USB3P2_TXP_C R6902 1 2 0_0201_SP USB3P2_TXP_CONN

[10] USB3P2_TXP
Current Limit Target:
2.3A(2.1-2.45A)
U6901

1 16 U6901_ILIM_HI R6906 1 2 1/16W_22.1K_1%_0402

IN ILIM_HI
USB2_P9_DN 2 15 U6901_ILIM_LO R6905 1 2 1/16W_2.7M_5%_0402
[10] USB2_P9_DN DM_OUT ILIM_LO
USB2_P9_DP 3 14
[10] USB2_P9_DP DP_OUT GND
4 13 -USB_PORT3_OC3 -USB_PORT3_OC3 [10] USB3P2_RXN R6903 1 2 0_0201_SP USB3P2_RXN_CONN
ILIM_SEL FAULT [10] USB3P2_RXN
USB_ON2 5 12
[85] USB_ON2 EN OUT USB3P2_RXP R6904 1 2 0_0201_SP USB3P2_RXP_CONN
[10] USB3P2_RXP
AOU_SEL1 6 11 USB2_P9_DN_AOU
[85] AOU_SEL1 CLT1 DM_IN
7 10 USB2_P9_DP_AOU
CLT2 DP_IN

E_PAD
AOU_SEL2 8 9 -AOU_IFLG -AOU_IFLG [85]
[85] AOU_SEL2 CLT3 STATUS
1
C6903
17

0.1U_10V_K_X7R_0402 SN1702001RTER_WQFN16_3X3
2
@ TI SN1702001RTER
INSTALL_U6901_S
EXC24CH900U_4P
USB2_P9_DP_AOU 4 3 USB2_P9_DP_CONN
4 3

USB2_P9_DN_AOU 1 2 USB2_P9_DN_CONN
1 2
C FL6903 C
EMC@

D6901
TABLE of POWER SWITCH (U6901)
1 USB3P2_TXP_CONN USB_PWR_S2
Vendor LCFC P/N Description CH1
USB3P2_TXP_CONN 9 2 USB3P2_TXN_CONN
TI SA00008HF00 S IC SN1702001RTER WQFN 16P USB CHARGING NC_4 CH2
USB3P2_TXN_CONN 8
PERICOM SA00009D800 S IC PI5USB2546HZHEX TQFN 16P CONTROLLER NC_3
1 1
3 2 EMC@ 2 EMC@
VN C6904 C6905 + C6906 C6907
USB3P2_RXP_CONN 7 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 150U_B2_6.3VM_R35M 470P_50V_J_NPO_0402
CLT1 CLT2 CLT3 ILIM_SEL MOD NC_2 2
USB3P2_RXN_CONN 6 4 USB3P2_RXP_CONN 1 1 2
NC_1 CH3
0 0 0 X DCH OUT held low
5 USB3P2_RXN_CONN JUSB1 ME@
CH4
1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active USB3P2_TXP_CONN 9
* AOZ8808DI-05_DFN-10-10-9_2P5X1
EMC@ USB3P2_TXN_CONN
1
8
StdA_SSTX+
VBUS
* 1 1 1 0 SDP2 Data Connected USB2_P9_DP_CONN 3
7
StdA_SSTX-
D+
B
D6902 USB2_P9_DN_CONN 2 GND_DRAIN 10 B

* 1 1 0 X SDP1 Data Connected USB2_P9_DN_CONN 1 6 USB2_P9_DP_CONN USB3P2_RXP_CONN 6

4
D-
StdA_SSRX+
GND_2
GND_3
11
12
USB_PWR_S2 USB3P2_RXN_CONN 5 GND_1 GND_4 13
* 0 1 0 X SDP1 Data Connected
2 5
StdA_SSRX- GND_5

ALLTO_C190BF-10935-L
1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

3 4
1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode
CM1293A-04SO_SC-74-6
EMC@
0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active
*
0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 USB TYPE-A CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 69 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3B

D D

1
R7001
1/20W_100K_5%_0201
VCC5M

2
JBTB1
1 2
USB2_P1_DN 3 1 2 4
[10] USB2_P1_DN 3 4
[10] USB2_P1_DP USB2_P1_DP 5 6
5 6
2

7 8
R7002 USB3P1_TXP 9 7 8 10
[10] USB3P1_TXP 9 10
0_0805_SP [10] USB3P1_TXN USB3P1_TXN 11 12
13 11 12 14
USB3P1_RXP 15 13 14 16
[10] USB3P1_RXP
1

USB3P1_RXN 17 15 16 18 HP_L_JACK_L
[10] USB3P1_RXN 17 18 HP_L_JACK_L [84]
19 20 HP_R_JACK_L
19 20 HP_R_JACK_L [84]
-USB_PORT4_OC2 21 22
[3] -USB_PORT4_OC2 21 22
C 23 24 C
VCC5M_F

-USB_ON1 25 23 24 26 MIC_RING2
[85] -USB_ON1 25 26 MIC_RING2 [81]
SENSE_A 27 28 MIC_SLEEVE
[78] SENSE_A 27 28 MIC_SLEEVE [81]
HP_JACK_IN 29 30
[8] HP_JACK_IN 29 30
31 32
33 31 32 34
35 33 34 36
37 35 36 38
39 37 38 40
39 40
41
GND1 42
GND2 43
GND3 44
GND4

www.teknisi-indonesia.com FOX_QT510406-2101-9H

ME@
B B

Pin 44 change to NC , For Layout request

Do not rount at AGND
AGND

A A
Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 USB TYPE-A CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 70 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
5 4 3 2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
 5 4 3 2 1

VCC5B

SMART CARD CONN.

1
R7205
1/10W_0_5%_0603
@ VCC5B_SMART

2
D VCC3_SUS D

20180706

1
Add pull high Res , avoid float configre
R7202

2
F7201 1/20W_4.7K_5%_0201
JSC1

1A_32V_ERBRD1R00X

2
-SC_DTCT 6 8
[9] -SC_DTCT 6 GND2
5 7

1
4 5 GND1
USB2_P5_DP 3 4
[10] USB2_P5_DP 3
USB2_P5_DN 2
[10] USB2_P5_DN 2
VCC5B_F 1
1
20190114
Co-lay 0 Ohm and Fruse for Safety test HIGHS_FC5AF061-2121H
ME@
1 Place BOT side
@ C7201
0.1U_10V_K_X5R_0402_MURATA
2
C C

VCC5M

1/16W_10K_5%_0402
2
R7203
1

D7201 1 2 VCC5B_SMARTCARD_ON
[52,78,86,106,125,127] B_ON
RB521CM-30T2R_VMN2M-2
D7202 1 2
[8] SMARTCARD_ON
RB521CM-30T2R_VMN2M-2

B B

VCC5B
VCC5B_SMART

TABLE of POWER SWITCH (U7201)

W= 60 mil
Vendor LCFC P/N Description
1

R7204 U7201
@ 5 1 VCC5B_SMART GMT SA000074R00 S IC G524B1T11U SOT23 5P POWER SWITCH
1/16W_10K_5%_0402 IN OUT
2 RICHTEK SA0000AGK00 S IC RT9742NGJ5 TSOT-23-5 5P PWR SW
2

GND
VCC5B_SMARTCARD_ON 4 3 SILERGY SA000074P00 S IC SY6288C20AAC SOT23 5P POWER SWITCH
EN OC
G524B1T11U_SOT23-5
SA000074R00

Smart@ for MODS Smart Card SKU

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 Smart Card Reader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 72 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3GBE VCC3GBE [74,75]

VCC3LAN VCC3GBE
place near the PHY
D D

R7301 2 1 0_0603_SP

1
1 2 2
C7304 C7302 C7303
C7301 0.1U_10V_K_X5R_0402_MURATA 22U_6.3V_M_X5R_0603 0.1U_6.3V_K_X5R_0201
2
2 1 1
0.1U_10V_K_X5R_0402_MURATA VCC3GBE VCC3B VCC3GBE

When use Native function, intel

1/20W_100K_5%_0201
recommend pull high 10K ohm.
This part is un-mount in Sting.

2
@R7304

R7302
R7303
1/20W_10K_5%_0201 1/20W_10K_5%_0201

1
U7301
TABLE
-CLKREQ_PCIE9 48 13 MDI_0P vPro Capability
[12] -CLKREQ_PCIE9 CLK_REQ_N MDI_PLUS[0] MDI_0P [74]
-PLTRST_FAR 36 14 MDI_0N MDI_0N [74]
[13,37,51,64,66,76] -PLTRST_FAR PE_RST_N MDI_MINUS[0]
PCIE9_CLK_100M 44 17 MDI_1P GbE
[12] PCIE9_CLK_100M PE_CLKP MDI_PLUS[1] MDI_1P [74]
-PCIE9_CLK_100M 45 18 MDI_1N MDI_1N [74] Yes No
[12] -PCIE9_CLK_100M PE_CLKN MDI_MINUS[1]
PHY

PCIE
MDI
PCIE9_RXP C7305 1 2 0.1U_6.3V_K_X5R_0201 PCIE9_RXP_C 38 20 MDI_2P MDI_2P [74]
[10] PCIE9_RXP PETp MDI_PLUS[2]
PCIE9_RXN C7306 1 2 0.1U_6.3V_K_X5R_0201 PCIE9_RXN_C 39 21 MDI_2N
[10] PCIE9_RXN PETn MDI_MINUS[2] MDI_2N [74]
U13 Jacksonville-LM Jacksonville-V
PCIE9_TXP C7307 1 2 0.1U_6.3V_K_X5R_0201 PCIE9_TXP_C 41 23 MDI_3P MDI_3P [74]
[10] PCIE9_TXP PERp MDI_PLUS[3]
PCIE9_TXN C7308 1 2 0.1U_6.3V_K_X5R_0201 PCIE9_TXN_C 42 24 MDI_3N MDI_3N [74]
[10] PCIE9_TXN PERn MDI_MINUS[3]
VCC3GBE
C SML0_CLK SML0_CLK 28 6 7309 R7306 1 2 0_0201_SP C
[7,55] SML0_CLK SMB_CLK SVR_EN_N
SML0_DATA SML0_DATA 31 LOGIC

SMBUS
[7,55] SML0_DATA SMB_DATA 1 7310 R7308 1 2 1/20W_4.7K_5%_0201
RSVD1_VCC3P3
[13] -LANWAKE -LANWAKE 2 5
LANPHYPC R7309 1 2 0_0201_SP LANPHYPC_R 3 LANWAKE_N VDD3P3_IN
[13] LANPHYPC LAN_DISABLE_N 4
VDD3P3_4
15 C7309 1 2 1U_6.3V_K_X5R_0402
-RJ45_LINKUP 26 VDD3P3_15 19
[13,74] -RJ45_LINKUP -RJ45_ACTIVITY LED0 VDD3P3_19
27 29
[74] -RJ45_ACTIVITY LED1 VDD3P3_29
25

LED
LED2
VCC3GBE 47
VDD0P9_47 46
32 VDD0P9_46 37
34 JTAG_TDI VDD0P9_37
R7310 1 2 1/20W_10K_5%_0201 7302 33 JTAG_TDO 43
KEEP SHORT AND WIDE

JTAG
R7311 1 2 1/20W_10K_5%_0201 7303 35 JTAG_TMS VDD0P9_43 PATTERN
JTAG_TCK 11
VDD0P9_11
R7312 1 2 1/20W_470_5%_0201 7312 9 40
7304 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
VDD0P9_16 8
Y7301 7305 30 VDD0P9_8
TEST_EN FL7301
7307 1 3 7306 12 7 7308 1 2 7311
1 3 RBIAS CTRL0P9 4.7UH_NRS2012T4R7MGJ_20%
GND1 GND2 49
GND
2 4 2 2 2
WGI219LM-QREF-A0_QFN48_6X6
C7310 C7311 @ C7312
2 2 INSTALL_U7301_S
2

2
C7313 C7314 place near the PHY 22U_6.3V_M_X5R_0603 0.1U_6.3V_K_X5R_02010.1U_6.3V_K_X5R_0201
@ R7313 R7314 R7315 @ 1 1 1
12P_25V_JC_NPO_0201 25MHZ_10PF_8Y25000010 12P_25V_JC_NPO_0201 1/20W_1K_5%_0201
1/20W_3.01K_1%_0201
1 1 1/20W_10K_5%_0201
1

1
B B

U7301 GBE PHY

Model P/N

vPro WGI219LM SA000073020

TABLE of crystal (Y7301)
non-vPro WGI219V SA000072Z20
Vendor LCFC P/N Description
TXC SJ10000FY10 S CRYSTAL 25MHZ 10PF +-30PPM 8
KDS SJ10000MN00 S CRYSTAL 25MHZ 10PF 1ZZHAE25000CC0B
Harmony SJ10000W900 S CRYSTAL 25MHZ 10PF X2CL025000DA1H-HX

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 GBE JACKSONVILLE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 73 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3GBE VCC3GBE [73,75]

VCC3GBE

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
VCC3GBE
D D

2 2 2 2 2

2
R7401 @
1/20W_4.7K_5%_0201 @
1 1 1 1 1

C7401

C7402

C7403

C7404

C7405
1

39
30
21
14
8
4
1
U7401

VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
38 DOCK_MDI_3-
B0+ DOCK_MDI_3- [62]
37 DOCK_MDI_3+
B0- DOCK_MDI_3+ [62]
MDI_3N 2
[73] MDI_3N A0+ 34 DOCK_MDI_2-
B1+ DOCK_MDI_2- [62]
MDI_3P 3 33 DOCK_MDI_2+
[73] MDI_3P A0- B1- DOCK_MDI_2+ [62]
29 DOCK_MDI_1-
B2+ DOCK_MDI_1- [62]
C
MDI_2N 6 28 DOCK_MDI_1+ C
[73] MDI_2N A1+ B2- DOCK_MDI_1+ [62]
MDI_2P 7 25 DOCK_MDI_0-
[73] MDI_2P A1- B3+ DOCK_MDI_0- [62]
24 DOCK_MDI_0+
B3- DOCK_MDI_0+ [62]
MDI_1N 9 17 -DOCK_ACTIVITY_SYS -DOCK_ACTIVITY_SYS [62]
[73] MDI_1N A2+ LEDB0 18 -DOCK_LINKUP_SYS -DOCK_LINKUP_SYS [62]
MDI_1P 10 LEDB1 41
[73] MDI_1P A2- LEDB2
36 SYS_MDI_3-
C0+ SYS_MDI_3- [75]
MDI_0N 11 35 SYS_MDI_3+
[73] MDI_0N A3+ C0- SYS_MDI_3+ [75]
MDI_0P 12 32 SYS_MDI_2-
[73] MDI_0P A3- C1+ SYS_MDI_2- [75]
31 SYS_MDI_2+
C1- SYS_MDI_2+ [75]
-DOCK_RJ45_DET 13 27 SYS_MDI_1-
[62] -DOCK_RJ45_DET SEL C2+ SYS_MDI_1- [75]
26 SYS_MDI_1+
C2- SYS_MDI_1+ [75]
-RJ45_ACTIVITY 15 23 SYS_MDI_0-
[73] -RJ45_ACTIVITY LEDA0 C3+ SYS_MDI_0- [75]
-RJ45_LINKUP 16 22 SYS_MDI_0+
[13,73] -RJ45_LINKUP LEDA1 C3- SYS_MDI_0+ [75]
42
LEDA2 19 -RJ45_ACTIVITY_SYS
LEDC0 -RJ45_ACTIVITY_SYS [75]
5 20 -RJ45_LINKUP_SYS -RJ45_LINKUP_SYS [75]
PD LEDC1 40
B LEDC2 B
43
PAD_GND

PI3L720ZHEX_TQFN42_9X3P5

SA00007E900
INSTALL_U7401_S

TABLE of LAN SWITCH (U7401)

Vendor LCFC P/N Description
PERICOM SA00007E900 S IC PI3L720ZHE+CX TQFN GBE LA
TI SA000072400 S IC TS3L501ERUAR WQFN 42P LAN

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 LAN SWITCH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 74 of 130

5 4 3 2 1
 5 4 3 2 1

TABLE of Transformer (TL7501)

Vendor LCFC P/N Description
BOTHHAND SP050008B00 S X'FORM_ NA0069R LF LAN
TAIMAG SP050009U00 S X'FORM_ IH-189-G LAN
D D

LAN X' FORM

TL7501
RJ45 Conn.
JRJ1 ME@
SYS_MDI_3- 1 1:1 -RJ45_ACTIVITY_SYS A1
[74] SYS_MDI_3- TD1+ T1/B VCC3GBE [74] -RJ45_ACTIVITY_SYS Yellow_LED-
24 RJ45_TXD3-
TX1+ R7501 1 2 1/16W_330_5%_0402 0401 A2
Yellow_LED+
SYS_MDI_3+ 2 RJ45_TXD0+ 1
[74] SYS_MDI_3+ TD1- PR1+
23 RJ45_TXD3+ RJ45_TXD0- 2
TX1- PR1-
3 22 0306 RJ45_TXD1+ 3
TDCT1 T1/A TXCT1 PR2+
RJ45_TXD2+ 4
4 21 0305 PR3+
TDCT2 1:1 TXCT2
SYS_MDI_2- 5 T1/B RJ45_TXD2- 5
[74] SYS_MDI_2- TD2+ PR3-
20 RJ45_TXD2-
TX2+ RJ45_TXD1- 6
PR2-
RJ45_TXD3+ 7 GND2
SYS_MDI_2+ 6 PR4+ GND2
[74] SYS_MDI_2+ TD2- 19 RJ45_TXD2+ RJ45_TXD3- 8 GND1
TX2- PR4- GND1
-RJ45_LINKUP_SYS B1
T1/A [74] -RJ45_LINKUP_SYS Green_LED-
C R7502 1 2 1/16W_330_5%_0402 0402 B2 C
SYS_MDI_1- 7 1:1 Green_LED+
[74] SYS_MDI_1- TD3+ T1/B
18 RJ45_TXD1- SINGA_2RJ3101-138211F
TX3+

SYS_MDI_1+ 8
[74] SYS_MDI_1+ TD3-
17 RJ45_TXD1+
TX3-
9 16 0303 1
TDCT3 T1/A TXCT3

1/2W_75_5%_0805

1/2W_75_5%_0805

1/2W_75_5%_0805

1/2W_75_5%_0805
C7501
0304 10 15 0302 1U_6.3V_K_X5R_0402
TDCT4 1:1 TXCT4 2
SYS_MDI_0- 11 T1/B
[74] SYS_MDI_0- TD4+ RJ45_TXD0-
14
TX4+

CL13 close to LAN Chip

1
SYS_MDI_0+ 12
[74] SYS_MDI_0+ TD4- RJ45_TXD0+
13
TX4-

R7503 2

R7504 2

R7505 2

R7506 2
T1/A

NA69LF

SP050008B00 C7502
7501 1 2 EMC@
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1000P_3KV_K_X7R_1808_H1.5
0.1U_25V_K_X7R_0402

D7501 RCLAMP0524PATCT_SLP2510P8-10-9 D7502 RCLAMP0524PATCT_SLP2510P8-10-9

B B
2 2 2 2 2
1 SYS_MDI_1- 9 1 SYS_MDI_1- SYS_MDI_3- 9 1 SYS_MDI_3-
SYS_MDI_1+ 8 2 SYS_MDI_1+ SYS_MDI_3+ 8 2 SYS_MDI_3+
SYS_MDI_0- 7 4 SYS_MDI_0- SYS_MDI_2- 7 4 SYS_MDI_2-
1 1 1 1 1
C7503

SYS_MDI_0+ 6 5 SYS_MDI_0+ SYS_MDI_2+ 6 5 SYS_MDI_2+

2
C7504

C7505

C7506

C7507

C7508

EMC_NS@ EMC@ EMC@ EMC@ EMC@

EMC@ EMC@
3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 LAN MAGNFTICS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 75 of 130

5 4 3 2 1
 5 4 3 2 1

RTS5232S_DV12 RTS5232S_AV12 OZ711LV2_cap

RTS5232S
VCC3B VCC3B_RTS5232S VCC3B_RTS5232S VCC3B_RTS5232S_AUX
40 mils
R7601 1 2 0_0603_SP VCC3B_RTS5232S R7602 1 2 0_0402_SP RTS5232S_DV12
20 mils RTS5232S_AV12
20 mils OZ711LV2_cap
20 mils

1 1 1 1 1 1

1 1 C7601 C7602 C7603 C7604 C7605 C7619

4.7U_6.3V_K_X5R_0603 0.1U_10V_K_X7R_0402 4.7U_6.3V_K_X5R_0603 0.1U_10V_K_X7R_0402 0.1U_10V_K_X7R_0402 2.2U_10V_K_X5R_0402
C7606 C7607 2 2 2 2 2 2
10U_6.3V_M_X5R_0402
2 2
0.1U_10V_K_X7R_0402
Close to pin 27 Close to pin 14 Close to pin 10 Close to pin 24
Close to pin 11
D D
For sequence tune.

VCC3B_RTS5232S_AUX

VCC3B_RTS5232S VCC3B_RTS5232S

teknisi-indonesia.com

1
R7603

2
1/16W_10K_5%_0402
R7604
1/20W_10K_5%_0201

2
U7601

1
VCC33_18 11 30 SD_MMC_CD R7606 1 2 0_0402_SP SD_MMC_CD_CONN
3V3_IN SD_CD# SD_MMC_CD_CONN [77]
C VCC33_18 18 31 C
DV33_18 MS_INS#
1
C7608 RTS5232S_AV12 10 32 RTS5232S_WAKE#
AV12 WAKE#
1U_10V_K_X5R_0402

R7605 1 2 0_0402_SP RTS5232S_DV12 14

2 DV12S
DV12 connects with AV12, due
to DV12 need a external input. 15 SD_MMC_D1 R7608 1 2 0_0201_SP SD_MMC_D1_CONN
SP1 SD_MMC_D1_CONN [77]

VCC3_MC VCC3_MC 12 16 SD_MMC_D0 R7609 1 2 0_0201_SP SD_MMC_D0_CONN

Card_3V3 SP2 SD_MMC_D0_CONN [77]
17 SD_MMC_CLK R7610 1 2 0_0201_SP SD_MMC_CLK_CONN
VCC3B_RTS5232S_AUX SP3 SD_MMC_CLK_CONN [77]
27
3V3aux 19 SD_MMC_CMD R7611 1 2 0_0201_SP SD_MMC_CMD_CONN
SP4 SD_MMC_CMD_CONN [77]
R7612 1 2 1/16W_6.2K_1%_0402 RTS5232S_RREF 9 20 SD_MMC_D3 R7613 1 2 0_0201_SP SD_MMC_D3_CONN
RREF SP5 SD_MMC_D3_CONN [77]
1. Close to R7604 21 SD_MMC_D2 R7614 1 2 0_0201_SP SD_MMC_D2_CONN
SP6 SD_MMC_D2_CONN [77]
2. 12mils, lengths < 200mils
C7609 1 2 0.1U_10V_K_X7R_0402 PCIE10_TXP_C 3 29 SD_MMC_WPI
[10] PCIE10_TXP HSIP SP7
C7610 1 2 0.1U_10V_K_X7R_0402 PCIE10_TXN_C 4
[10] PCIE10_TXN HSIN
C7611 1 2 0.1U_10V_K_X7R_0402 PCIE10_RXP_C 7
[10] PCIE10_RXP HSOP Close to U7601
[10] PCIE10_RXN
C7612 1 2 0.1U_10V_K_X7R_0402 PCIE10_RXN_C 8
HSON NC1
13 Part Number Vendor
22
NC2
SA000077K00 RTS5232S-GR REALTEK

2
PCIE10_CLK_100M 5 23
[12] PCIE10_CLK_100M REFCLKP NC3 R7615
[12] -PCIE10_CLK_100M
-PCIE10_CLK_100M 6
REFCLKN NC4
24 OZ711LV2_cap 0_0402_SP SA00009F600 OZ711LV2LN-A-0-TR
25

1
NC5
1 26
[13,37,51,64,66,73] -PLTRST_FAR PERST# NC6

B B
-CLKREQ_PCIE10 2
[12] -CLKREQ_PCIE10 CLK_REQ#
SD_MMC_D0_CONN C7613 1 2 5.6P_50V_D_NPO_0402
VCC3B_RTS5232S R7616 1 2 1/16W_10K_5%_0402 7601 28 33 EMC@
GPIO GND SD_MMC_D3_CONN C7614 1 2 5.6P_50V_D_NPO_0402
EMC@
RTS5232S-GR_QFN32_4X4 SD_MMC_D2_CONN C7615 1 2 5.6P_50V_D_NPO_0402
EMC@
SA000077K00
INSTALL_U7601_S SD_MMC_CMD_CONN C7616 1 2 5.6P_50V_D_NPO_0402
EMC@

SD_MMC_D1_CONN C7618 1 2 5.6P_50V_D_NPO_0402

EMC@

EMC, close to U7601

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 MEDIA CONTROLLER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 76 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3_MC VCC3_MC
VCC3_MC [76]

D D

2
F7701
1A_32V_ERBRD1R00X

1
40 mils VCC3_MC_CONN Mode Detect
Normal short
Card Insert open
1 1
C7701
C7702
10U_6.3V_M_X5R_0402
2 2
0.1U_10V_K_X7R_0402

C C

JREAD1
Close to JREAD1
SD_MMC_D2_CONN 1
[76] SD_MMC_D2_CONN MICRO SD_DAT2
SD_MMC_D3_CONN 2
[76] SD_MMC_D3_CONN MICRO SD_CD/DAT3
SD_MMC_CMD_CONN 3
[76] SD_MMC_CMD_CONN MICRO SD_CMD
4
SD_MMC_CLK_CONN 5 MICRO SD_VDDI
[76] SD_MMC_CLK_CONN MICRO SD_CLK
6
SD_MMC_D0_CONN 7 MICRO SD_VSS
[76] SD_MMC_D0_CONN MICRO SD_DAT0/RCLK+
SD_MMC_D1_CONN 8
[76] SD_MMC_D1_CONN MICRO SD_DAT1/RCLK-
SD_MMC_CD_CONN 9 10
[76] SD_MMC_CD_CONN MICRO SD_CD GND_1 11
GND_2 12
GND_3 13
GND_4

B B
T-SOL_158-2220902601
Close to JREAD1 ME@
1 1
EMC@ EMC@
C7703 C7704
2 2
1000P_50V_K_X7R_0402

6.8P_25V_C_NPO_0201

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 MEDIA CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 77 of 130

5 4 3 2 1
 5 4 3 2 1

VCC5B_CODEC
VCC3B_CODEC VCC1R8_SUS VCC5BA VCC1R8_SUS_CODEC
R7838 1 2 0_0603_SP R7839 1 2 0_0603_SP R7840 1 2 0_0603_SP R7841 1 2 0_0603_SP R7832 1 2 0_0603_SP

VCC3B VCC3B_CODEC

0.1U_10V_K_X5R_0402_MURATA

0.1U_10V_K_X5R_0402_MURATA

0.1U_10V_K_X5R_0402_MURATA

0.1U_10V_K_X5R_0402_MURATA

0.1U_10V_K_X5R_0402_MURATA
0.1U_6.3V_K_X5R_0201
1 1 1 1 1 1 1 1 1

C7801

C7802

C7803

C7804

C7805

C7806

C7807

C7808

C7809
100P_50V_J_NPO_0402

2.2U_6.3V_K_X5R_0402

100P_50V_J_NPO_0402

0.1U_6.3V_K_X5R_0201
1 1 R7802 1 2 0_0402_SP

C7810

C7811
2.2U_6.3V_K_X5R_0402
VCC5B VCC5B_CODEC
2 2 2 2 2 2 2 2 2

RF@

RF@
RF_NS@

RF_NS@
2 2
R7803 1 2 0_0402_SP

PVDD
VCC1R8_SUS VCC1R8_SUS_CODEC
AGND AGND AGND
D D
R7804 1 @ 2 1/16W_0_5%_0402

VCC3B_CODEC

VCC5B VCC5BA

1
DVDD-IO

AVDD1

AVDD2
R7812 R7817 1 2 0_0603_SP

DVDD
1/16W_47K_5%_0402

2
1 1 1 1

18

46

41

40

20
3
R7836 1 SW@ 2 1/20W_0_5%_0201 U7801 C7845 @C7834 C7836 C7837
[84] HP_L_JACK_U 10U_6.3V_M_X5R_04020.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 4.7U_6.3V_M_X5R_0402

DVDD

PVDD2

PVDD1

AVDD1
DVDD-IO

CPVDD/AVDD2
R7837 1 SW@ 2 1/20W_0_5%_0201 2 2 2 2
[84] HP_R_JACK_U @C7835
D7801 RB751V-40_SOD323-2
2 -SPK_MUTE_R 2 1
PDB -SPK_MUTE [85]
1 2
14 HDA_BCLK_R R7813 1 2 0_0201_SP HDA_BCLK
HP_L_JACK R7805 BCLK HDA_BCLK [9]
1 2 0_0201_SP R7806 1 2 1/20W_47_5%_0201HP_L_JACK_R 27
[84] HP_L_JACK HPOUT-L HDA_SYNC
15 0.01U_6.3V_K_X7R_0201
HP_R_JACK R7807 SYNC HDA_SYNC [9]
1 2 0_0201_SP R7808 1 2 1/20W_47_5%_0201HP_R_JACK_R 26
[84] HP_R_JACK HPOUT-R 47 AGND
MIC2_VREFO_L R7809 1 2 0_0201_SP MIC2_VREFO_L_codec
28 JD2
[81] MIC2_VREFO_L MIC2-VREFO-L SENSE_A
48
MIC2_VREFO_R MIC2_VREFO_R_codec JD1 SENSE_A [70]
R7810 1 2 0_0201_SP 29
[81] MIC2_VREFO_R MIC2-VREFO-R
1
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
4 1 TP7801 Test_Point_20MIL
MIC_RING2_CODEC 30 GPIO0/DMIC-DATA12
[81] MIC_RING2_CODEC MIC2-L/RING2 5 1 TP7802
MIC_SLEEVE_CODEC 31 GPIO1/DMIC-CLK Test_Point_20MIL
[81] MIC_SLEEVE_CODEC MIC2-R/SLEEVE 1
6
BEEP_MIX_ATT C7812 1 2 0.1U_6.3V_K_X5R_0201 BEEP_MIX_ATT_C 34 I2C-DATA @ C7846
[83] BEEP_MIX_ATT PCBEEP 7 0.1U_6.3V_K_X5R_0201
I2C-CLK 2
C VCC5BA C
8
R7811 1 2 1/20W_10K_5%_0201 33 NC1
5VSTB 9
NC2 For Audio Jack.
35
LINE2-R 10
36 NC3
LINE2-L 11
NC4
12
NC5

C7813 1 2 2.2U_6.3V_K_X5R_0402 CBP 23 45 SP_OUTR+

CBP SPK-OUT-R+ SP_OUTR+ [82]
CBN 24 44 SP_OUTR-
CBN SPK-OUT-R- SP_OUTR- [82]
43 SP_OUTL-
SPK-OUT-L- SP_OUTL- [82]
42 SP_OUTL+
MIC2_CAP SPK-OUT-L+ SP_OUTL+ [82]
32
MIC2-CAP 13
VREF 38 DC DET/EAPD
VREF
LDO3_CAP 19 16 HDA_SDIN0_R R7815 1 2 1/20W_33_5%_0201 HDA_SDIN0
LDO3-CAP SDATA-IN HDA_SDIN0 [9]
LDO2_CAP 21 17 HDA_SDO
LDO2-CAP SDATA-OUT HDA_SDO [9]
LDO1_CAP 39
LDO1-CAP 25 CPVEE
CPVEE

0.1U_10V_K_X5R_0402_MURATA
2.2U_6.3V_K_X5R_0402

2.2U_6.3V_K_X5R_0402

Thermal Pad
2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_10V_K_X5R_0402

2.2U_6.3V_K_X5R_0402

1 1/20W_10K_5%_0201
AVSS1

AVSS2

1000P_25V_K_X5R_0201

1000P_25V_K_X5R_0201

1000P_25V_K_X5R_0201

1000P_25V_K_X5R_0201
47P_25V_J_NPO_0402

47P_25V_J_NPO_0402

1U_6.3V_K_X5R_0402

220P_50V_K_X7R_0402

220P_50V_K_X7R_0402

220P_50V_K_X7R_0402

220P_50V_K_X7R_0402
ALC3287-CG_MQFN48_6X6
37

22

49

INSTALL_U7801_C
Analog Plane
B 1 1 1 1 1 B

2
2 2 2 2 2 1 1
C7814

C7815

C7818

1@ 1 1 1 1 1

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
C7816

C7817

@ @ 1 1 1 1
1
C7819
@ @

R7816 2
2 2

C7820

C7821
2 2 2 2 2 2

C7824

C7825

C7826

C7827

C7828

C7829
2 2 2 2

C7830

C7831

C7832

C7833
AGND AGND AGND AGND AGND

AGND

Vender suggest.
20180912
Delete C7820 for HDA CLK EA test result VCC1R8_SUS VCC1R8_SUS_CODEC

R7829 1 2 0_0402_SP

R7830 1 @ 2 1/16W_0_5%_0402 1
R7831 1 @ 2 1/16W_0_5%_0402 C7842
PLACE UNDER ALC3287 1U_6.3V_K_X5R_0201 U7802
2
1 6 1
EMC_NS@ C7838 1 2 0.01U_6.3V_K_X7R_0201 VIN VOUT

1
EMC@ C7839 0.1UC_25VC_KC_X5RC_0402 C7843

0.1U_6.3V_K_X5R_0201
1 2 2 5 R7833
EMC@ C7840 0.1UC_25VC_KC_X5RC_0402 GND QOD 2 @

1/16W_10_5%_0402
1 2
EMC@ C7841 0.1UC_25VC_KC_X5RC_0402 R7818 1 @ 2 1/20W_0_5%_0201 3 4
[52,72,86,106,125,127] B_ON

2
1 2 ON CT

1000P_25V_K_X7R_0201 C7844
AGND VCC3B R7819 1 2 0_0201_SP 1
TPS22918DBVR_SOT23-6

A AGND A
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CODEC-AL3287
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 78 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 AUDIO CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 79 of 130

5 4 3 2 1
 2 1

BLANK
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 AUDIO JACK SENSE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 80 of 130

2 1
 5 4 3 2 1

MIC2_VREFO_R
[78] MIC2_VREFO_R
R8103,8104,8105,8107
EVT FVT SIT SVT
Resistor V V
D R-short V D
1
C8110
1U_6.3V_K_X5R_0402

1
2
@
R12809
1/20W_2.2K_5%_0201
AGND
MIC2_VREFO_L
[78] MIC2_VREFO_L

2
MIC2_VREFO_R_R R8103 1 2 0_0201_SP

1
R12808
1/20W_2.2K_5%_0201
1

2
C8111
1U_6.3V_K_X5R_0402
2 MIC2_VREFO_L_R R8104 1 2 0_0201_SP
@
C C
AGND

MIC_SLEEVE R8105 1 2 0_0402_SP MIC_SLEEVE_CODEC

[70] MIC_SLEEVE MIC_SLEEVE_CODEC [78]

1
1
@ R8106
C8103
1000P_25V_K_X7R_0201
1/20W_0_5%_0201 2

2
AGND AGND

MIC_RING2 R81047 1 2 0_0402_SP MIC_RING2_CODEC

[70] MIC_RING2 MIC_RING2_CODEC [78]
1

B 1 B
@ R8108
C8104
1000P_25V_K_X7R_0201
1/20W_0_5%_0201 2 R8109 1 2 0_0201_SP
2

AGND AGND

AGND

1 2
NEAR EXT MIC CONN
EMC@ C8105
0.01U_6.3V_K_X7R_0201

A AGND A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 AUDIO EXT MIC I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 81 of 130

5 4 3 2 1
 5 4 3 2 1

D D

JSPK1 @
SP_OUTR+ EMC@ FL8201 1 2 BLM18PG221SN1D_2P SP_OUTR+_L 1
[78] SP_OUTR+ 1
SP_OUTR- EMC@ FL8202 1 2 BLM18PG221SN1D_2P SP_OUTR-_L 2
[78] SP_OUTR- 2
C SP_OUTL- EMC@ FL8203 1 2 BLM18PG221SN1D_2P SP_OUTL-_L 3 C
[78] SP_OUTL- 3
SP_OUTL+ EMC@ FL8204 1 2 BLM18PG221SN1D_2P SP_OUTL+_L 4
[78] SP_OUTL+ 4
5
6 GND1
GND2

HIGHS_WS33040-S0351-HF
1 1 1 1
C8201 C8202 C8203 C8204

220P_50V_K_X7R_0402

220P_50V_K_X7R_0402

220P_50V_K_X7R_0402

220P_50V_K_X7R_0402
2 2 2 2

B B

Close to SPEAKER CONN

www.teknisi-indonesia.com

A A
Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 AUDIO JACK SENSE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 82 of 130

5 4 3 2 1
 5 4 3 2 1

D
Audio Beep D

R8301 C8301
EC_SPKR 2 1 1 2
[85] EC_SPKR
1/16W_4.7K_5%_0402 0.1U_10V_K_X7R_0402

R8302 C8302
PCH_SPKR 2 1 1 2
[8] PCH_SPKR
C C
1/16W_4.7K_5%_0402 0.1U_10V_K_X7R_0402

1
R8303
@ 1/20W_10K_5%_0201
B B

2
BEEP_MIX_ATT
BEEP_MIX_ATT [78]

A A
Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 AUDIO BEEP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 83 of 130

5 4 3 2 1
 5 4 3 2 1

Audio Debug Function P.40

EC IT8227E
UART_EN

P.10
D D
PCH UART
UART2_TX SW@
UART2_RX
P.41
U4101 P.52
SW@ TS5USBA224RSWR
R4106
R4107 Audio Jack
P.50 P.51
Codec Head Phone/ R4105
USB/AUDIO SWITCH
HP_OUTR Line Out R4108
HP_OUTL

AUDIO@
R5124
R5125

C VCC3M C

VCC3M VCC3M VCC5M

AUDIO DEBUG PORT

1
R8409
@ 1/20W_10K_5%_0201

1
R8401 SW@ R8402

2
SW@ 1/20W_10K_5%_0201 1/20W_10K_5%_0201 R8405
SW@ 1/20W_0_5%_0201

2
UART_EN_R
U8401 SW@
HP_R_JACK_L R8403 1 SW@ 2 1/20W_0_5%_0201 HP_R_JACK_SW 9 1 UART_RX
[70] HP_R_JACK_L VBUS D- UART_RX [8,66]
7 10 UART_TX UART_TX [8,66]
HP_L_JACK_L R8404 1 SW@ 2 1/20W_0_5%_0201 HP_L_JACK_SW 6 D+/R D+ 5 VAUDIO
[70] HP_L_JACK_L D-/L VAUDIO
8 2
ASEL R HP_R_JACK_U [78]
4 3
GND L HP_L_JACK_U [78]
TS5USBA224RSWR_UQFN10_1P8X1P4
R8406 1 2 0_0201_SP SA00007RR00
[78] HP_R_JACK

1
R8407 1 2 0_0201_SP R8410
[78] HP_L_JACK
1/20W_10K_5%_0201

2
TABLE:
Mode Audio UART

B UART_EN L H B

TABLE:

Part Name For NPI For MP

U8401 SW@ ASM NA

R8403 SW@ ASM NA
R8404 SW@ ASM NA
R8401 SW@ ASM NA
R8402 SW@ ASM NA
R8405 SW@ ASM NA
R8506 AUDIO@ NA ASM
R8507 AUDIO@ NA ASM

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 AUDIO DEBUG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 84 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3SW_EC VCC3SW_AVCC
VCC1R8_SUS VCC3SW_EC

L8501 VCC3M
BLM18PG121SN1D_2P
1 2

1
1 1 R8538

1
1/20W_10K_1%_0201 R8539
C8501 C8502 C8503 1/20W_15K_1%_0201

1
R8502 R8503 1000P_50V_K_X7R_0402 0.1U_25V_K_X5R_0402 1 2
R8501 -HDD_DTCT [96]

2
2 2 10U_6.3V_M_X5R_0603_YAGEO
1 2 -ESPI_CS @ 1/16W_1K_5%_0402 @ 1/16W_1K_5%_0402 -TEMBER_DETECT

2
1/16W_20K_5%_0402 EC_AGND
R8541
resistor -LPC_ESPI_Strap0 -LPC_ESPI_Strap1 1/20W_33K_1%_0201
signal value 1 2 VCC3SW_EC
type VCC1R8_SUS
-SSD_DTCT [64]
D VCC3SW_EC VCC3SW D
ESPI_CLK pull-down 9K-50K ACIN_EC R8543 1 @ 2 1/16W_10K_5%_0402

1
15K-40K R8504 R8505
ESPI_IO[3:0] pull-up
1/16W_1K_5%_0402 1/16W_1K_5%_0402 R8544 1 @ 2 1/16W_0_5%_0402
ESPI_CS# pull-up 15K-40K R8542

1
1/16W_51K_+-1%_0402 @

2
NOTE: R8514 R8516 R8515 VCC3SW_EC 1 2 D8501 2 1 RB751V-40_SOD323-2
The eSPI interface should be implemented -KBD_BL_DTCT [88] ACIN [102]
weak pull-up/pull-down either as an integral 0_0402_SP 0_0402_SP 0_0603_SP
part of the eSPI master buff or on the board.
C8512 1 2 100P_50V_J_NPO_0402

2
NOTE:
eSPI or LPC interface is selected via strap pins
VCC3_LDO_PD
LPC_eSPI_Strap0# and LPC_eSPI_Strap1#. 1 1
C8504 C8505
VCC3SW R8545 1 2 1/16W_10K_5%_0402

0.1U_25V_K_X5R_0402
strap0 strap1 0.1U_25V_K_X5R_0402
Bus interface 2 2
pin9 pin123 Close pin75
R8506 1 2 1/16W_100K_5%_0402 -LID_CLOSE
0 0 eSPI MAFS

115
Close pin114

19
46
76
1 1 LPC UEC1A
VCC1R8_SUS

VCC
VCC
VCC
VCC
UMA@
R8551 1 2 1/20W_100K_5%_0201

44 VCORF C8511 1 2 2.2U_25V_K_X5R_0402

R8548 1 2 0_0201_SP -VIDEO_THERM_ALERT_EC VCORF
[40] -VIDEO_THERM_ALERT
VBKUP 114
75 VBKUP 69
ACIN_EC VSBY GPIO22/SDA1/N2TMS I2C_DATA_BT [101,102]
73 70
VCC3M -PSL_OUT PBL_IN1#&GPI70 GPIO17/SCL1/N2TCK I2C_DATA_PD_ECR8546 I2C_CLK_BT [101,102]
74 68 1 2 0_0201_SP
PSL_OUT#&GPIO71 GPIO74/SDA2/N2TMS I2C_CLK_PD_EC R8547 I2C_DATA_PD [59]
93 67 1 2 0_0201_SP
[51,62] -PWRSWITCH PSL_IN2#&GPIO6/EXT_PURST# GPO73/SCL2/N2TCK/SDP_VIS# I2C_CLK_PD [59]
17 120
[51] -LID_CLOSE GPIO42/SCL3B/PSL_IN3#&GPI42 GPIO31/SDA3A/N2TMS SMB03_DATA [91,92,93]
20 119 VCC3M
[88] -LED_FNLOCK GPIO43/SDA3B/PSL_IN4#&GPI43 GPIO23/SCL3A/N2TCK SMB03_CLK [91,92,93]
28
-AOU_IFLG GPO53/SDA4A/N2TMS/RSMRST#/XORTR# I2C_DATA_EC [40,53]
R8507 1 2 1/16W_100K_5%_0402 24
-LPC_ESPI_Strap0 GPIO47/SCL4A/N2TCK/DPWROK I2C_CLK_EC [40,53] I2C_CLK_EC
1 C8523 9 23 R81094 1 2 1/20W_4.7K_5%_0201
-EC_WAKE -LPC_ESPI_Strap1 GPIO65/SMI#/LPC_eSPI_Strap0# GPIO46/SDA4B AOU_SEL2 [69] I2C_DATA_EC
R8508 1 @ 2 1/16W_10K_5%_0402 10P_50V_J_NPO_0402 123 21 R81095 1 2 1/20W_4.7K_5%_0201
GPIO67/SOUT1/LPC_eSPI_Strap1# GPIO44/SCL4B AOU_SEL1 [69]
EMC_NS@ 108
-USB_ON1 GPIO05/SDA5 -CAM_FW_WR_EN [51]
R8509 1 2 1/16W_100K_5%_0402 Close to Pin 17. 107
2 GPIO97/SCL5 OTP_RESET [100]
VCCSPI 88
R8510 1 2 1/16W_10K_5%_0402 -HOTKEY 90 VCCSPI
[88] -LED_CAPSLOCK -LED_NUMBER F_CS0#/GPIOC6
92
C -EC_WLAN_WAKE [88] -LED_NUMBER -LED_MUTE F_SCK/GPIOC7 C
R8511 1 2 1/16W_10K_5%_0402 87 110
[88] -LED_MUTE -LED_MICMUTE F_SDIO&F_SDIO0/GPIOC5/KBSOUT15 GPIO82/VD_OUT1 CPUCORE_PWRGD [13]
86 104
FAN_ID [88] -LED_MICMUTE F_SDI&F_SDIO1/GPIOC4 GPIO80/VD_IN1 VCCIN_AUX_EN [110]
R8512 1 2 1/16W_10K_5%_0402 91 66
[70] -USB_ON1 GPIO81/F_WP#/F_SDIO2 GPO33/H_PWM/VD1_EN# -SPK_MUTE [78]
84
[3] VGA_BLON GPIO77/F_SDIO3

VeSPI 4 31
ESPICLK_60M VDD/VeSPI GPIO56/TA1 FAN_FRQ [90] VCC3SW_EC
2 117 R8552
[7] ESPICLK_60M -ESPI_CS LCLK/eSPI_CLK GPIO20/TA2 VCC3WLAN_DRV [128]
2 3 26 1/16W_10K_5%_0402
[7] -ESPI_CS ESPI_IO0 LFRAME#/GPIOF6/eSPI_CS# GPIO51/TA3 BACKLIGHT_ON [51]
126 63
[7] ESPI_IO0 ESPI_IO1 LAD0/eSPI_IO0/F_SDIO0 GPIO14/TB1 M_ON2 [104,116] -SPK_MUTE
EMC_NS@ C8506 127 64 1 @ 2
[7] ESPI_IO1 ESPI_IO2 LAD1/eSPI_IO1/F_SDIO1 GPIO01/TB2/KBSOUT4 -EC_WAKE [8]
100P_50V_J_NPO_0402 128 15
1 [7] ESPI_IO2 ESPI_IO3 LAD2/eSPI_IO2 GPIO36/TB3/CTS1# ACOFF [102]
1
[7] ESPI_IO3 -ESPI_RESET_EC LAD3/eSPI_IO3
R8518 1 2 0_0201_SP 125 R8553
[7] -ESPI_RESET VCCIN_AUX_PGD SERIRQ/GPIOF0/eSPI_RST#
6 1/16W_10K_5%_0402
[110] VCCIN_AUX_PGD -VIDEO_THERM_ALERT_EC GPIO24/eSPI_ALERT#
7 1 @ 2
8 LRESET#/GPIOF7/PLTRST# 32
For GPU [40] -VIDEO_POWER_LIMIT
[13,108] VGATE
R8520 1 2 0_0201_SP VGATE_R 124 GPIO11/CLKRUN#/eSPI_CS2#
GPIO10/LPCPD#
GPIO15/A_PWM/TRIST#/SPI_MISO
GPIO21/B_PWM
118
FAN_ON [90]
KBD_BL_PWM [88]
62 LED_AC_CON
GPIO13/C_PWM/SPI_MOSI
1.8V level 65 LED_AC_CHG
PROCHOT_EC 82 GPIO32/D_PWM 22
GPIO75/SPI_SCK GPIO45/E_PWM/DTR1#_BOUT1 -LED_PWR [51]
79 16
[8] TOP_SWAP_EN -PD_I2C_INT_EC GPIO02/SPI_MISO GPIO40/F_PWM/RI1# LED_LOGO [51]
R8521 1 2 0_0201_SP 83 81
[59] -PD_I2C_INT LCD_SELF_TEST_ON_R GPIO76/SPI_MOSI GPIO66/G_PWM/PSL_GPIO66 EC_SPKR [83]
R8522 1 2 0_0201_SP 77
[3,51] LCD_SELF_TEST_ON GPIO00/32KCLKIN VCC3SW_AVCC
VCC3B
VCC3SW_EC R8526 1 2 1/20W_4.7K_5%_0201 85 102
R8527 1 @ 2 1/20W_0_5%_0201 EXT_RST# AVCC 94
VCCIO_OUT GPIO07/AD0/VD_IN2 -HOTKEY [88]
VCCST_CPU R8528 1 2 0_0201_SP VTT 12 95
FAN_FRQ PECI_R VTT GPIO03/EXT_PURST#/AD1/SMI# -EC_WLAN_WAKE [66] VCC3M
R8523 1 2 1/16W_10K_5%_0402 R8529 1 2 1/16W_43_5%_0402 13 96
[6] PECI PECI GPIO04/AD2 -PWRSHUTDOWN [40,100,101,105]
97
SMB03_CLK GPIO90/AD3 ADP_I [102]
R8524 1 2 1/16W_2.2K_5%_0402 98 @
GPIO91/AD4/OVT# M_TEMP [101] M_ON2
25 99 R8554 1 2 1/16W_100K_5%_0402
SMB03_DATA [69] USB_ON2 GPIO50/PSCLK3 GPIO92/AD5 -TEMBER_DETECT FAN_ID [90]
R8525 1 2 1/16W_2.2K_5%_0402 27 100
[69] -AOU_IFLG GPIO52/PSDAT3 GPIO93/AD6 101
GPIO94/AD7 ME_FLASH [9]

AGND
GND
GND
GND
GND
GND
GND
1
VCC3SW_EC
NPCE68BPA0DX_LQFP128_16X16 C8513

5
18
45
78
89
116

103
EMC@ 0.1U_10V_K_X5R_0402_MURATA
R8530 1 2 1/16W_10K_5%_0402 I2C_CLK_BT 2

R8531 1 2 1/16W_10K_5%_0402 I2C_DATA_BT

EC_AGND
1
B B
C8508
0.1U_6.3V_K_X5R_0201
-PROCHOT 2 L8502
[6,59,102,108] -PROCHOT Need check
BLM18PG121SN1D_2P
1

D 1 2
PROCHOT_EC 2 Q8501
G L2N7002KWT1G_SOT323-3 1
2

SB000019400 LCD_SELF_TEST_ON
R8532 S C8507
3

1/20W_100K_5%_0201 47P_50V_J_NPO_0402
For debug
2

2
1
R8566 trace length needs to be equal
1

1/20W_10K_1%_0201 C8522
100P_25V_J_NPO_0201
2
1

1 ESPI_CLK_debug R8557 1 2 1/16W_33_5%_0402 ESPICLK_60M

@ TP8502 1 -ESPI_CS_debug R8558 1 2 1/16W_33_5%_0402 -ESPI_CS
@ TP8503 1 ESPI_IO0_debug R8559 1 2 1/16W_33_5%_0402 ESPI_IO0
AC_LED R8555
@
@
TP8504
TP8505
1
1
ESPI_IO1_debug
ESPI_IO2_debug
R8560
R8561
1
1
2
2
1/16W_33_5%_0402
1/16W_33_5%_0402
ESPI_IO1
ESPI_IO2
VCC3SW 1/10W_0_5%_0603 VCC3SW_EC @ TP8506 1 ESPI_IO3_debug R8562 1 2 1/16W_33_5%_0402 ESPI_IO3
1 @ 2 @ TP8507 1 -ESPI_RESET_debug R8563 1 2 1/16W_33_5%_0402 -ESPI_RESET
POWER ADAPTER Bi-COLOR(ORANGE/WHITE) @ TP8508

D
3 1

AO3413_SOT23-3
R8556
Q8502

G
2
VCC3M -PSL_OUT 1 2 VCC3SW_EC
20191123
1

Change BAT LED backlight test result 100 Ohm to 75 Ohm VCCSPI
R8534 1/20W_47K_5%_0201
1
@ 1/16W_300_5%_0402
C8514 1 1 1 1

1
R8533 LED1 0.1U_6.3V_K_X7R_0201 1 1
2

1 2 LED_AC_CHG_R A1 C 2 C8517 C8518 C8519 C8520 C8521

ORG C8515 C8516

2
2 2 2 2

0.1U_10V_K_X5R_0402_MURATA

0.1U_10V_K_X5R_0402_MURATA

0.1U_10V_K_X5R_0402_MURATA

0.1U_10V_K_X5R_0402_MURATA

10U_6.3V_M_X5R_0603_YAGEO
1/16W_75_5%_0402
2 2

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402
A2 Power Supply Control
6

D WHI
LED_AC_CHG 2 Q8503A @ VCC5M 1222A-S2ST3D-C30-2C-FTK_ORG_WHI
G L2N7002KDW1T1G_SOT363-6
1 SC50000GM00
1

C8509 S
1

A A
100P_50V_J_NPO_0402 R8565
EMC@ @ 1/16W_100K_5%_0402 R8537
2 @ 1/16W_300_5%_0402
R8535
2

1 2

1/16W_100_5%_0402
3

Q8503B D
LED_AC_CON 5 @ TABLE of (LED1)
G
Vendor LCFC P/N Description
1

1 L2N7002KDW1T1G_SOT363-6
C8510 R8536 S
LITE ON SC50000GM00 S LED LTW-327DSKF-5A 3X1 ORANGE/WHITE
4

100P_50V_J_NPO_0402 @ 1/16W_100K_5%_0402 Title

EMC@ Security Classification LC Future Center Secret Data
2 EVERLIGHT SC50000GD00 S LED 12-22A/S2ST3D-C30/2C(FTK) ORG/WHI
Issued Date 2015/01/12 Deciphered Date 2016/01/12 EC_NPCE68APA0DX
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 85 of 130

5 4 3 2 1
 5 4 3 2 1

VCC3M

R8601 1 2 1/16W_100K_5%_0402 AC_PRESENT

R8602 2 1 1/16W_10K_5%_0402 DRV2

R8603 2 1 1/16W_10K_5%_0402 DRV1

-PWRSW_EC 1 TP9807 @
R8616 2 1 1/16W_10K_5%_0402 -PWRSW_EC

D D

UEC1B

53 DRV0
KBSOUT0/GPOB0/SOUT_CR/JENK# 52 DRV1
KBSOUT1/GPIOB1/TCK 51 DRV2
R8608 1 2 0_0201_SP B_ON_R 10 KBSOUT2/GPIOB2/TMS 50 DRV3
[52,72,78,106,125,127] B_ON GPIO26/PSCLK2 KBSOUT3/GPIOB3/TDI
R8609 1 2 0_0201_SP A_ON_R 11 49 DRV4
[106,107] A_ON AC_PRESENT_R GPIO27/PBDAT2 KBSOUT4/GPOB4 DRV[17:0]
R8610 1 2 0_0201_SP 14 48 DRV5
[13] AC_PRESENT GPIO34/SIN1 KBSOUT5/GPIOB5/TDO DRV[17:0] [88]
29 47 DRV6
[126] VCC3LAN_DRV CPUCORE_ON_R ECSCI/GPIO54 KBSOUT6/GPIOB6/RDY#
R8611 1 2 0_0201_SP 30 43 DRV7
[13,108] CPUCORE_ON GPIO55/CLKOUT KBSOUT7/GPIOB7/KBRST#
R8604 DRV17 33 42 DRV8
1/16W_100K_5%_0402 DRV16 34 GPO57/KBSOUT17/DCD1#/TEST#/SPI_SCK KBSOUT8/GPIOC0 41 DRV9
1 2 B_ON R8612 1 2 0_0201_SP IPDDATA_R 71 GPIO60/KBSOUT16/DSR1# KBSOUT9/GPOC1 40 DRV10
[89] IPDDATA GPIO35/PSDAT1 KBSOUT10&P80_CLK/GPIOC2
R8613 1 2 0_0201_SP IPDCLK_R 72 39 DRV11
[89] IPDCLK GPIO37/PSCLK1 KBSOUT11&P80_DAT/GPIOC3
R8605 80 38 DRV12
[91] GSENSE_INT GPIO41/PSL_GPIO41 KBSOUT12/GPIO64
1/16W_100K_5%_0402 105 37 DRV13
A_ON [105] M_ON GPIO95 KBSOUT13/GP(I)O63
1 2 106 36 DRV14
[13] MPWRG GPIO96 KBSOUT14/GP(I)O62
109 35 DRV15
[13,64] -PWRSW_EC GPIO30/RTS1# KBSOUT15/GPIO61/XOR_OUT
R8614 1 2 1/16W_100_5%_0402 EC_TX_R 111
[66] EC_TX GPIO83/SOUT_CR
112
[13] BPWRG GPIO84/VD_OUT2
R8615 1 2 1/16W_100_5%_0402 EC_RX_R 113
[66] EC_RX GPIO87/SIN_CR
121
[13] -RSMRST_EC GPIO85 SENSE[7:0]
122 54 SENSE0
[13,56] -PCH_SLP_SUS GPIO86/KBRST# KBSIN0/GPIOA0/N2TCK/SIN2 SENSE[7:0] [88]
55 SENSE1
KBSIN1/GPIOA1/N2TMS/CTS2# 56 SENSE2
KBSIN2/GPIOA2/RI2# 57 SENSE3
KBSIN3/GPIOA3/DCD2# 58 SENSE4
KBSIN4/GPIOA4/DSR2# 59 SENSE5
KBSIN5/GPIOA5/SOUT2 60 SENSE6
KBSIN6/GPIOA6/RTS2# 61 SENSE7
VCC3SW_EC KBSIN7/GPIOA7/DTR2#_BOUT2
C C

M_ON R8606 1 @ 2 1/16W_100K_5%_0402 NPCE68BPA0DX_LQFP128_16X16

For Mirror Code

"H" --> Enable
"L" --> Disable (Default)

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 EC_NPCE68APA0DX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 86 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 EC_IT8227E-256/DX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 87 of 130

5 4 3 2 1
 5 4 3 2 1

Keyboard CONN
VCC3B VCC3M
VCC3B VCC3M

1
R8801 R8802 R8803 R8804
@ 1/16W_0_5%_0402 @ 1/16W_0_5%_0402 0_0603_SP @ 1/16W_0_5%_0402
D D

2
2 1/20W_15K_5%_0201

2 1/20W_15K_5%_0201

2 1/20W_15K_5%_0201

2 1/20W_15K_5%_0201

2 1/20W_15K_5%_0201

2 1/20W_15K_5%_0201

2 1/20W_15K_5%_0201

2 1/20W_15K_5%_0201
1
C8801
0.1U_6.3V_K_X5R_0201_MURATA
@ @ @ @ @ @ @ @ 2

R8805 1

R8806 1

R8807 1

R8808 1

R8809 1

R8810 1

R8811 1

R8812 1
JKBL1
40 42
39 40 GND2 41
-LED_NUMBER R8813 1 2 1/20W_100_5%_0201 -LED_NUMBER_R 38 39 GND1
[85] -LED_NUMBER 38
DRV17 37
DRV16 36 37
TP4MIDDLE 35 36
TP4RIGHT 34 35
TP4LEFT 33 34
32 33
-LED_CAPSLOCK R8814 1 2 1/20W_100_5%_0201 -LED_CAPSLOCK_R 31 32
[85] -LED_CAPSLOCK 31
30
-HOTKEY 29 30
[85] -HOTKEY -LED_MICMUTE -LED_MICMUTE_R 29
R8815 1 2 1/20W_100_5%_0201 28
[85] -LED_MICMUTE -LED_MUTE -LED_MUTE_R 28
R8816 1 2 1/20W_100_5%_0201 27
[85] -LED_MUTE -LED_FNLOCK -LED_FNLOCK_R 27
R8817 1 2 1/20W_100_5%_0201 26
[85] -LED_FNLOCK VCC3M_KBD 26
25
DRV11 24 25
[86] DRV[17:0] 24
DRV8 23
C
DRV10 22 23 C
DRV12 21 22
DRV9 20 21
DRV13 19 20
DRV15 18 19
DRV5 17 18
DRV7 16 17
DRV6 15 16
DRV3 14 15
[86] SENSE[7:0] 14
DRV1 13
SENSE5 12 13
DRV2 11 12
DRV4 10 11
SENSE0 9 10
SENSE2 8 9
DRV0 7 8
SENSE1 6 7
SENSE4 5 6
DRV14 4 5
SENSE6 3 4
SENSE7 2 3
SENSE3 1 2
1
100P_50V_J_NPO_0402

100P_50V_J_NPO_0402

100P_50V_J_NPO_0402

100P_50V_J_NPO_0402

100P_50V_J_NPO_0402

2
1 1 1 1 1 HIGHS_FC5AF401-3181H
EMC@ EMC@ EMC@ EMC@ EMC@ D8801 2 ME@
C8802 C8803 C8804 C8805 C8807 PESD5V0U2BT_SOT23-3 C8806
EMC@ 3300P_25V_K_X7R_0201
2 2 2 2 2
@ 1

1
PLACE NEAR JKBL2

B
Track Point B

VCC5B VCC3B
0.01U_6.3V_K_X7R_0201
1/10W_0_5%_0603

2 2
1

@ C8808
R8825

C8809
1

@ 0.01U_6.3V_K_X7R_0201
1 R8822 1
0_0402_SP
2

VCC_TP
2

VCC_TP

22U_6.3V_M_X5R_0603
VCC5B
2
1/20W_10K_5%_0201

C8813
1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
2

VCC_TP
1
R8818

R8819

R8823
R8820

@ 0_0402_SP
1

JTP1
VCC_TP 1
TP4DATA 2 1
[89] TP4DATA TP4_RESET 2
3
[8] TP4_RESET 3
TP4MIDDLE 4
TP4RIGHT 5 4
TP4LEFT 6 5
A
7 6 A
TP4CLK 8 7
[89] TP4CLK VCC5B_TP 8
9
KBD_BL_PWM 10 9
[85] KBD_BL_PWM -KBD_BL_DTCT 10
11 13
[85] -KBD_BL_DTCT 11 GND1
12 14
12 GND2
22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
1/20W_10K_5%_0201

HIGHS_FC1AF121-1151H
1

220P_25V_K_X7R_0201
1/16W_100K_5%_0402

ME@
2
R8824

2 2 2
C8810

C8811

C8812
R8821
2

1 1 1
Security Classification LC Future Center Secret Data Title
1

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CP/TPOINT/KB CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 88 of 130

5 4 3 2 1
 5 4 3 2 1

Click Pad

VCC3B VCC3B

C8901 R8901 R8902 R8903

D D
TP4CLK TP4DATA

1
4700P_6.3V_K_X7R_0201

1/20W_100K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
1
R8917 IPDCLK
0_0603_SP
2

2
IPDDATA

1
EMC@ EMC@
D8901 D8902

1
JCP1

PESD5V0H1BSF_SOD962-2

PESD5V0H1BSF_SOD962-2
12 14 D8906
SMB_CLK_3B 11 12 GND2 13 PESD5V0U2BT_SOT23-3
[33,35,93] SMB_CLK_3B 11 GND1
10 EMC@
TP4DATA 9 10
[88] TP4DATA 9

2
[88] TP4CLK TP4CLK 8

1
SMB_DATA_3B 7 8
[33,35,93] SMB_DATA_3B

2
VCC3B_PAD 6 7
R8923 1 2 0_0201_SP -LID_CLOSE_CP_CONN 5 6
[8] -LID_CLOSE_CP 5
IPDCLK 4
[86] IPDCLK 4
IPDDATA 3
[86] IPDDATA 3
2
PAD_DISABLE 1 2
[8] PAD_DISABLE 1
HIGHS_FC5AF121-2121H
ME@

C
FingerPrint Conn C

VCC3B

1
R8918
JFPR1
0_0603_SP
10
9 GND2

2
GND1
VCC3B_FP 8
USB2_P4_DN_CONN 7 8
USB2_P4_DP_CONN 6 7
5 6
4 5
3 4
3
1

1
EMC@ EMC@ 1 2
D8904 D8905 C8902 1 2
1

1
USB2_P4_DP R8904 1 2 0_0402_SP USB2_P4_DP_CONN 1
[10] USB2_P4_DP
PESD5V0H1BSF_SOD962-2 0.1U_10V_K_X5R_0402_MURATA

PESD5V0H1BSF_SOD962-2
2 ELCO_04-6811-608-000-846+
[10] USB2_P4_DN USB2_P4_DN R8905 1 2 0_0402_SP USB2_P4_DN_CONN ME@
2

www.teknisi-indonesia.com
2

B B

NFC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 TOUCH PAD/NFC/FPR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 89 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C
VCC5B

40mil JFAN1
1

7
R9001 6 GND2
GND1
0_0603_SP
5
[85] FAN_ON 5
4
2

3 4
[85] FAN_FRQ 3
VCC5B_FAN 2
1 2
[85] FAN_ID 1
HIGHS_WS33050-S0351-HF
ME@

B B

A A
Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12
FAN CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 90 of 130

5 4 3 2 1
 A B C D E

VCC3B VCC3B

1
2
R9102
R9101 0_0402_SP
@ 1/20W_10K_5%_0201
1 1

2
1
2 2
1
C9101 C9102
0.1U_6.3V_K_X5R_0201_MURATA 0.1U_6.3V_K_X5R_0201_MURATA C9103
1 1 10U_6.3V_M_X5R_0402
2

Close to pin 3 Close to pin 7

2 U9101 2

U9101
ADDR_SEL 1 12 I2C_CLK_GSENSE R9105 1 2 0_0201_SP
SDO/SA0 SCL/SPC SMB03_CLK [85,92,93]
R9106 1 2 0_0201_SP I2C_DATA_GSENSE 2 11
[85,92,93] SMB03_DATA SDA/SDI/SDO NC
3 10 GSENSE_CS R9103 1 2 0_0201_SP VCC3B
4 VDD_IO CS 9
GSENSE_INT 5 RES GND_2 8
[86] GSENSE_INT INT1 GND_1
1 INT2 6 7
INT2 VDD
TP9101 LIS2DWLTR_LGA12_2X2
Test_Point_20MIL SA00009AQ00
2

R9104
1/20W_10K_5%_0201
1

3 3

TABLE
TABLE of G-Sersor (U9101)
P/N ADDR_SEL Address
Vendor P/N LCFC P/N
ST LIS2DWLTR SA00009AQ00 H 32h (W) & 33h (R)
LIS2DWLTR
BOSCH BMA280 SA0000A1600 L 30h (W) & 31h (R)
H 0011001b(0x19)
BMA280
L 0011000b(0x18)
H 3Eh (W) & 3Fh (R)
KX022-1020
L 3Ch (W) & 3Dh (R)

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 APS G-SENSOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 91 of 130

A B C D E
 5 4 3 2 1

Thermal Sensor Close to DIMM

VCC3B U9201

D 1 10 SMB03_CLK D
VDD SMCLK SMB03_CLK [85,91,93]
REMOTE1+ 2 9 SMB03_DATA
DP1 SMDATA SMB03_DATA [85,91,93]
1
C9201 REMOTE1- 3 8
DN1 ALERT#
0.1U_10V_K_X5R_0402_MURATA REMOTE2+ 4 7 R9201 1 @ 2 1/16W_10K_5%_0402 VCC3B
2 DP2 THERM#
REMOTE2- 5 6
DN2 GND
1. Address 1001_101xb
F75303M_MSOP10 2. Internal pull up 1.2K to 1.5V
SA000046C0J R for init i al t her mal s hut do wn t e mp

TABLE of Thermal Sensor (U9201)

Vendor LCFC P/N Description
FINTEK SA000046C0J S IC F75303M MSOP 10P SENSOR
C C
Nuvoton SA000065D00 S IC NCT7719W MSOP 10P THERMAL SENSOR

Under the pipe Close to SSD

REMOTE1+ REMOTE2+ REMOTE1+ REMOTE2+

1 1 1 1

1
C9202 C9203 C9204 C C9205 C
@ 2 Q9201 @ 2 Q9202
2200P_50V_K_X7R_0402 2200P_50V_K_X7R_0402 100P_50V_J_NPO_0402 B MMBT3904WH_SOT323-3 100P_50V_J_NPO_0402 B MMBT3904WH_SOT323-3
2 2 2 E SB000008E1J 2 E SB000008E1J

3
REMOTE1- REMOTE2- REMOTE1- REMOTE2-

B B

Trace width/space:10/10 mil

Trace length:<8"
TABLE of Thermal Sensor (Q9201,Q9202)
Vendor LCFC P/N Description
PANJIT SB000008E1J S TR MMBT3904WH NPN SOT323-3
LRC SB00000ZJ00 S TR LMBT3904WT1G NPN SOT323-3
NXP SB00000YV00 S TR PMST3904 NPN SOT323-3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 THERMAL SENSOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 92 of 130

5 4 3 2 1
 5 4 3 2 1

SMBus
VCC3_SUS
DIMM1,DIMM2,CP
D VCC3B VCC3B D

1
R9303 R9304
R9301 R9302 1/16W_4.7K_5%_0402 1/16W_4.7K_5%_0402
1/20W_10K_5%_0201 1/20W_10K_5%_0201

2
2
G
@ @

SMB_CLK 6 1 SMB_CLK_3B

S
[7] SMB_CLK SMB_CLK_3B [33,35,89]

D
@ Q9301A
L2N7002KDW1T1G_SOT363-6
SB000013A00
R9305 1 2 0_0201_SP

5
G
C C

SMB_DATA 3 4 SMB_DATA_3B

S
[7] SMB_DATA SMB_DATA_3B [33,35,89]

D
@ Q9301B
L2N7002KDW1T1G_SOT363-6
SB000013A00
R9306 1 2 0_0201_SP

GPU, Thermal Sendor,

Embedded Controller, G sensor
VCC3B

B B
2
G

SML1_CLK 6 1 SMB03_CLK
S

[7,59] SML1_CLK SMB03_CLK [85,91,92]

D

Q9302A
@ L2N7002KDW1T1G_SOT363-6
SB000013A00 2N7002KDWH
Vth= min 1V, max 2.5V
R9307 1 @ 21/16W_0_5%_0402 ESD 2KV
TABLE of U9301/U9302/U9303/U9304
5
G

Vendor P/N LCFC P/N

SML1_DATA 3 4 SMB03_DATA TI SN74LVC1G66DCK SA00005BE0J
S

[7,59] SML1_DATA SMB03_DATA [85,91,92]

D

Q9302B
NXP 74LVC1G66GW SA00007KS00
@ L2N7002KDW1T1G_SOT363-6
SB000013A00
ONSemi MC74VHC1G66DFT2G SA00008JQ00
A R9308 1 @ 21/16W_0_5%_0402 A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 SMBUS SWITCH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 93 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 THINK ENGINE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 94 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 THINK ENGINE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 95 of 130

5 4 3 2 1
 5 4 3 2 1

D D

SATA HDD CONN.

VCC5B_HDD_Conn

1 1 1 1
@ C9601 C9602 C9603 C9604

0.1U_10V_K_X5R_0402_MURATA
10U_10V_K_X5R_0805_H1.25

10U_10V_K_X5R_0805_H1.25

1U_10V_K_X5R_0402
2 2 2 2

C C

VCC5B_HDD VCC5B

1
R9603 R9601
0_0805_SP @ 1/8W_0_5%_0805

2
VCC5B_HDD_Conn
JHDD1 ME@

14 16
PCIE11_L0_SATA0_TXP_CONN 13 14 GND16 15
[97] PCIE11_L0_SATA0_TXP_CONN PCIE11_L0_SATA0_TXN_CONN 13 GND15
12
[97] PCIE11_L0_SATA0_TXN_CONN 12
11
PCIE11_L0_SATA0_RXN_CONN 10 11
[97] PCIE11_L0_SATA0_RXN_CONN 10
PCIE11_L0_SATA0_RXP_CONN 9
[97] PCIE11_L0_SATA0_RXP_CONN 9
8
HD_SSD_DEVSLP R9602 1 2 0_0402_SP HD_SSD_DEVSLP_CONN 7 8
[10] HD_SSD_DEVSLP -HDD_DTCT 7
6
[85] -HDD_DTCT 6
5
4 5
3 4
2 3
1 2
1

HIGHS_FC5AF141-3181H
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 SATA HDD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 96 of 130

5 4 3 2 1
 5 4 3 2 1

PCIE11_L0_SATA0_TXP NSATA_RE@ R9701 1 2 1/20W_0_5%_0201 PCIE11_L0_SATA0_TXP_R NSATA_RE@ C9701 1 2 0.01U_6.3V_K_X7R_0201_MURATA PCIE11_L0_SATA0_TXP_CONN

PCIE11_L0_SATA0_TXN NSATA_RE@ R9702 1 2 1/20W_0_5%_0201 PCIE11_L0_SATA0_TXN_R NSATA_RE@ C9702 1 2 0.01U_6.3V_K_X7R_0201_MURATA PCIE11_L0_SATA0_TXN_CONN

PCIE11_L0_SATA0_RXP NSATA_RE@ R9703 1 2 1/20W_0_5%_0201 PCIE11_L0_SATA0_RXP_R NSATA_RE@ C9703 1 2 0.01U_6.3V_K_X7R_0201_MURATA PCIE11_L0_SATA0_RXP_CONN

PCIE11_L0_SATA0_RXN NSATA_RE@ R9704 1 2 1/20W_0_5%_0201 PCIE11_L0_SATA0_RXN_R NSATA_RE@ C9704 1 2 0.01U_6.3V_K_X7R_0201_MURATA PCIE11_L0_SATA0_RXN_CONN

D D

VCC3B VCC3B_HDD

SATA REDRIVER

1
R9720 R9721
1/10W_0_5%_0603 0_0603_SP
@
VCC3B VCC3B_HDD

2
U9701
7 10
EN VDD1 20
VDD2
1

PCIE11_L0_SATA0_TXP SATA_RE@C9705 1 2 0.01U_6.3V_K_X7R_0201_MURATA PCIE11_L0_SATA0_TXP_C 1

[10] PCIE11_L0_SATA0_TXP PCIE11_L0_SATA0_TXN SATA_RE@C9706 AI+
R9705 1 2 0.01U_6.3V_K_X7R_0201_MURATA PCIE11_L0_SATA0_TXN_C 2 6
[10] PCIE11_L0_SATA0_TXN AI- NC1
@ 16
NC2
1/16W_100K_5%_0402

PCIE11_L0_SATA0_RXP SATA_RE@C9707 1 2 0.01U_6.3V_K_X7R_0201_MURATA PCIE11_L0_SATA0_RXP_C 5

[10] PCIE11_L0_SATA0_RXP BO+
PCIE11_L0_SATA0_RXN SATA_RE@C9708 1 2 0.01U_6.3V_K_X7R_0201_MURATA PCIE11_L0_SATA0_RXN_C 4 9 A_EM
[10] PCIE11_L0_SATA0_RXN
2

BO- A_EM

1
8 B_EM
3 B_EM R9708 @ R9709
TDet_B#

1/20W_0_5%_0201

1/16W_0_5%_0402
13 15 PCIE11_L0_SATA0_TXP_CONN_C SATA_RE@C9709 1 2 0.01U_6.3V_K_X7R_0201_MURATA @
TDet_A# AO+ PCIE11_L0_SATA0_TXP_CONN [96]
14 PCIE11_L0_SATA0_TXN_CONN_C SATA_RE@C9710 1 2 0.01U_6.3V_K_X7R_0201_MURATA
TDetT_EN 18 AO- PCIE11_L0_SATA0_TXN_CONN [96]

2
TDetT_EN

1
A_EQ 17 11 PCIE11_L0_SATA0_RXP_CONN_C SATA_RE@C9711 1 2 0.01U_6.3V_K_X7R_0201_MURATA
A_EQ BI+ PCIE11_L0_SATA0_RXP_CONN [96]

1
R9706 B_EQ 19 12 PCIE11_L0_SATA0_RXN_CONN_C SATA_RE@C9712 1 2 0.01U_6.3V_K_X7R_0201_MURATA
B_EQ BI- PCIE11_L0_SATA0_RXN_CONN [96]

1/16W_0_5%_0402
@ @ R9707 21
PAD

1/16W_0_5%_0402
SATA_RE@ PI3EQX6741STZDEX_TQFN20_4X4
2

INSTALL_U9701_S

2
C C

VCC3B
1

1
R9710 R9711 R9712 R9713 R9714
1/16W_0_5%_0402

1/20W_0_5%_0201

1/16W_0_5%_0402

1/16W_0_5%_0402

1/16W_0_5%_0402
@ @ @ @ @
2

2
VCC3B

TDetT_EN A_EQ B_EQ A_EM B_EM

20180911
Remove R9719 for SATA SI result
1 1 1
SATA_RE@ SATA_RE@ SATA_RE@
C9713 C9714 C9715
1

B B
.01U_50V_K_X7R_0402

.01U_50V_K_X7R_0402

1U_6.3V_K_X5R_0402

SATA_RE@ SATA_RE@ SATA_RE@ SATA_RE@

2 2 2 R9715 R9716 R9717 R9718 R9719
1/16W_1K_5%_0402

1/16W_1K_5%_0402

1/16W_1K_5%_0402

1/16W_1K_5%_0402

1/16W_1K_5%_0402

@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 SATA RE-DRIVER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 97 of 130

5 4 3 2 1
 5 4 3 2 1

NOTE:
Check timing sequence in SDV phase.
VCC3B VCC3_SUS_TPM
5 ms < t
NOTE:
1) It is recommended to connect the TPM to the system's
standby voltage to improve performance.
R9801 1 @ 2 1/16W_0_5%_0402 2) SPI_RST# must be asserted for at least 5 msec after
0 < t VSB power-up.
VSB 3) VSB may come up anytime before VDD power-up,
VCC3_SUS but not after VDD power-up.
D 4) SPI_RST# may be asserted together with VDD power D
VDD negation, but should not at any point exceed 0.5V
above the VDD power level.
R9802 1 2 0_0402_SP 1 ms < t

SPI_RST#

VCC3_SUS_TPM

VCC3_SUS_TPM

2 2 2 2 2 2
TPM@ TPM@ TPM@ TPM@ @ @
C9801 C9802 C9803 C9804 C9805 C9806

2
@ 0.1U_6.3V_K_X5R_0201_MURATA 0.1U_6.3V_K_X5R_0201_MURATA 0.1U_6.3V_K_X5R_0201_MURATA 10U_6.3V_M_X5R_0402 0.1U_6.3V_K_X5R_0201_MURATA 10U_6.3V_M_X5R_0402
R9803 1 1 1 1 1 1
1/20W_10K_5%_0201

1
Close to Pin1, Pin8, Pin22

TABLE

Pin ST Micro Nuvoton

22
U9801 No

1
C ST33HTPH2X32AHD4 NPCT750LABYX C

VHIO2

VHIO1

VSB
-TPM_IRQ R9804 1 2 0_0201_SP -TPM_IRQ_R 18 2 1 NiC VSB
[8] -TPM_IRQ PIRQ#/GPIO2 NC1 3
NC2 4 1 TP9801 PAD @ 2 GND NC
SPI_MOSI_IO0 R9805 1 @ 2 1/20W_33_5%_0201 SPI_MOSI_IO0_2_R 21 PP/GPIO6 5 3 NiC NC
[7,21] SPI_MOSI_IO0 MOSI/GPIO7 NC3
SPI_MISO_IO1 R9806 1 @ 2 1/20W_33_5%_0201 SPI_MISO_IO1_2_R 24 9 4 NiC GPIO/PP
[7,21] SPI_MISO_IO1 MISO NC5 10
NC6 11
5 NiC NC
NC7 12 6 GPIO_LP GPIO3
NC8
[7] -SPI_CS2
-SPI_CS2 R9807 1 2 0_0201_SP -SPI_CS2_R 20
SCS#/GPIO5 GPIO4
13 1 TP9802 PAD @ 7 GPIO_PP NC
14 VHIO
SPI_CLK R9808 1 @ 2 1/20W_33_5%_0201 SPI_CLK_2_R 19 NC9 15
8 NiC
[7,21] SPI_CLK SCLK NC10
NPCT750LADYX_QFN32_5X5 16
-PLTRST_NEAR 17 GND1 25
[13] -PLTRST_NEAR PLTRST# NC11 26
1 6 NC12 27
GPIO3 NC13 9 NiC NC
@ TP9805 28
1 7 NC14 31 10 NiC NC
@ TP9806 NC4 NC15 32 11 NiC NC
vPro TABLE (VPRO@) NC16
12 NC
29 1 TP9803 PAD @
NiC
LCFC P/N SD00000LHYT SDA/GPIo0 30 1 TP9804 PAD @
13 NiC GPIO4
SCL/GPIO1 14 NiC NC

GND2

GND3
Description 1/20W_33_5%_0201 15 NC
NiC
Location R9805,R9806,R9807 16 NiC GND
SA00008KS30

23

33
INSTALL_U9801_S
In SIT phase change.
Non-vPro TABLE (NVPRO@) So only change PN, symbol not correct.
17 SPI_RST# RST#
LCFC P/N SD00000LIYT 2019/12/2 Nick
18 SPI_PIRQ# PIRQ#/GPIO2
Description 1/20W_56_5%_0201 19 SPI_CLK SCLK
20 SPI_CS# SCS#/GPIO5
Location R9805,R9806,R9807 21 MOSI MOSI/GPIO7
B 22 VPS VHIO B

23 NiC GND
24 MISO MISO

TABLE of TPM (U9801) 25 NiC NC

26 NiC NC
Vendor LCFC P/N Description 27 NiC NC
NUVOTON SA00008KS30 S IC NPCT750LADYX QFN 32P TPM 2.0 28 NiC NC
29 NiC SDA/GPIO1
ST SA0000AB720 S IC ST33HTPH2X32AHD8 VQFN 32P TPM 2.0 30 NiC SDA/GPIO0
31 NiC NC
32 NiC NC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DISCRETE TPM 2.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 98 of 130

5 4 3 2 1
 5 4 3 2 1

For ME GND hole Screw Hole

D D

H21 H15 H17 H5 HICT3

PAD_C5P0D2P2 PAD_C5P5D2P2 PAD_C5P5D2P2 PAD_C5P5D2P2 HICT1 HICT2 PAD_C2P5D2P5N
PAD_C2P5D2P5N PAD_C2P5D2P5N

@ @ @ @ @

1
@ @

1
H12 H16 H6 H10 H11 H18 H23
PAD_C7P0D3P3 PAD_C6P0D2P2 PAD_C7P0D3P3 PAD_C6P0D3P3 PAD_C6P0D3P3 PAD_C6P0D3P3 PAD_C6P0D3P3

@ @ @ @ @ @ @
1

1
H7 H8 H9 H4 H19 H20
PAD_C6P0D3P3 PAD_C6P0D3P3 PAD_C6P0D3P3 PAD_C7P0D3P3 PAD_C6P0D4P2 PAD_C8P0D2P2

@ @ @ @ @ @
1

1
H1 H2 H3 H13 H14
PAD_C8P0D2P3 PAD_C8P0D2P3 PAD_C8P0D2P3 PAD_C8P0D5P5 PAD_C8P0D5P5

C @ @ @ @ @ C
1

H31 H33
H28 H30 H29 pad_o2p3x1p6d1p7x1p0 pad_o2p3x1p6d1p7x1p0
PAD_C6P0D2P2 PAD_O2P3X2P8D2P3X2P8 PAD_O2P3X2P8D2P3X2P8

@ @
1

@ @ @ 1
1

H32
pad_r1p3x2p3d0p7x1p7

@
1

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 SCREW HOLE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 99 of 130

5 4 3 2 1
 5 4 3 2 1

VINT20_IN VINT20_IN [59,60,102]

VSYS15 VSYS15 [51,102,103,104,105,106,108,109,110,117,118]

VCC3SW VCC3SW [20,51,85,101,102,105,126,127]

RTCVCC RTCVCC [13,16,20]

D D

PD0002
1SS355VMTE-17

PD0003 1 2
PR0002 1SS355VMTE-17 PR0003 PR0001 VINT20_IN
0_0402_SP 1/16W_100K_1%_0402
1/16W_10K_1%_0402
1 2 2 1 1 2 1 2 1 2
[40,85,101,105] -PWRSHUTDOWN VSYS15
PD0004
1SS355VMTE-17

2
3
PQ0002
E
2
B PR0004
PMBT3906 1/16W_750K_5%_0402

1
C
VCORE1 VCORE2 VCCIN_AUX

1
540_0402NEW_30%_PRF15BB541NB6RC 540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC

1
C PT0002 PT0003 PT0004
PQ0003 2 2 1 2 1 2 1
C PMBT3904 B C
PQ0001
E 2 2N7002KW_SOT323-3
3

1
D
PC0001 2 OTP_RESET [85]
1U_25V_K_X7R_0603_YAGEO G
1 DIS@
S

3
2 1 2 1

PT0007 PT0008
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
Charger VCCGFXCORE_D
2 1

PR0005
1/16W_0_5%_0402
UMA@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 VIN Detector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632 0.3

Date: Tuesday, October 13, 2020 Sheet 100 of 128

5 4 3 2 1
 5 4 3 2 1

VCC3SW

1
D D
PR0101
1/16W_1M_5%_0402
EMC@
PL0102
BLM18KG300TN1D_2P
PRT7 under CPU bottom side for CPU thermal protection.

2
ME@ VMB2 VMB 1 2
JDC1 PF0101 This is for thermal team request.
HIGHS_WS33081-S0201-HF 12A_32V_0501012.WRS EMC@
PL0101
1 2 1 BLM18KG300TN1D_2P
1 2 BAT_PWR15
9
PTH1 2 3 I2C_CLK_BT_R 1 2
10 3 4 I2C_DATA_BT_R PR0105
@
teknisi-indonesia.com
PTH2 4 5 PR0106 1/16W_100_1%_0402 1/16W_0_5%_0402
5 6 EMC@ EMC@

2
11 1 2 1 2
PTH3 6 7 I2C_CLK_BT [85,102]
PC0102 PC0101 VCC3B
12 7 8 PR0102 1/16W_100_1%_0402 1000P_50V_K_X7R_0402 0.01U_25V_K_X7R_0402 PR0108

1
PTH4 8 1 2 0_0402_SP
I2C_DATA_BT [85,102]
1 2
C PR0109 1/16W_10K_1%_0402
A/D +VL_3.3V C

2
1 2
M_TEMP [85]
PR0104

1
BATT_OUT [102] 1/16W_16.5K_1%_0402
PC0103
0.1U_16V_K_X7R_0603_YAGEO PU0101

1
1 8 NTC_V_1
VCC TMSNS1

EMC_NS@
PESD5V0U2BT_SOT23-3
PR0107 2 7 OTP_N_002 2 1
0_0402_SP GND RHYST1
[40,85,100,105] -PWRSHUTDOWN 1 2 OTP_N_003 3 6 PR0103
OT1 TMSNS2 1/16W_6.49K_1%_0402

1
PD0101
4 5
1 OT2 RHYST2 PT0101
G718TM1U_SOT23-8
100K_0402_1%_NCP15WF104F03RC

2
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 BATTERY INPUT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632
2.0

Date: Tuesday, October 13, 2020 Sheet 101 of 128

5 4 3 2 1
 5 4 3 2 1

VINT20_IN VINT20_IN [59,60,100]

VSYS15 VSYS15 [51,100,103,104,105,106,108,109,110,117,118]

BAT_PWR15 BAT_PWR15 [101]

PJ0201
2 1
2 1
@ JUMP_43X79
D D

VINT20_IN
EMC@ VSYS15

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
PL0201 EMC@

1
PC0243

PC0238

PC0212

PC0229

PC0228

PC0233

EMC@ PC0227

EMC@ PC0216
1UH_PCMB053T-1R0MS_7A_20% PR0201 PQ0204 PR0204 PL0202
1W_0.01_+-1%_1206_100PPM/C AONY36324 1/16W_56_5%_0402 2.2UH_CMLE063T-2R2MS_10A_20% PQ0205
1 2 VINT20 1 2 VBUS 1 2 AONH36334

2
7

9
10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR
2 2

1
1000P_50V_K_X7R_0201

330P_50V_K_X7R_0402
0.01U_25V_K_X7R_0201
33U_D2_25VM_R40M
10U_25V_K_X5R_0805_H1.25_MUR
PR0202 PC0213 PC0220

2
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

PC0201
1 1/20W_4.99_1%_0201 PR0205 5 0.047U_25V_K_X7R_0402_MURATA
0.047U_25V_K_X7R_0402_MURATA EMC@ 7 10

1
EMC_NS@

EMC_NS@

1/20W_4.99_1%_0201 2 4 PR0203 6 4
PC0232

PC0210
1

1 1 1
EMC@
+

PC0211

PC0235

PC0239

PC0244

PC0236

PC0231
@ PC0224 3 1/16W_56_5%_0402 5 3

2
EMC@

EMC@
PC0206

PC0202

PC0205
0.1U_25V_K_X7R_0402_MURATA PR0207 2

1 2

12
2 1 1/10W_2.2_5%_0603 PR0206 EMC@
2

2 1/10W_2.2_5%_0603 PC0240
@ 2 330P_50V_K_X7R_0402 PQ0201

2
0_0201_SP
2 30 25 AONR21357_DFN8

1
BTST1 BTST2

1
0_0201_SP
1 8

PR0208

PR0209
PC0208 PC0241 LX1_CHG 32 23 LX2_CHG 2 7 PR0210
0.033U_25V_K_X7R_0402 1 0.033U_25V_K_X7R_0402 SW1 SW2 3 6 1W_0.01_+-1%_1206_100PPM/C

1
1 DL1_CHG 29 26 DL2_CHG 5 1 2
LODRV1 LODRV2 BAT_PWR15

0.1U_25V_K_X7R_0402_MURATA

0.1U_25V_K_X7R_0402_MURATA
DH1_CHG DH2_CHG

10U_25V_K_X5R_0805_H1.25_MUR
PC0225 31 24 1 PC0219 1

4
HIDRV1 HIDRV2

1
1U_25V_K_X5R_0402

1U_25V_K_X5R_0402

PC0218
0.47U_25V_K_X5R_0603 1 2

PC0242

PC0230
1 22
VBUS VSYS

1
PC0214

PC0215
0.1U_25V_K_X7R_0402_MURATA

2
C 2 21 BATDRV# 2 2 C
ACN BATDRV#

2
3 20
ACP SRP
1 2 VDDA 7 PU0201 19
BQ25700_VDD VDDA SRN PR0212 1
1/10W_10_5%_0603 2
BQ25700ARSNR_QFN32_4X4 BQ25700_VDD

1
PR0211 6 28 1 2 PR0213 1
1/10W_10_5%_0603 2
1/16W_10_1%_0402 PR0214 PR0215 1/20W_40.2K_1%_0201 ILIM_HIZ REGN PC0234 2.2U_10V_K_X5R_0402
1/20W_255K_1%_0201 1 2 1 2 PC0209680P_25V_K_X7R_0201_MURATA
1 PC0223 1800P_25V_K_X7R_0201 16 17 1 2 PR0216 1 2
1 2 PC0217 COMP1 COMP2 1/20W_10K_1%_0201

2
PC0207 33P_25V_J_NPO_0201 1 2
1U_25V_K_X5R_0402 -PROCHOT_P 1 2 11 18 PC0237 15P_25V_J_NPO_0201
PROCHOT# CELL_BATPRES

1
2 PR0217 0_0201_SP

1/20W_220K_5%_0201
1 2 13
PD0203 [85,101] I2C_CLK_BT SCL

PR0219
PR0218 0_0402_SP 8 1 2 ADP_I [85]
2 1 -PROCHOT_P 1 2 12 IADPT
[6,59,85,108] -PROCHOT [85,101] I2C_DATA_BT SDA
PR0220 0_0402_SP 9 1 2 @ PR0221

2
1 2 4 IBAT PR0222 0_0201_SP 1/16W_0_5%_0402
1SS355VMTE-17 [85] ACIN CHRG_OK
PR0223 0_0402_SP 10 1 2
PD0202
1 2 5 PSYS PR0224 0_0201_SP
PSYS [108] VDDA
PR0225 0_0201_SP ENZ_OTG 27
PGND

100P_50V_K_X7R_0201

100P_50V_K_X7R_0201

100P_50V_K_X7R_0201
[40] GPU_GPIO12 2 1 15
CMPOUT

1
PR0226 33
PAD

1
PR0227 1/20W_100K_1%_0201 14 PR0228
1SS355VMTE-17 CMPIN VCC3M

PC0222

PC0221

PC0203
0_0402_SP PQ0203 D 1/16W_137K_1%_0402 PR0229
1 2 2 @ PR0230 1/20W_82K_1%_0201

1
[85] ACOFF G 1/20W_0_5%_0201

1
ADP_I 1 2

2
2
B S 2N7002KW_SOT323-3 B
PR0232

3
1/20W_300K_1%_0201
PR0231 VINT20_IN

1
1/20W_10K_1%_0201
PD0201

1
PQ0202 D PR0234

2
1 2 2 1/20W_100K_1%_0201
@ PR0233 [101] BATT_OUT G
1/20W_100K_1%_0201
VCC3M VCC3SW

2
1SS355VMTE-17

1
S 2N7002KW_SOT323-3

3
PR0235

1
0.1U_25V_K_X7R_0402_MURATA
1/20W_1M_5%_0201

1/20W_10K_1%_0201
2

2
PR0237

2
1
@PC0226
@ PR0236 PR0239
1/20W_10K_1%_0201 0_0201_SP
@ PR0238 @

2
1/20W_0_5%_0201

1
@ POUT1 PAD 1 1 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 BATTERY CHARGER(BQ25700A)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632
2.0

Date: Tuesday, October 13, 2020 Sheet 102 of 128

5 4 3 2 1
 5 4 3 2 1

VSYS15 VSYS15 [51,100,102,104,105,106,108,109,110,117,118]

VCC5M VCC5M [51,69,70,72,84,85,107,108,109,110,116,117,118,119,120,125,126,127]

D D

VCC5M
VCC3M FSW=750 KHz
TDC:8A

1
10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR
@ PR0302
1/16W_100K_5%_0402
OCP:12A
VSYS15 @
PJ0301 PR0310 PC0306

2
2 1 +5V_VIN 1/10W_10_5%_0603 0.1U_25V_M_X7R_0603
2 1

2200P_25V_K_X7R_0402
47P_50V_J_NPO_0402
+5V_PWRGD +5VBS 1 2 1 2

0.1U_25V_K_X5R_0402
1

1
RF_NS@ PC0310

EMC@ PC0313

EMC@ PC0301

PC0308

PC0309
JUMP_43X79 PU0301
VCC5M

1
PL0301
8A

PGOOD

BOOT
2

2
2 1UH_PCMC063T-1R0MN_11A_20% PJ0302

10P_50V_J_NPO_0402
5 2 +5VLX 1 2 +5VALW_P 2 1
VIN LX1 2 1
C C

2
3 EMC_NS@ @ JUMP_43X118
LX2

2200P_25V_K_X7R_0402
PR0308
3V5V_ON

0.1U_25V_K_X5R_0402
22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25
1/10W_4.7_5%_0603 1

PC0312
LV6228CGQUF_UQFN12_3X3 PR0305 1 1

1
PC0318

PC0314

PC0304

PC0303

EMC@ PC0311

EMC@ PC0302
3V5V_ON 6 10 +5VOUT 0_0402_SP

1
EN VOUT
2

0.1U_25V_K_X5R_0402
PR0306 @

2
1

2
2 2

PC0316
12 0_0402_SP
VCC5M CLK 11
100mA 2 1
LDO

1
1/16W_1K_1%_0402
EMC_NS@
+VL_3.3V

PR0307
PC0315

4.7U_6.3V_K_X5R_0603
9 1 2 680P_50V_K_X7R_0402
VCC

AGND

PGND
PR0304 @ @

+5V_VCC
1
@ PR0309+5VALW_P

PC0307
1/16W_0_5%_0402

2
1/16W_0_5%_0402

4
2

1U_6.3V_K_X5R_0402_MURATA
2

1
PC0305
PC0317 @ PR0303

2
1U_25V_K_X7R_0603_YAGEO 1/16W_15K_5%_0402
PR0301 1

2
0_0402_SP

2
1

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DC/DC VCC5M (LV6228)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632 2.0

Date: Tuesday, October 13, 2020 Sheet 103 of 128

5 4 3 2 1
 5 4 3 2 1

VSYS15 VSYS15 [51,100,102,103,105,106,108,109,110,117,118]

VCC5M_PD VCC5M_PD [59]

D D

VCC3M

1
@ PR0401
1/16W_100K_5%_0402
VCC5M_PD
FSW=750 KHz

VCC5M_PD_PG 2
TDC:8A

10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR
OCP:12A
VSYS15 @
PJ0401 PR0402 PC0410
2 1 +5V_VIN_1 1/10W_10_5%_0603 0.1U_25V_M_X7R_0603
2 1

2200P_25V_K_X7R_0402
47P_50V_J_NPO_0402
+5VBS_1 1 2 1 2

0.1U_25V_K_X5R_0402
1

1
RF_NS@ PC0417

EMC@ PC0411

EMC@ PC0406

PC0409

PC0415
JUMP_43X79 PU0401
VCC5M_PD

1
C C
PL0401
8A

PGOOD

BOOT
2

2
2 1UH_PCMC063T-1R0MN_11A_20% PJ0402
5 2 +5VLX_1 1 2 2 1
VIN LX1 2 1

2
3 EMC_NS@ @ JUMP_43X118
LX2

2200P_25V_K_X7R_0402
PR0405
3V5V_ON

0.1U_25V_K_X5R_0402
22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25
PR0404 1/10W_4.7_5%_0603
0_0402_SP LV6228CGQUF_UQFN12_3X3 1 1

1
PC0413

PC0405

PC0403

PC0404

EMC@ PC0416

EMC@ PC0407
1 2 6 10 +5VOUT_1

1
EN VOUT

0.1U_25V_K_X5R_0402
@ PR0403

2
1

2
2 2

PC0402
1/16W_0_5%_0402 12
[85,116] M_ON2 1 2 CLK 11
100mA
LDO EMC_NS@

1
PC0408

4.7U_6.3V_K_X5R_0603
9 680P_50V_K_X7R_0402
VCC

AGND

PGND

+5V_VCC_1
1

PC0414
1U_25V_K_X7R_0603_YAGEO
8

4
2
2

1
PC0412
PC0401
1U_6.3V_K_X5R_0402_MURATA

2
1
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +5VTPC(LV6228C)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632 2.0

Date: Tuesday, October 13, 2020 Sheet 104 of 128

5 4 3 2 1
 5 4 3 2 1

VSYS15 VSYS15 [51,100,102,103,104,106,108,109,110,117,118]

VCC3M VCC3M [4,13,16,51,52,55,56,59,84,85,86,88,102,103,104,106,110,116,118,119,120,123,124,125,126,127,128]

D D

VCC3M

1
@ PR0501 VCC3M
1/16W_100K_5%_0402
FSW=750 KHz
VSYS15
PU0501 TDC:8A

2
@ SYX198BQNC_QFN10_3X3

2
PJ0501
1 +3V_VIN 7 2 +3V_PWRGD
OCP:11A
2 1 EN2 PG

2200P_25V_K_X7R_0402
PR0503 PC0504

1
0.1U_25V_K_X5R_0402

47P_50V_J_NPO_0402

10U_25V_K_X5R_0805_H1.25_MUR
1 0_0603_SP 0.1U_25V_M_X7R_0603
VCC3M

1
PC0505
JUMP_43X79 PR0502 8 6 +3VBS 1 2 1 2

PC0501
IN BS

PC0503
RF_NS@ PC0502
1/16W_1M_5%_0402 PL0501
2.2UH_CMLE063T-2R2MS_10A_20% PJ0502
8A

2
2 9 10 +3VLX 1 2 +3VALW_P 2 1
3V5V_ON

2
GND LX PR0504 2 1
C EMC@ 0_0402_SP @ JUMP_43X118 C

2200P_25V_K_X7R_0402
EMC@ 3V5V_ON 1 4 +3VALW_OUT 1 2 +3VALW_P EMC_NS@
EN1 OUT

0.1U_25V_K_X5R_0402
22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25
PR0506 PR0505
0_0402_SP 1/10W_4.7_5%_0603
100mA 1 1 1 1

1
PC0508

PC0506

PC0509

PC0512

EMC@ PC0510

EMC@ PC0513
PR0507 +3VALW_FB 3 5 1 2
1/16W_20K_1%_0402 FB LDO VCC3SW

2 1
[86] M_ON M_ON 1 2 1

2
PC0511 EMC_NS@ 2 2 2 2
4.7U_6.3V_K_X5R_0603 PC0507
1 2 680P_50V_K_X7R_0402

1
@ PR0508 1/20W_0_5%_0201 2

1
2
PR0509
VCC3SW_EC @ PC0514 1/16W_1M_5%_0402
0.1U_25V_K_X5R_0402

1
1/20W_47K_5%_02011/16W_47K_1%_0402
PC0515 PR0512

2
1

PR0511
1/16W_47K_1%_0402

0.01U_25V_K_X7R_0402 1/16W_1K_1%_0402
1

PR0510

1 2 1 2
2

6
D
2

2
2

G PQ051A
3

B
D 2N7002KDWH_SOT363-6 B
@PR0513

[40,85,100,101] -PWRSHUTDOWN 5 S

1
G
PQ051B
1

S
4

2N7002KDWH_SOT363-6

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DC/DC VCC3M (SYX198)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632 2.0

Date: Tuesday, October 13, 2020 Sheet 105 of 128

5 4 3 2 1
 A B C D

1 1

PJ0602
2 1
2 1
VSYS15 VSYS15 [51,100,102,103,104,105,108,109,110,117,118]
@ JUMP_43X118
VCC1R2A VCC1R2A [4,5,14,15,33,34,35,36]
PJ0603
VCC0R6B VCC1R2AP 2 1 VCC1R2A
VCC0R6B [33,34,35,36] 2 1
@ JUMP_43X118

PJ0604
VCC0R6B
VCC0R6BP
2
2 1
1
VCC0R6B TDC: 1.5A
PU0601 @ JUMP_43X39

PC0602
0.1U_25V_K_X5R_0402
VCC1R2A
PJ0601 EMC@ EMC@ RF_NS@ RF_NS@ 1 1 2 TDC: 8.4A
VSYS15 2
2 1
1 VSYS15_1.2V 2
IN1
BS
OCP: 10A
10U_25V_K_X5R_0805_H1.25_MUR

10U_25V_K_X5R_0805_H1.25_MUR

2200P_25V_K_X7R_0402
0.1U_25V_K_X5R_0402

47P_50V_J_NPO_0402

68P_50V_J_NPO_0402
@ JUMP_43X79 Fsw: 300KHz

1
1 3
IN2
1

1
PC0601

PC0604

PC0605

PC0606

PC0607
2 6 PR0611 2
LX1
PC0603

0_0402_SP
4
2

2
2 IN3 19

2
LX2 PL0601
5 0.68UH_PCMC063T-R68MN_15.5A_20%
IN4

1/16W_20K_1%_0402
20 LX_1.2V 1 2 VCC1R2AP
LX3 VCC1R2AP

2
SY8310RAC_QFN20_3X3

1/10W_4.7_5%_0603
PC0608

2200P_25V_K_X7R_0402
EMC_NS@

PR0603
330P_50V_K_X7R_0402

680P_50V_K_X7R_0402
PR0602

0.1U_25V_K_X5R_0402
22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25

22U_6.3V_M_X5R_0805_MUR_H1.25
7 15 FB_1.2V 1 1 1 1 1 1

2
PG FB

1
PC0625

PC0614

PC0624

PC0609

PC0615

PC0610

EMC@ PC0611

EMC@ PC0612
1/16W_20K_1%_0402
1

2 1
@ PR0601

1
PC0613
1/16W_100K_1%_0402

2
2
2 2 2 2 2 2

PR0613
14 PR0612
VDDQ

EMC_NS@
PR0614

2
1/16W_4.7_1%_0402 1/16W_1K_1%_0402

1
1 2 17
VCC3M

1
BIAS
1
PC0616 13
4.7U_10V_K_X5R_0402 VTT
PR0605
0_0402_SP 2 12 VCC0R6BP
1 2 S3_1.2V 10 VTTSNS
[4] DDR_VTT_PG_CTRL S3 VCC0R6BP @ @

22U_6.3V_M_X5R_0603
1/16W_1M_5%_0402

0.1U_25V_K_X5R_0402
PR0606 @
1

1
22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

PC0621
1/16W_0_5%_0402
1

1
PR0610

PC0618

PC0619

@ PC0620
[52,72,78,86,125,127] B_ON 2 1
@ PC0617 11 VTTREF_0.6V
VTTREF_0.6V

2
3 0.1U_6.3V_K_X7R_0402 9 VTTREF 3
2

2
S5
2

PR0607 1
@ 1/16W_0_5%_0402

GND1

GND2
1 2 S5_1.2V PC0622

TEST
GND
[13,107,123] -PCH_SLP_S4 1U_10V_K_X6S_0402
2
1/16W_1M_5%_0402

1 2
21

18

16
[86,107] A_ON
1
PR0609

PR0608
1

0_0402_SP PC0623
0.1U_16V_K_X7R_0402_MURATA
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 DC/DC VCC1R2A(RT8231)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632
2.0

Date: Tuesday, October 13, 2020 Sheet 106 of 128

A B C D
 5 4 3 2 1

VCC5M VCC5M [51,69,70,72,84,85,103,108,109,110,116,117,118,119,120,125,126,127]

VCC2R5A VCC2R5A [33,34,35,36]

D D

VCC2R5A
TDC: 2A
OCP: 4A
Fsw: 1MHz
@ PJ0702
@ PJ0701 PL0701 JUMP_43X39

4
JUMP_43X39 1UH_PH041H-1R0MS_20%
2 1 VIN_+2.5VSP 10 1 2.5VSP_LX 1 2 +2.5VSP 2 1 VCC2R5A
VCC5M

PG
2 1 PVIN2 LX1 2 1

2
9 2 EMC_NS@
PVIN1 LX2

1
PR0702

22P_50V_J_NPO_0402
C PC0701 PC0702 8 3 1/10W_4.7_5%_0603 C
SVIN1 LX3

1
10U_10V_K_X5R_0603 10U_10V_K_X5R_0603 EMC@ EMC@

PC0703
PU0701 PR0703

2 1

2200P_25V_K_X7R_0402
22U_6.3V_M_X6S_0805_H1.25

22U_6.3V_M_X6S_0805_H1.25

0.1U_25V_K_X5R_0402
RT8068AZQW_WDFN10_3X3 1/16W_31.6K_1%_0402

1
20170901 5 6 EMC_NS@

GND

2
EN FB

PC0707

PC0705

PC0708

PC0706
@ PR0701 PC0704

NC
1/16W_0_5%_0402 680P_50V_K_X7R_0402

2
1 2

11

7
[13,106,123] -PCH_SLP_S4

2
1 2 EN_2.5VSP
[86,106] A_ON

1
PR0704 @ PR0705 @ PC0709
0_0402_SP 1/16W_1M_5%_0402 0.22U_10V_K_X5R_0402

2
PR0706

1
1/16W_10K_1%_0402

2
B B

A Security Classification LC Future Center Secret Data Title A

Issued Date 2013/08/05 Deciphered Date 2014/12/31 DC/DC VCC2R5A(RT8068A)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632
2.0

Date: Tuesday, October 13, 2020 Sheet 107 of 128

5 4 3 2 1
 5 4 3 2 1

PU0801
VSYS15
VCC5M RT3613EEGQW_WQFN32_4X4
PR0805
PR0801
1/10W_2.2_1%_0603
1 2 VCC 24 8 AU1_VIN 1 2
VCC VIN
1/10W_6.2_1%_0603 1 PC0803
PC0801 1 2
4.7U_10V_K_X5R_0402
0.47U_25V_K_X5R_0402_YAGEO
2

PR0802
1/16W_75_5%_0402
VREF06 1 2 VRHOT16 12 PWM1_CORE [109]
[6,59,85,102] -PROCHOT VR_HOT# PWM1
1/16W_1.15K_1%_0402

1/16W_33.2K_1%_0402

VREF06
PR0807
B B

PWM2_CORE [109]
1/16W_75K_1%_0402

VREF_RC 1 2 26 13
VREF06 PWM2
1

2
PR0804

1
PR0803

PR0806

PR0808 1/16W_3.9_1%_0402
0_0402_SP PC0802
0.47U_25V_K_X5R_0402_YAGEO
2 11
SET1_H 2

PIN_TSEN_H 1

PWM3
SET2_H

SET3_H

DRVEN 15
[109] DRVEN DRVEN
PR0810 PR0811
ISEN1P_R 1
1/16W_5.1K_1%_0402

1 2 1 2 2
CORE_ISEN1P [109]
1/16W_200_1%_0402

1/16W_470_1%_0402

PR0816
1

1
1/16W_110K_1%_0402 PR0809 4 AU1_ISEN1P 1 1/16W_2.55K_1%_0402 1/16W_2.55K_1%_0402
ISEN1P
PR0812

PR0813

PR0814

1 2 1/16W_10K_1%_0402 PR0817
PR0815 1/16W_1.2K_1%_0402 PC0804
1/16W_15K_1%_0402 PT0802 0.1U_50V_K_X7R_0402
PR0818 2
100K_0402_1%_NCP15WF104F03RC
2

2
PINSET_TSEN 2 1 TSEN 7 3 AU1_ISEN1N 1 2
TSEN ISEN1N PC0805 CORE_ISEN1N [109]
1/16W_680_1%_0402 0.1U_50V_K_X5R_0402
Close to Phase1 Mosfet 1 2
AU1_SET1 22 PR0819 PR0820
AU1_SET2 SET1 AU1_ISEN2P ISEN2P_R 1
1/16W_1.15K_1%_0402

21 1 1 2 2
AU1_SET3 20 SET2 ISEN2P CORE_ISEN2P [109]
SET3

1
1/16W_17.8K_1%_0402

1/16W_28.7K_1%_0402

1 1/16W_2.55K_1%_0402 1/16W_2.55K_1%_0402
PR0826 PR0821
1

1
PR0823

0_0402_SP 1/16W_1.2K_1%_0402 PC0806

PR0822

PR0824

1 2 AU1_VRON 9 2 AU1_ISEN2N PR0827 0.1U_50V_K_X7R_0402

PR0825 [13,86] CPUCORE_ON VRON ISEN2N 1/16W_680_1%_0402 2

2
1/16W_18.2K_1%_0402 2 1 2
PC0808 CORE_ISEN2N [109]
SET1_L 2

SET3_L 2

PIN_TSEN_L 2

0_0201_SP
@ PC0807 14 0.1U_50V_K_X5R_0402
VCCST NC1

1
1U_16V_M_X5R_0201 5 1 2
SET2_L

1 ISEN3P

PR8040
0.1U_25V_K_X5R_0402

1/16W_100_1%_0402
1/16W_1.5K_1%_0402

32 PR0831 1/16W_10K_1%_0402

2
NC2 AU1_ISEN3N
1/16W_45.3_1%_0402

6 1 2
ISEN3N VCC5M
1

1
0_0402_SP

0_0402_SP

0_0402_SP

PC0809
PR0828

PR0829

PR0830

PR0832

PR0833

PR0834

PR0835
1/16W_0_5%_0402

VCC5M
2

2
2

@
@ PR0836
PR0837 1/16W_10K_1%_0402
0_0402_SP

1
1 2 SVID_VCLK 19 31 ANS_EN 1 2
[14] SVID_CLK VCLK ANS_EN
PR8038
PR8053 1/16W_10K_1%_0402
0_0402_SP
1 2 SVID_VDIO 18 28
[14] SVID_DATA VDIO VSEN VCC_SENSE [14]
PR0842 PC0810
0_0402_SP 82P_50V_G_COG_0402 PC0811
1 2 SVID_ALERT 17 29 AU1_COMP 1 2 1 2
[14] -SVID_ALERT PR0843 ALERT# COMP
PR0844
1/16W_10K_1%_0402 PR0845 120P_50V_J_NPO_0402
1 2 1 2 1 2 1 2
VCC1R8_SUS PR0846 1/16W_20K_1%_0402
VGATE 10 30 AU1_FB 1/16W_23.2K_1%_0402 1/16W_22.1K_1%_0402
Close to Phase1 Inductor
[13,85] VGATE VR_READY FB AU1_FB
2

PT0801 [102] PSYS 23 27

100K_0402_1%_NCP15WF104F03RC
PSYS RGND VSS_SENSE [14]
1

2
PR0848
1

@ PC0812 1/16W_16K_1%_0402
0.1U_50V_K_X5R_0402 AU1_IMON 25 33
IMON GND
1

A
1 A
2

PR0850
1/16W_3K_5%_0402
2

1 2 1 2
VREF06 PR0851 PR0852
1/16W_17.4K_1%_0402 1/16W_26.1K_1%_0402

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CPU_CORE_RT-1A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
GL4A0/GL5A0 NM-C6320.3
Date: Tuesday, October 13, 2020 Sheet 108 of 128
5 4 3 2 1
 5 4 3 2 1

PL0901
BLM18KG300TN1D
EMC@ 1 2
EMC@ VSYS15
RF_NS@ EMC@

2200P_25V_K_X7R_0402
PC0901 PC0902 PC0903 PC0904 PC0905 PC0906 PL0902

47P_50V_J_NPO_0402
1 1 1 BLM18KG300TN1D
TGL U

0.1U_25V_K_X5R_0402
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

PC0907
1 2

2.2_0603_1% EMC@
VCCCPUCORE

2
PR0901 2 2 2
2.2_0603_1% 2 1
TDC= 43A

5
D PR0905 1 D
2 1 PC0908 PQ0901
VCC5M 0.22U_25V_K_X7R_0603 AON6380_DFN8-5 IccMAX=65A
PC0910
1U_10V_K_X5R_0402
1 2 OCP=91A
2
PU0901
BOOT
4
Vcore_HG14

Vcore_PH1
teknisi-indonesia.com
8
VCC 3 PL0903
5 UGATE 0.22UH_CMLE062D-R22MS1R957_25A_20%
[108] PWM1_CORE

3
2
1
PWM 2 Vcore_PH1 1 4
PHASE
[108] DRVEN
1
EN
VCCCPUCORE

2
7 2 3 1
6 LGATE PR0902
GND1 9 + @PC0909
GND2 4.7_0603_5%
330U_D2_2.5V_Y
RT9610CGQW_WDFN8_2X2 EMC_NS@

1
Vcore_LG14 4 2
1
PC0911
680P_50V_K_X7R_0402
2

3
2
1

3
2
1
PQ0902
AONS36323_DFN
PQ0903
AONS36323_DFN
EMC_NS@
CORE_ISEN1N [108]

C C

CORE_ISEN1P [108]

PL0904
BLM18KG300TN1D
EMC@ 1 2
EMC@ EMC@ VSYS15
RF_NS@

2200P_25V_K_X7R_0402
PC0912 PC0913 PC0914 PC0915 PC0916 PC0917 PL0905

47P_50V_J_NPO_0402
1 1 1 BLM18KG300TN1D

0.1U_25V_K_X5R_0402
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

PC0918
1 2
2.2_0603_1% EMC@
PR0903

2
2 1 2 2 2
2.2_0603_1% 1

5
PR0906
2 1 PC0919 PQ0904
VCC5M 0.22U_25V_K_X7R_0603
2
AON6380_DFN8-5
PC0920 1
1U_10V_K_X5R_0402
PU0902 Vcore_HG24
4
2 8 BOOT Vcore_PH2
B VCC B
3 PL0906
5 UGATE 0.22UH_CMLE062D-R22MS1R957_25A_20%
[108] PWM2_CORE
3
2
1
PWM 2 Vcore_PH2 1 4
PHASE
DRVEN 1
EN
VCCCPUCORE
5

2
7 2 3 1
6 LGATE PR0904
GND1 9 + PC0922
GND2 4.7_0603_5%
330U_D2_2.5V_Y
EMC_NS@
RT9610CGQW_WDFN8_2X2
1
Vcore_LG24 4 2
1
PC2021
680P_50V_K_X7R_0402
2
3
2
1

3
2
1

PQ0905
AONS36323_DFN
PQ0906
AONS36323_DFN
EMC_NS@
CORE_ISEN2N [108]

CORE_ISEN2P [108]

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632
2.0

Date: Tuesday, October 13, 2020 Sheet 109 of 128

5 4 3 2 1
 5 4 3 2 1

VSYS15 VSYS15 [51,100,102,103,104,105,106,108,109,117,118]

VCC5M VCC5M [51,69,70,72,84,85,103,107,108,109,116,117,118,119,120,125,126,127] VSYS15

VSYS15
PL1002
BLM18KG300TN1D
EMC@

2
D 1 2 D
PR1002 EMC@
0_0603_SP RF_NS@ EMC@

2200P_25V_K_X7R_0402

68U_D3L_25VM_R70M

68U_D3L_25VM_R70M

68U_D3L_25VM_R70M
PC1004 PC1005 PC1006 PC1007 PC1009 PC1002 PL1003

47P_50V_J_NPO_0402
2.2_0603_1% 1 1 1 BLM18KG300TN1D

1
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

0.1U_25V_K_X5R_0402

PC1010
PR1003 1 2 1 1 1
PC1003
2 1
EMC@ + + +

PC1012

PC1013

PC1015
1 2 2

2
2 2 2
0.1U_25V_K_X5R_0402 PC1008

5
2 2 2

20

10
0.1U_25V_K_X5R_0402
1 PQ1001 @ @ @
AON6380_DFN8-5

VSYS

BOOT
PR1007
PR1005
1/10W_5.1_5%_0603
1 2 16 11 AUX_HG 1 2 AUX_HG_R 4
VCC5M 2
VCC
PU1001
UGATE

PC1011 RT6543AGQW_WQFN20_3X3 0_0603_SP PL1001

1U_25V_K_X7R_0603_YAGEO 15 12 0.22UH_CMLE062D-R22MS1R957_25A_20%

3
2
1
1 PVCC PH AUX_PH 1 4
PR1006 VCCPCHCORE
VCCPCHCORE

2
1/16W_100K_1%_0402 2 3 1
VCC1R8_SUS 1 2 4 13 AUX_LG PR1010
C
[85] VCCIN_AUX_PGD
PGOOD LGATE
4.7_0603_5% + PC1001
470U_D2E_2.5VM_R7M
TDC= 14A C

PR1011
0_0402_SP EMC_NS@ IccMAX=27A

1
1 2 19 2 ISENSEP 4 4 2
[116] V1R8_SUS_PWRGD EN ISENSEP 1
OCP=35A

@ PR1023
1/20W_0_5%_0201
PR1012
@ PR1024 1 2 PC1019 1/16W_10.2K_1%_0402
1/16W_0_5%_0402 PC1020 680P_50V_K_X7R_0402
1 2 0.1U_25V_K_X5R_0402 18 3 ISENSEN 2
[85] VCCIN_AUX_EN

3
2
1

3
2
1

2
VID0 ISENSEN PQ1002 PQ1003 EMC_NS@ 0.1U_25V_K_X5R_0402

1
PR1027 1 2 0_0402_SP AONS36323_DFN AONS36323_DFN 1 2
[16] VCCPCHCORE_VID0
PC1014
PR1028 1 2 0_0402_SP 17 8 PR1013 PR1014
[16] VCCPCHCORE_VID1 VID1 VOUT 1 2 1 2
1/16W_100K_1%_0402

PR1001 1/16W_866_1%_0402 1/16W_510_1%_0402

1/16W_100K_1%_0402 1 2
1

1 2 9 5 PR1015
FSWSEL COMP
PR1026

PR1025 0_0603_SP PR1022 0_0201_SP

VCC5M
1

1/16W_100K_1%_0402 1 2 1 2
PR1017
PR1016 1 2 1 6 PR1018 @ @ PT1001
PC1016 PR1019
2

1/16W_100K_1%_0402 CS_DIS FB 2200P_50V_K_X7R_0402 1/16W_10K_1%_0402 1.5K_0402_3%_NCP15XW152E03RC

1/16W_120K_1%_0402 1 2 1 2 1 2 1 2
2

PC1018 1/16W_1.6K_1%_0402
21 7 PC1017 390P_50V_K_X7R_0402_YAGEO
B
VCC3M AGND RGND 1 2 1 2
B

PR1021 VCCPCHCORE_SENSE [16]

PGND

27P_50V_J_NPO_0402 1/16W_6.34K_1%_0402

VSSPCHCORE_SENSE [16]
14

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 VCCPCHCORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C6320.3
Date: Tuesday, October 13, 2020 Sheet 110 of 128
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 VCCSA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632
2.0

Date: Tuesday, October 13, 2020 Sheet 111 of 128

5 4 3 2 1
 5 4 3 2 1

D VCCCPUCORE D

1 1 1 1 1 1 1 1 1
PC1201 PC1211 PC1212 PC1213 PC1214 PC1215 PC1216 PC1217 PC1218
22U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_0603
2 2 2 2 2 2 2 2 2

VCCCPUCORE

1 1 1 1 1 1 1 1 1
PC1230 PC1231 PC1232 PC1233 PC1234 PC1235 PC1236 PC1237 PC1238
22U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_060322U_6.3V_M_X5R_0603
C 2 2 2 2 2 2 2 2 2 C

VCCPCHCORE
VCCPCHCORE
22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
2 2 2 2 2 2
PC1249

PC1250

PC1251

PC1252

PC1253

PC1254 2 2 2 2 2 2 1

PC1255

PC1256

PC1257

PC1258

PC1259

PC1261

PC1244
1 1 1 1 1 1
1 1 1 1 1 1 2
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
GL4A0/GL5A0 NM-C632 0.1

Date: Tuesday, October 13, 2020 Sheet 112 of 128

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
GL4A0/GL5A0 NM-C632 0.1

Date: Tuesday, October 13, 2020 Sheet 113 of 128

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 DC/DC VCC1R05_SUS(NB653)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632
0.1

Date: Tuesday, October 13, 2020 Sheet 114 of 128

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
GL4A0/GL5A0 NM-C632 0.1

Date: Tuesday, October 13, 2020 Sheet 115 of 128

5 4 3 2 1
 5 4 3 2 1

VCC5M VCC5M [51,69,70,72,84,85,103,107,108,109,110,117,118,119,120,125,126,127]

PR1606 VCC3M
100K_0402_1%
VCC1R8_SUS 1 2
VCC1R8_SUS [7,9,11,16,51,78,85,108,110,117]
D D
VCC1R8_SUS
TDC: 2A
OCP: 4A
V1R8_SUS_PWRGD [110]
Fsw: 1MHz

PU1601 @ PJ1602
RT8068AZQW_WDFN10_3X3 PL1601 JUMP_43X39

4
PJ1601 1UH_PH041H-1R0MS_20% VCC1R8_SUS
2 1 VIN_+1.8VSP 10 1 1.8VSP_LX 1 2 +1.8VSP 2 1
VCC5M

PG
2 1 PVIN2 LX1 2 1

2
9 2
@ JUMP_43X39
1 1 PVIN1 LX2 EMC@EMC@

22P_50V_J_NPO_0402
PR1602 1

2200P_25V_K_X7R_0402
22U_6.3V_M_X6S_0805_H1.25

22U_6.3V_M_X6S_0805_H1.25

0.1U_25V_K_X5R_0402
PC1601 PC1608 8 3 4.7_0603_5%
C
SVIN1 LX3 EMC_NS@ C

PC1605
10U_10V_K_X5R_0603 10U_10V_K_X5R_0603 PR1603
2 2 1/16W_20K_1%_0402

1
2
1 1 1 1 1

PC1604

PC1603
5 6

GND
EN FB

PC1606

PC1609
PR1605 PC1602

NC
0_0402_SP 680P_50V_K_X7R_0402
1 2 EN_1.8VSP 2 2 2 2 2

11

7
[85,104] M_ON2
EMC_NS@

1/16W_1M_5%_0402
1
1 2 1

1
@PC1607

PR1601
@ PD1601 0.22U_10V_K_X5R_0402 PR1604
CUS357_SOD323-2 2 1/16W_10K_1%_0402

2
B B

A Security Classification LC Future Center Secret Data Title A

Issued Date 2013/08/05 Deciphered Date 2014/12/31 DC/DC VCC1R8_SUS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
GL4A0/GL5A0 NM-C632
2.0

Date: Tuesday, October 13, 2020 Sheet 116 of 128

5 4 3 2 1
 5 4 3 2 1

PR1702
0_0201_SP
1 2
[40] GFXCORE_D_EN
VCC1R8VIDEO_AON VCC1R8_SUS MLCCs must be placed
symmetrically on Top and Bottom. DIS_EMC@
PL1701

1
DIS@ BLM18KG300TN1D
PR1703 @ PR1704 DIS_EMC@ DIS_EMC@ 1 2
VSYS15

1000P_25V_K_X7R_0402
0.1U_25V_K_X5R_0402
1/20W_10K_1%_0201 1/20W_10K_1%_0201

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
TABLE : PC1514 / PC1515

2
D 1 1 1 1 1 1 1 D

PC1702

PC1703

DIS@ PC1704

DIS@ PC1705

DIS@ PC1706

PC1701
PR1705 DIS@
0_0201_SP UGATE1_VGA PC1707 1st: 2R5TPE470M7 PANASONIC
[40] VGA_CORE_PSI 1 2 PSI_VGA 0.1U_25V_K_X5R_0402
DIS@ DIS@ 2 2 2 2 2 2 2
PR1707 PC1709
2nd : T520V477M2R5ATE007 KEMET

DIS@
1 1/10W_1_1%_0603 0.22U_25V_K_X5R_0402
@ PR1706 1 2 1 2
@ PC1708 1/20W_10K_1%_0201 PR1708 Table PL1501、PL1502
0.1U_25V_K_X5R_0402 0_0201_SP
2 1 2 DIS@ CYNTEC : CMLE063T-R15MS0R907

BOOT1_VGA
[40] VIDEO_PWM_VID

2
PHASE1_VGA PR1709 DIS@

10
3
4
1/16W_1.5_1%_0402 PQ1701
DIS@ UGATE1_VGA 1 2 1 AOE6930_DFN8-10 DIS@
PR1710 PL1702
1/20W_20.5K_1%_0201 0.15UH_CMLE063T-R15MS0R907_38A_20%
VREF_272 1 2 5 PHASE1_VGA_M 1 2 DIS_EMC@ DIS_EMC@
VCCGFXCORE_D

0.1U_25V_K_X7R_0402
PHASE1_VGA 2 6

2200P_50V_K_X7R_0402
DIS@ LGATE1_VGA 7 2
LGATE1_VGA

10U_6.3V_M_X5R_0603_YAGEO

10U_6.3V_M_X5R_0603_YAGEO

10U_6.3V_M_X5R_0603_YAGEO

10U_6.3V_M_X5R_0603_YAGEO
@ PC1710 PR1711 8
2700P_25V_K_X7R_0201 1/20W_6.19K_1%_0201 PC1711 1 1

PC1712

PC1713
1 2 1 2 470P_50V_K_X7R_0201 1 1 1 1
1

VID_VGA

PSI_VGA

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
1 1 1 1

VIDBUF
1
+ + + +

PC1716

PC1717

PC1718

PC1719

DIS@ PC1714

DIS@ PC1715

DIS@ PC1744

DIS@ PC1745
DIS_EMC_NS@

2
DIS@ 2 2
PR1712 PR1713
DIS@ DIS@ 1/20W_4.32K_1%_0201 2 2 2 2 2 2 2 2
1/4W_2.2_5%_0603
PR1715 PR1716

DIS@

DIS@

DIS@

DIS@
1/20W_309_1%_0201 1/20W_16.5K_1%_0201
DIS_EMC_NS@

1
1

DIS@ 1 2 1 2

PSI
VIDBUF

VID

EN

HG1

BST1
PR1714
1/20W_100_1%_0201 TABLE : PQ1501,PQ1502
DIS@ PC1720 1 2 4700P_25V_K_X5R_0201 REFIN_272 7 20 PC1722
REFIN PH1 4.7U_6.3V_K_X5R_0603
MLCCs must be placed
2

DIS@ PC1721 1 2 0.01U_25V_K_X7R_0402 VREF_272 8 19 1 2 AOS : AOE6930

VREF LG1
DIS@
ON : NTMFD001N03P9 symmetrically on Top and Bottom.
PR1718 DIS@ PR1717 1 2 1/20W_34K_1%_0201 FS 9 PU1701 21 DIS@
0_0201_SP FS NCP81278TMNTXG_QFN20_3X3PAD
C C
1 2 FBRTN 10 18
[42] GPU_GND_SENSE
DIS@ FBRTN PVCC VCC5M
DIS@ 1 DIS@ PR1719 FB_VGA 11 17
PC1723 PC1724 1/20W_49.9_1%_0201 DIS@ PC1725 FB LG2
100P_25V_J_NPO_0201 1 2 FB1_VGA 1 2 1 2 COMP_VGA 12 16
COMP/ILMT PH2 MLCCs must be placed

PGOOD
2 47P_50V_J_NPO_0402 22P_50V_J_NPO_0402 symmetrically on Top and Bottom.

BST2
DIS_EMC@

HG2
1 2 1 2 1 2FB2_VGA 1 2
[42] GPU_VDD_SENSE
DIS@ PL1703
PR1720 DIS@ DIS@ DIS@ PR1722 PR1723 BLM18KG300TN1D
DIS_EMC@ DIS_EMC@ VSYS15

13

14

15

VEEO
CDDC
CP
GC
Fo
Xn
C==A
O
R15
E60
_.
DA
0_0201_SP PR1721 PC1726 1/20W_51.1K_1%_0201 1/10W_1_1%_0603 1 2

1000P_25V_K_X7R_0402
0.1U_25V_K_X5R_0402
1/20W_10K_1%_0201 220P_25V_J_X7R_0402 BOOT2_VGA 1 2

-P
tk

3
1

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
DIS@ DIS@

PP
-
e
a7

A
PR1724 PR1701 UGATE2_VGA 1 1 1 1 1 1

PC1728

PC1729

DIS@ PC1730

DIS@ PC1731

DIS@ PC1732

DIS@ PC1733
1/20W_100_1%_0201 1/16W_19.6K_1%_0402 1 1 DIS@

=
6
2
PC1727 PC1734
2

0.22U_25V_K_X5R_0402 2 2 2 2 2 2 0.1U_25V_K_X5R_0402
GFXCORE_D_PWRGD [37,40,50,118] 2 2
DIS@
VCCGFXCORE_D
DIS@
PR1725 PHASE2_VGA
1/20W_10K_1%_0201
1 2
VCC3_SUS VCCGFXCORE_D
DIS@
PR1726 DIS@
MLCCs must be placed

10
3
4
1/16W_1.5_1%_0402 PQ1702 symmetrically on Top and Bottom.
LGATE2_VGA UGATE2_VGA 1 2 1 AOE6930_DFN8-10 DIS@
PL1704
0.15UH_CMLE063T-R15MS0R907_38A_20%
5 PHASE2_VGA_M 1 2 DIS_EMC@ DIS_EMC@
PHASE2_VGA 2 6

2200P_50V_K_X7R_0402
0.1U_6.3V_K_X5R_0201
7 2
B
LGATE2_VGA 8 B

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
PC1735
470P_50V_K_X7R_0201
1
DIS_EMC_NS@ 1 1 1 1 1 1 1 1

DIS@ PC1736

DIS@ PC1738

DIS@ PC1737

DIS@ PC1739

DIS@ PC1740

DIS@ PC1741

PC1742

PC1743
9

2
PR1727 2 2 2 2 2 2 2 2
1/4W_2.2_5%_0603
DIS_EMC_NS@

1
VCC5M VCCGFXCORE_D
1

DIS@
1

DIS@ PR1729
PR1728 1/10W_10_5%_0603
1/16W_100K_5%_0402
2
2

www.teknisi-indonesia.com
3

D
5 DIS@
G PQ171B
6

D UM6K33N_UMT6
GFXCORE_D_EN 2 DIS@ S
4

G PQ171A
A UM6K33N_UMT6 A
S
1

Document Number

DORAEMON
Size Title Rev
Custom 0.01
BLANK
Date: Tuesday, October 13, 2020 Sheet 117 of 128
5 4 3 2 1
 5 4 3 2 1

VCC3M

1
DIS@
PR1816
1/10W_5.1_5%_0603

VTO
CDC
CC
1==
R12
210
VAA
I
D
E
O
D 2 DIS@ D
PC1802
1U_6.3V_K_X5R_0402

P
1
@ PJ1801
DIS_EMC@ DIS_EMC@ DIS_RF_NS@

2
1 2 VCC1R2VIDEO_VIN DIS@
VSYS15 1 2 PR1817

2200PC_50VC_KC_X7RC_0402
0.1UC_25VC_KC_X5RC_0402
JUMP_43X79 1/20W_150K_1%_0201

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
DIS@ DIS@

47PC_50VC_JC_NPOC_0402
PR1801 PC1803
VCC1R2VIDEO

1
1 1 1 1 1 1 1 1/16W_2.2_5%_0402 0.1U_25V_K_X7R_0402_MURATA

DIS@ PC1811

DIS@ PC1810

DIS@ PC1809

DIS@ PC1805

PC1807

PC1806

PC1808
1 2 1 2

18

19

13
7
2 2 2 2 2 2 2

3V3

AGND

FS

BST1
DIS@
2 PL1801 DIS_EMC@ @ PJ1802
VIN 12 0.22UH_CMMS063T-R22MS2R107_26A_20% DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS_EMC@ JUMP_43X79
SW1 VCC1R2VIDEO_SW 1 2 VCC1R2VIDEO_R 1 2
1 2

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
11

2200PC_50VC_KC_X7RC_0402
1 SW2

0.1UC_6.3VC_KC_X7RC_0402
PGND1 1
DIS@ DIS@ 2 2 2 2 2 2 2 2 2 1 @ PJ1803

PC1812

PC1815

PC1816

PC1817

PC1818

PC1819

PC1820

PC1821

PC1813

PC1814
3 10 1 2 1 2 PC1822 JUMP_43X79
PGND2 BST2

2
PU1801 PR1802 680PC_50VC_KC_X7RC_0402 1 2
PC18013300P_50V_K_X7R_0402 1/16W_2.2_5%_0402 DIS@ PC1804 2 DIS_EMC_NS@ DIS@ 1 2
MP2941AGL-Z_QFN19_3X4 PR1815 0.1U_25V_K_X7R_0402_MURATA PR1821 1 1 1 1 1 1 1 1 1 2
C C

1
2 1 6 0_0402_SP 1/16W_10_1%_0402
VCC1R8VIDEO_AON SS 16 1 2 PR1806

1
PR1814 VOUT
DIS@ 0_0201_SP 1/10W_4.7_5%_0603
1 2 5 DIS_EMC_NS@ VCC1R2VIDEO_FB_R
VID 17 VCC1R2VIDEO_FB

2
FB

1
DIS@ 1 4 DIS@
PGND3

MODE
PC1823 9 PR1819

CLM
0.01UC_25VC_KC_X7RC_0402 PG 1/16W_20K_1%_0402

EN

2
2

1 14

15
1/20W_90.9K_1%_0201
DIS@
DIS@ PR1808 VCC1R2VIDEO

PR1813
1/20W_0_5%_0201
PU1802 1/16W_100K_5%_0402
6

1
PR1820
74AUP1G32GF_SOT891-6_1X1 1 2 Remote Sense - 1
VCC3M

2
PR1812 DIS@ PR1823 near DC/DC @
Vcc

2 0_0201_SP PR1818 PR1825 near VRAM PR1825

[9,40] GC6_FB_EN A 1R2VIDEO_ON VCC1R2VIDEO_EN
@ PR1809 4 1 2 @ 1/16W_20K_1%_0402 1/20W_0_5%_0201

2
1 2 1 Y @
GND

[37,40,50,117] GFXCORE_D_PWRGD 1R2VIDEO_PWRGD [37]

2
5 B DIS@ PR1823

1
1/20W_0_5%_0201 NC 1/20W_0_5%_0201

1
PR1811 VCC1R2VIDEO_FB_R 1 2
3

DIS@
1/20W_100K_5%_0201

PR1810
B 0_0201_SP 2 B
1 2
[40] VCC1R0VIDEO_PWRGD
VCC5M VCC1R2VIDEO
1

DIS@ DIS@
PR1803 PR1804 VCC1R2VIDEO

2
1/16W_100K_5%_0402 1/10W_10_5%_0603 Remote Sense - 2
PR1828 near DC/DC PR1827
PR1827 near GPU 0_0201_SP
2

PR1828
0_0201_SP

1
1 2
3

D
5 DIS@
G PQ181B
6

D DIS@ UM6K33N_UMT6
VCC1R2VIDEO_EN 2 PQ181A S
4

G UM6K33N_UMT6
S
A A
1

Document Number

VCC1R2VIDEO
Size Title Rev
Custom 0.01
GL4A0/GL5A0 NM-C632
Date: Tuesday, October 13, 2020 Sheet 118 of 128
5 4 3 2 1
 5 4 3 2 1

VCC3M

1
@ PJ1902

1
JUMP_43X79
D D

2
2

VEEO
CCDC
CPPP
1:
R1
87
V
I
D
E
O
_
A
O
N
.A3
A
DIS_EMC@ 1 DIS_EMC@ 2 1

:
2:
DIS@
PC1902 PC1903 PC1904

A
2200P_25V_K_X7R_0201 0.1U_6.3V_K_X5R_0201 10U_6.3V_M_X5R_0402
2 1 2

Table PL1701

Cyntec :HMLQ25201B-R47M VCC1R8VIDEO_AON

DIS@
PD1902 DIS@
RB521CM_30 PU1901
2 1 BD9B304QWZE2_UMMP008AZ020-8-9 DIS@
[40,50] 1R8_MAIN_PWRGD
PC1905
DIS@ 1 0.1U_6.3V_K_X5R_0201
PD1901 VIN 3 1 2 DIS@
RB521CM_30 BOOT PL1901 @ PJ1901
C C
2 1 1R8VIDEO_AON_EN 2 0.47UH HMLQ25201B-R47MSR 4.7A_20% JUMP_43X79
[7,40] 1R8VIDEO_AON_ON EN 4 1 2 VCC1R8VIDEO_AONP DIS_EMC@ 1 2
SW 1 2
1
8
GND DIS_EMC_NS@

22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603

0.1U_6.3V_K_X5R_0201
1
PC1910 680P_50V_K_X7R_0402 1
5 7 2
MODE FB 2 2 2 2 DIS_EMC@
1

DIS@ PC1906

DIS@ PC1907

PC1908
DIS@ DIS@ PR1902 DIS@

E-PAD
PR1903 6 1/20W_150K_1%_0201 PC1901 PC1909
1/20W_1M_5%_0201 FREQ 2 120P_50V_J_COG_0201
2200P_25V_K_X7R_0201

2
PR1906 4.7_0603_5% 1 1 1 1

DIS_EMC_NS@
2

1
DIS@
PR1904
1/20W_120K_1%_0201

VCC5M VCC1R8VIDEO_AON

2
B B
1

DIS@ DIS@
PR1905 PR1901
1/16W_100K_5%_0402 1/10W_10_5%_0603
2

DIS@
3

PQ191B D
5
G
6

D DIS@ UM6K33N_UMT6
1R8VIDEO_AON_EN 2 PQ191A S
4

G UM6K33N_UMT6
S
1

A A

Document Number

DORAEMON
Size Title Rev
Custom 0.01
BLANK
Date: Tuesday, October 13, 2020 Sheet 119 of 128
5 4 3 2 1
 5 4 3 2 1

VEEO
CCDC
CPPP
1:
R1
06
VAA
I
D
E
O
.1
::
.
9A
3
@ PJ2001
JUMP_43X79
D 1 2 DIS_EMC@ D
VCC3M 1 2
1 1 1
PC2001 PC2003 Table PL1901
0.1U_6.3V_K_X5R_0201 10U_6.3V_M_X5R_0402
DIS@
DIS_EMC@ 2 2 2
Cyntec :HMLQ25201B-R47M VCC1R0VIDEO
DIS@
PC2002 PU2001
2200P_25V_K_X7R_0201 BD9B304QWZE2_UMMP008AZ020-8-9 DIS@
PC2004
1 0.1U_6.3V_K_X5R_0201
PR2005 VIN 3 1 2 DIS@
0_0201_SP BOOT PL2001 @ PJ2002
1 2 2 0.47UH HMLQ25201B-R47MSR 4.7A_20% JUMP_43X79
[40] 1R0VIDEO_EN EN 4 1 2 DIS_EMC@ 1 2
SW 1 2
1
DIS_EMC_NS@

2200P_25V_K_X7R_0201
22U_6.3V_M_X5R_0603

22U_6.3V_M_X5R_0603
1 8 PC2011
@ PC2005 GND 680P_50V_K_X7R_0402

1
0.1U_6.3V_K_X5R_0201 DIS@ DIS@
5 7 2 PR2002
1
PC2006 1 1 1 1
DIS_EMC@
MODE FB

2
2

DIS@ PC2007

DIS@ PC2008

PC2009
1/20W_75K_1%_0201 100P_25V_J_NPO_0201 PC2010

E-PAD
6 0.1U_6.3V_K_X5R_0201
FREQ DIS_EMC_NS@ 2

2
C
PR2006 4.7_0603_5% 2 2 2 2 C

1
DIS@
PR2001
1/20W_300K_1%_0201

2
VCC5M VCC1R0VIDEO
1

DIS@ DIS@
PR2003 PR2004
B 1/16W_100K_5%_0402 1/10W_10_5%_0603 B
2

2
3

D
5 DIS@
G PQ201B
6

D UM6K33N_UMT6
1R0VIDEO_EN 2 DIS@ S
4

G PQ201A
UM6K33N_UMT6
S
1

A A

Document Number

DORAEMON
Size Title Rev
Custom 0.01
BLANK
Date: Tuesday, October 13, 2020 Sheet 120 of 128
5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 121 of 130

5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 122 of 130

5 4 3 2 1
 5 4 3 2 1

[3,6,7,8,10,13,16,21,37,40,50,51,72,93,98,117,124] VCC3_SUS VCC3_SUS

[6,16] VCC1R05_OUT_FET VCC1R05_OUT_FET

[6,13,14,108] VCCST VCCST

VCC3_SUS VCC3_SUS

[6,14] VCCSTG VCCSTG

D D

1
R12301 R12302
1/20W_10K_5%_0201 1/20W_10K_5%_0201 VCC1R05_OUT_FET VCCST

2
VCCST_OVERRIDE_Q D12301 2 1 RB521CM-30T2R_VMN2M-2

3
Q12302

Q12301_3 1 LSK3541G1ET2L_VMT3

2
3
Q12301

1
1 LSK3541G1ET2L_VMT3 C12301 U12301
[13] VCCST_OVERRIDE

2
TPS22971YZPT_DSBGA8
1

10U_6.3V_M_X5R_0402 A2 A1
R12303 2 VIN1 VOUT1
1/20W_100K_5%_0201 B2 B1
VIN2 VOUT2
C2 C1 1
2

CT PG C12302
D12302 2 1 RB521CM-30T2R_VMN2M-2 U12301_D2 D2 D1
[13] -PCH_SLP_S3 ON GND 0.1U_25V_K_X5R_0201
2
C C
D12305 2 1 RB521CM-30T2R_VMN2M-2
[13,106,107] -PCH_SLP_S4

1
R12304
1/20W_100K_5%_0201

2
VCC3M VCC1R05_OUT_FET VCCSTG
Slew Rate=10uS<TR<65us T_on<65us

1
R12305
@
2 1/16W_10K_5%_0402

U12302
B B
TPS22971YZPT_DSBGA8
D12303 A2 A1
RB521CM-30T2R_VMN2M-2 VIN1 VOUT1
VCCST_OVERRIDE_Q 2 1 B2 B1
VIN2 VOUT2
C2 C1
CT PG
U12302_D2 D2 D1
ON GND

D12304
SA00008GZ00
RB521CM-30T2R_VMN2M-2
2 1
[13] -CPU_C10_GATE
1

1 1
R12306
1/20W_100K_5%_0201 C12303 C12304
10U_6.3V_M_X5R_0402 0.1U_6.3V_K_X7R_0402
2 2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 LOADSW VCCST&VCCSTG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 123 of 130

5 4 3 2 1
 5 4 3 2 1

D D

VCC3M VCC3_SUS
C C

R12401 1 2 0_0805_SP

B B

A A
Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 LOAD SW PCH SUS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 124 of 130

5 4 3 2 1
 5 4 3 2 1

[64] VCC3B_SSD VCC3B_SSD

SSD VCC3M

1/16W_10K_5%_0402
2
R12501
@

1
@
B_ON D12501 1 2 VCC3B_SSD_ON
[52,72,78,86,106,127] B_ON
D D
@ RB521CM-30T2R_VMN2M-2
D12502 1 2
[9] SSD_ON
RB521CM-30T2R_VMN2M-2

VCC3M

VCC3B_SSD

1
W= 120 mil
C12501
1U_25V_K_X5R_0402 U12501
2 1 14 VCC3B_SSD
@ IN1_1 OUT1_2
2 13
IN1_2 OUT1_1
VCC3B_SSD_ON R12502 1 2 0_0201_SP VCC3B_SSD_ON_R 3 12 C12503 1 2 1000P_25V_K_X7R_0201
EN1 CT1
1
VCC5M 4 11 @
VBIAS GND C12506
VCC3M 5 10 C12504 1 2 1000P_25V_K_X7R_0201 0.1U_25V_K_X5R_0201
EN2 CT2 2
@
6 9 VCC3B_SSD @
7 IN2_1 OUT2_2 8
IN2_2 OUT2_1
1
15
Thermal Pad C12505
1 0.1U_25V_K_X5R_0201
G2898KD1U_TDFN14P_2X3 2
@
C12502 SA00008F400
1U_25V_K_X5R_0402 @
2
@

C C

TABLE of POWER SWITCH (U12501)

Vendor LCFC P/N Description
GMT SA00008F400 S IC G2898KD1U TDFN 14P LOAD SWITCH

[96] VCC5B_HDD VCC5B_HDD

HDD

B B
VCC5M

VCC5B_HDD

1
W= 120 mil
C12507
1U_25V_K_X5R_0402 U12502
2 1 14 VCC5B_HDD_R R12506 1 2 0_0805_SP
2 IN1_1 OUT1_2 13
IN1_2 OUT1_1 1
VCC3B_SSD_ON R12505 1 2 0_0201_SP VCC5B_HDD_ON_R 3 12 C12509 1 2 1000P_25V_K_X7R_0201 C12511
EN1 CT1 0.1U_25V_K_X5R_0201
4 11 2
VCC5M VBIAS GND
VCC3M 5 10 C12510 1 2 1000P_25V_K_X7R_0201
EN2 CT2
6 9 VCC3B_HDD_R
7 IN2_1 OUT2_2 8
IN2_2 OUT2_1 VCC3B_HDD
15
Thermal Pad
1 G2898KD1U_TDFN14P_2X3 R12507 1 2 0_0805_SP

C12508 SA00008F400 1
1U_25V_K_X5R_0402
2 C12512
0.1U_25V_K_X5R_0201
2

A
TABLE of POWER SWITCH (U12502) A

Vendor LCFC P/N Description

GMT SA00008F400 S IC G2898KD1U TDFN 14P LOAD SWITCH

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 LOAD SW SSD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 125 of 130

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 5 4 3 2 1

VCC3LAN VCC3LAN [62,73]

Due to solve G3 to S5 wake on lan issue
+3VALW must meet INTEL spec.
Control LAN power sequence must be stuff.
D D

For VPRO

VCC3SW VCC5M VCC3M VCC3LAN

40 mils 40 mils

D
3 1
R12601 R12602
1/20W_47K_5%_0201 1/20W_47K_5%_0201 Q12601
VPRO@ @ AO3413_SOT23-3

G
R12604

2
VPRO@

2
C -VCC3LAN_DRV1 2 1/16W_10K_5%_0402 C
VPRO@ 1

1
D
VCC3LAN_DRV R12605 1 2 0_0201_SP VCC3LAN_DRV_R2 Q12602 C12601
[86] VCC3LAN_DRV 0.01U_16V_K_X7R_0201
G 2N7002WT1G_1N_SC-70-3
S VPRO@ 2 VPRO@

3
1
SB000019400
R12606
1/16W_100K_5%_0402
VPRO@

2
20180703
R12604 0 Ohm change to 10K for inrunch current issue

B B
For NVPRO
VCC3M VCC3LAN

NVPRO@
R12603
1/8W_0_5%_0805
1 2

A
Security Classification LC Future Center Secret Data Title A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 LOAD SW LAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 126 of 130

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 5 4 3 2 1

VCC3SW VCC3SW [20,51,85,101,102,105,126]

VCC3M VCC3M [4,13,16,51,52,55,56,59,84,85,86,88,102,103,104,105,106,110,116,118,119,120,123,124,125,126,128]

VCC5M VCC5M [51,69,70,72,84,85,103,107,108,109,110,116,117,118,119,120,125,126]

VCC5B VCC5B [54,72,78,88,90,96]

VCC3B VCC3B [3,7,8,10,12,13,33,34,35,36,37,51,52,53,55,63,64,66,70,73,76,78,85,88,89,91,92,93,97,98,101]

D D

VCC5M
VCC3SW

1 1 1
R12701 1 @ 2 B_ON 1/16W_10K_5%_0402
C12702 C12703 C12704
0.1U_16V_K_X7R_0402_MURATA 0.1U_16V_K_X7R_0402_MURATA 0.1U_16V_K_X7R_0402_MURATA
2 EMC_NS@ 2 EMC_NS@ 2 EMC_NS@

1. MIRROR code, is correct????

2. After reset EC, EC control "Low", not High or Disable.

Smart Switch
C
VCC5M To VCC5B C

VCC3M To VCC3B
VCC3M VCC3B
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm
U12701 J12701
1 14 VCC3B_LS 1 2
2 VIN1_1 VOUT1_2 13 1 2
VCC5M VIN1_2 VOUT1_1 JUMP_43X118
[52,72,78,86,106,125] B_ON B_ON 3 12 C12706 1 2 100P_50V_J_NPO_0402
ON1 CT1 INSTALL_S
1
4 11 VCC5B
VBIAS GND 1
C12705
1U_6.3V_K_X5R_0402_MURATA B_ON 5 10 C12701 1 2 1000P_25V_K_X7R_0402 C12707
2 VCC5M ON2 CT2 0.1U_10V_K_X7R_0402
6 9 J12702 2
7 VIN2_1 VOUT2_2 8 VCC5B_LS 1 2
VIN2_2 VOUT2_1 1 2
1 15 JUMP_43X118 1
GPAD
B INSTALL_S B
C12708 TPS22976DPUR_WSON14P_3X2 C12709
1U_6.3V_K_X5R_0402_MURATA SA00008C900 0.1U_10V_K_X7R_0402
2 2
S IC TPS22976DPUR WSON 14P LOAD SWITCH
INSTALL_U12701_S
Notice: TPS22976DPUR is common symbol with TPS22966DPUR

TABLE of POWER SWITCH (U12701)

Vendor LCFC P/N Description
TI SA00008C900 S IC TPS22976DPUR WSON 14P LOAD SWITCH teknisi-indonesia.com
GMT SA00008F400 S IC G2898KD1U TDFN 14P LOAD SWITCH
RICHTEK SA000067200 S IC RT9740AGQW WDFN 14P LOAD SWITCH

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 LOAD SW B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 127 of 130

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 5 4 3 2 1

VCC3WLAN VCC3WLAN [8,9,66]

D D
VCC3WLAN
VCC3M W= 60 mil
R12806 1 @ 21/8W_0_5%_0805 VCC3WLAN

VCC3M
VCC3WLAN

C
W= 60 mil C

1
R12801 U12801
1/16W_10K_5%_0402 5 1 VCC3WLAN
IN OUT
2

2
GND

[85] VCC3WLAN_DRV VCC3WLAN_DRV 4 3

EN OC
G524B1T11U_SOT23-5
SA000074R00

B B
TABLE of POWER SWITCH (U12801)
Vendor LCFC P/N Description
GMT SA000074R00 S IC G524B1T11U SOT23 5P POWER SWITCH
RICHTEK SA0000AGK00 S IC RT9742NGJ5 TSOT-23-5 5P PWR SW
SILERGY SA000074P00 S IC SY6288C20AAC SOT23 5P POWER SWITCH

A A
Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 LOAD SW WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 1.0

Date: Tuesday, October 13, 2020 Sheet 128 of 130

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VRAM LAN CHIP Non-vPro CPU PCB

ZZZ1
D ZZZ2 U7301 UCPU1 UCPU1 UCPU1 UCPU1 UCPU1 UCPU1 UCPU1 UCPU1 D

X764AS01001 SA000073020 I7-TGL I5-TGL I3-TGL I7-TGL I5-TGL I3-TGL PENTIUM-TGL CELERON-TGL NM-D272
M2G@ VPRO@
PCB@
SA0000AWZ70 SA0000AY270 SA0000AY370 SA0000AWZ10 SA0000AY210 SA0000AY310 SA0000B4910 SA0000B4C30
DAZ1YQ00100
TGLI7MP@ TGLI5MP@ TGLI3MP@ TGLI7@ TGLI5@ TGLI3@ PEN@ CEL@
ZZZ3 U7301

VPRO CPU FUSE DOWN CPU

X764AS01002 SA000072Z20 UCPU1 UCPU1

S2G@ NVPRO@

ZZZ4

C I7VPRO-TGL I5VPRO-TGL C

SA0000AY110 SA0000AY010
TGLI7V@ TGLI5V@
X764BD01001
H2G@

16MB + 32MB ROM (vPro)

R2107 R2108 R2109 R2110 R2111 R2113 R2114 R2115 R2116 R2117 R9805 R9806 R9808

SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT SD00000LHYT
VPRO@ VPRO@ VPRO@ VPRO@ VPRO@ VPRO@ VPRO@ VPRO@ VPRO@ VPRO@ VPRO@ VPRO@ VPRO@
1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201 1/20W_33_5%_0201

B B

32MB ROM (non-vPro) SPI ROM

R2107 R2108 R2109 R2110 R2111 R9805 R9806 R9808 U2101 U2101

SD00000LIYT SD00000LIYT SD00000LIYT SD00000LIYT SD00000LIYT SD00000LIYT SD00000LIYT SD00000LIYT SA0000A1Q00 SA00008J400
NVPRO@ NVPRO@ NVPRO@ NVPRO@ NVPRO@ NVPRO@ NVPRO@ NVPRO@ NVPRO@ VPRO@
1/20W_56_5%_0201 1/20W_56_5%_0201 1/20W_56_5%_0201 1/20W_56_5%_0201 1/20W_56_5%_0201 1/20W_56_5%_0201 1/20W_56_5%_0201 1/20W_56_5%_0201 W25R256JVEIQ_WSON8_8X6 MX25L25673GM2I-08G_SO8

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 PLM BOM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HL4A0/HL5A0 NM-D272 0.3

Date: Tuesday, October 13, 2020 Sheet 129 of 130

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Power On Sequence - Non Deep Sx

VCCRTC
D
tPCH01 D

9ms < T
-RTCRST
M_ON
tPCH04
9ms < T
VCCPDSW_3P3 tPCH02
10ms < T< 2s
tPCH05
1us < T
MPWRG
BATLOW#
tPCH32
95ms < T
-PCH_SLP_SUS
EXT_PWR_GATE#
G3-S5
VCCPRIM_3P3
tPCH06
200us < T
VCCPRIM_1P8
VCCPCHCORE
tPCH03
VCCIN_AUX_PGD tPCH07
10ms < T< 2s

0ms < T
-RSMRST
C
tPCH18 C

90us < T
-ESPI_RESET tPCH31
105ms < T
SUS_CLK tPLT02
T < 90ms
AC_PRESENT
VCCST

PWRBTN#
SLP_A#
CL_RST#
tPLT15
SLP_LAN# T < 100ms

VCC_LANPHY
SLP_WLAN#
VCC_WLANPHY
-PCH_SLP_S5
B B

-PCH_SLP_S4
-PCH_SLP_S3
-PCH_SLP_S0
S5-S0
CPU_C10_GATE#
A_ON
VCCST
VCC2R5A
VCC1R2AP
VCCSTG
tPLT04
ALL_SYS_PWRGD 1ms < T

CPUCORE_ON
VCCCPUCORE tCPU00
2ms < T
A

VCCST_PWRGD tCPU16
A

tPCH08 0ns < T

CPUCORE_PWRGD 1ms < T
tCPU01
1ms < T
PCH_CLK_OUTPUTS
tCPU08
1ms < T
PROCOWRGD tPLT05
No limit
BPWRG
tPCH23
SUS_STAT# 60us < T
tPCH33
PLTRST# 99ms < T Title
<Title>

Size Document Number Rev

E HL4A0/HL5A0 NM-D271 <RevCode>

Date: Tuesday, October 13, 2020 Sheet 130 of 130

5 4 3 2 1