CMOS Transistor and

Circuits

1
 Outline
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 DC characteristics and transfer function
 Noise margin
 Latchup
 Pass transistors
 Tristate inverter

Jan 2015 CMOS Transistor 2

 MOSFET as a switch

Jan 2015 CMOS Transistor 3

 MOS Symbols

Jan 2015 CMOS Transistor 4

 Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) → Dt = (C/I) DV
– Capacitance and current determine speed
 Also explore what a “degraded level” really means

Jan 2015 CMOS Transistor 5

 MOS Capacitor
 Gate and body form MOS capacitor
 Operating modes Vg < 0
polysilicon gate
silicon dioxide insulator
+
– Accumulation - p-type body

(a)

0 < V g < Vt

– Depletion
depletion region
+
-

(b)

V g > Vt

– Inversion +
-
inversion region
depletion region

(c)

Jan 2015 CMOS Transistor 6

 Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs Vg

– Vgs = Vg – Vs Vgs
+ +
Vgd
– Vgd = Vg – Vd - -

– Vds = Vd – Vs = Vgs - Vgd Vs

-
Vds +
Vd

 Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation

Jan 2015 CMOS Transistor 7

 nMOS Cutoff
 No channel
 Ids = 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

Jan 2015 CMOS Transistor 8

 nMOS Linear
 Channel forms Vgs > Vt
Vgd = Vgs
+ g +
- -
s
 Current flows from d to s
d
n+ n+ Vds = 0

– e- from s to d p-type body

b

 Ids increases with Vds Vgs > Vt

+ g +
Vgs > Vgd > Vt

- - Ids
s d

 Similar to linear resistor

n+ n+
0 < Vds < Vgs-Vt
p-type body
b

Jan 2015 CMOS Transistor 9

 nMOS Saturation
 Channel pinches off Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
 Ids independent of Vds b

 We say current saturates

 Similar to current source

Jan 2015 CMOS Transistor 10

 I-V Characteristics
 In Linear region, Ids depends on:

– How much charge is in the channel

– How fast is the charge moving

Jan 2015 CMOS Transistor 11

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = eoxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt (Vgc – Vt is the amount of
voltage attracting charge to channel beyond the voltage required for inversion )

gate
Vg
polysilicon + +
gate
W
source Vgs Cg Vgd drain
Vs - - Vd
tox
channel
n+ - + n+
L SiO2 gate oxide Vds
n+ n+ (good insulator, eox = 3.9) p-type body
p-type body

Jan 2015 CMOS Transistor 12

 Carrier velocity
 Charge is carried by e-

 Carrier velocity v proportional to lateral E-field

between source and drain

 v = mE m called mobility

 E = Vds/L

 Time for carrier to cross channel:

– t=L/v

Jan 2015 CMOS Transistor 13

 nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
 mCox
W V  V  Vds V
 gs t  ds
L  2 
W
  Vgs  Vt  ds Vds  = mCox
V
 2 L

Jan 2015 CMOS Transistor 14

 nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt

 Now drain voltage no longer increases current

I ds   Vgs  Vt  dsat V
V
 dsat
 2 

  Vt 
2
 Vgs
2

Jan 2015 CMOS Transistor 15

 nMOS I-V Summary
 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

Jan 2015 CMOS Transistor 16

 Example
 We will be using a 0.18 mm process for your project
– tox = 40 Å
– m = 180 cm2/V*s
– Vt = 0.4 V
 Plot Ids vs. Vds
– Vgs = 0, 0.3, 0.6, 0.9, 1.2, 1.5 and 1.8V.
– Use W/L = 4/2 l

W  3.9  8.85 1014   W  W

  mCox   350   8    155 m A / V 2

L  100  10  L  L

Jan 2015 CMOS Transistor 17

Jan 2015 CMOS Transistor 18
 pMOS I-V

 All doping and voltages are inverted for pMOS

 Mobility mp is determined by holes

– Typically 2-3x lower than that of electrons mn

 Thus pMOS must be wider to provide same current

– In this class, assume mn / mp = 2

Jan 2015 CMOS Transistor 19

Jan 2015 CMOS Transistor 20
 DC Transfer Characteristics

Objective: Find the variation of

output voltage Vout for changes in
input voltage Vin.

Vtp – Threshold voltage of p-device

Vtn – Threshold voltage of n-device

Jan 2015 CMOS Transistor 21

Jan 2015 CMOS Transistor 22
 Recall CMOS device

CMOS inverter characteristics is

derived by solving for Vinn=Vinp and
Idsn=-Idsp

Jan 2015 CMOS Transistor 23

 CMOS inverter is divided into five regions of operation

Jan 2015 CMOS Transistor 24

Jan 2015 CMOS Transistor 25
Jan 2015 CMOS Transistor 26
Jan 2015 CMOS Transistor 27
Jan 2015 CMOS Transistor 28
 I-V Characteristics
 Make pMOS is wider than nMOS such that n = p
Vgsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

Jan 2015 CMOS Transistor 29

 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

Jan 2015 CMOS Transistor 30

 Load Line Analysis
 For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

Jan 2015 CMOS Transistor 31

 Load Line Summary

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

Jan 2015 CMOS Transistor 32

 DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot

VDD
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3 Vin2 D
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

Jan 2015 CMOS Transistor 33

 Operating Regions
 Revisit transistor operating regions

Region nMOS pMOS VDD

A B
A Cutoff Linear
Vout
B Saturation Linear C
C Saturation Saturation
D Linear Saturation D
E
0
E Linear Cutoff Vtn VDD/2 VDD+Vtp
VDD
Vin

Jan 2015 CMOS Transistor 34

 Beta Ratio
 If p / n  1, switching point will move from VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
p
 10
n
Vout 2
1
0.5
p
 0.1
n

0
VDD
Vin

Jan 2015 CMOS Transistor 35

 DC Transfer function is symmetric for βn=βp

Jan 2015 CMOS Transistor 36

Jan 2015 CMOS Transistor 37
 Noise Margin
It determines the allowable noise at the input gate (0/1)
so the output (1/0) is not affected

Noise margin is closely related to input-output transfer

function

It is derived by driving two inverters connected in series

Jan 2015 CMOS Transistor 38

Jan 2015 CMOS Transistor 39
Jan 2015 CMOS Transistor 40
Jan 2015 CMOS Transistor 41
 Impact of skewing transistor size on noise margin

Increasing (decreasing) P / N ratio increases (decreases) the low

noise margin and decreases (increases) the high noise margin

Jan 2015 CMOS Transistor 42

 Latchup in CMOS Circuits

Jan 2015 CMOS Transistor 43

 Latchup refers to short circuit formed between power and
ground rails in an IC leading to high current and damage
to the IC. Speaking about CMOS transistors, latch up is
the phenomenon of low impedance path between power
rail and ground rail due to interaction between parasitic
pnp and npn transistors

Jan 2015 CMOS Transistor 44

 Parasitic bipolar transistors are formed by substrate and
source / drain devices

Latchup occurs by establishing a low-resistance paths

connecting VDD to VSS
Latchup may be induced by power supply glitches or
incident radiation

If sufficiently large substrate current flows, VBE of NPN

device increases, and its collector current grows.

This increases the current through RWELL. VBE of PNP

device increases, further increasing substrate current.

Jan 2015 CMOS Transistor 45

Jan 2015 CMOS Transistor 46
 If bipolar transistors satisfy βPNP x βNPN > 1, latchup
may occur.

Operation voltage of CMOS circuits should be below

Vlatchup.

Remedies of latchup problem:

1. Reduce Rsubstrate by increasing P doping of substrate

by process control.
2. Reducing RWELL and resistance of WELL contacts by
process control.
3. Layout techniques: separation of P and N devices,
guard rings, many WELL contacts (at design).
Jan 2015 CMOS Transistor 47
 Pass Transistors
 We have assumed source is grounded
 What if source > 0? VDD
– e.g. pass transistor passing VDD VDD
 Vg = VDD
– If Vs > VDD-Vt => Vgs < Vt
– Hence transistor would turn itself off
 nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
 pMOS pass transistors pull no lower than Vtp

Jan 2015 CMOS Transistor 48

 Pass Transistor CKTs

As the source can rise to within a threshold voltage of the gate, the
output of several transistors in series is no more degraded than that
of a single transistor.

Jan 2015 CMOS Transistor 49

 Transmission Gates
 Single pass transistors produce degraded outputs
 Complementary Transmission gates pass both 0
and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

Jan 2015 CMOS Transistor 50

 Transmission gate ON resistance as input voltage
sweeps from 0 to 1(VSS to VDD), assuming that output
follows closely.

Jan 2015 CMOS Transistor 51

 Tristates
 Tristate buffer produces Z when not enabled

EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y

EN

Jan 2015 CMOS Transistor 52

 Nonrestoring Tristate
 Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y

EN

A Y

EN
Jan 2015 CMOS Transistor 53
 Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

Jan 2015 CMOS Transistor 54

 Multiplexers
 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1

Jan 2015 CMOS Transistor 55

 Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2

Jan 2015 CMOS Transistor 56

 Transmission Gate Mux
 Nonrestoring mux uses two transmission gates
– Only 4 transistors
S

D0
S Y
D1

Jan 2015 CMOS Transistor 57

 Inverting Mux
 Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
 Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

Jan 2015 CMOS Transistor 58

 4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

Jan 2015 CMOS Transistor 59

 Sizing for Performance
Cint NMOS and PMOS diffusion + diffusion-gate overlap.
Cext Fan-out (input gates) + interconnects.
Req Equivalent gate resistance.
CL  Cint  Cext Capacitive load of an inverter.
Cint  SCiref Req  Rref S S sizing factor.
 Cext 
Propagation delay: tp  0.69 Req  Cint  Cext   tp0 1  
 SCint 

tp0  0.69 ReqCint Inverter delay loaded only by intrinsic.

Jan 2015 CMOS Transistor 60

Cint   Cg Intrinsic cap to gate cap ratio ≈1.

f  Cext Cg Effective fan-out.

The delay of an inverter

 Cext   f  is only a function of the
tp  tp0  1  
 p0 
t 1  
  Cg    ratio between its external
 
load cap to its input cap
In Out
Cg1 1 2 N CL

 Cg 
tp   
N N
t t 1  j 1  , Cg N 1  CL
j 1 p j j 1 p0   Cg 
 j 

Jan 2015 CMOS Transistor 61

 tp Cg j 1 Cg j
 0, 1  j  N  1 imply   f , 2  j  N 1
Cg j Cg j Cg j 1

It implies that same sizing factor f is used for all stages.

The optimal size of an inverter is the Cg j  Cg j 1 Cg j 1
geometric mean of its neighbor drives

Given Cg1 and CL , and F  CL Cg the

optimal sizing factor is
1 f NF

The minimum delay through the  NF

tp  Ntp0 1  
chain is   

Jan 2015 CMOS Transistor 62

 What should be the optimal N ?
N
F ln F
The derivative by N of tp yields  N F  0
N

or equivalently f  e1 f  having a closed form solution

f  e only for γ=0, a case where the intrinsic self load is

ignored and only the fan-out is considered.

Jan 2015 CMOS Transistor 63