LOGICS CIRCUITS AND SWITCHING THEORY

EXPERIMENT 1

SUBMITTED TO THE FACULTY,

DEPARTMENT OF ELECTRONICS ENGINEERING,
SCHOOL OF ENGINEERING AND ARCHITECTURE,
UNIVERSITY OF THE CORDILLERAS

IN PARTIAL FULFILLMENT OF
THE COURSE, LOGIC CIRCUITS AND SWITCHING THEORY

SUBMITTED BY:
Emperador, Janssen Bryan G.

SCHEDULE:
SATURDAY 12:50 PM – 4:50 PM

SUBMITTED TO:
ENGR. KHENNETH GEOFFREY PAGADUAN

DATE:
MAY 18, 2024
I. Discussion of Theory

a. Input and Output Characteristics of Logic Gates

Logic 0 and Logic 1 are a range of voltage values, not just a single voltage and
zero volts respectively. The following are the range values of gates that is
powered with 5V.

The range of logic 1 input signals

are from 3.5V to 5V, with logic 0
being a range from 0 to 1.5V.

The acceptable range of output

signals are then 4.95V to 5V for
logic 1 and 0V to 0.05V for logic
0. Figure 1, Input and Output Characteristics of TTL

Notice there is a unhighlighted part of the graph, this is normally known as the
undefined region of the logic gate, logic gates cannot operate within this rage.

There is also a voltage tolerance

for TTL based gates.
Acceptable TTL signals are as
follows in figure 1. Logic 1 like said
before, is a range of values, in
this case is a range from 2V to 5V,
with logic 0 having a range of 0V
to 0.8 V. Figure 1a, Input and Output Characteristics of CMOS

Consequently, TTL outputs are

2.7V to 5V for logic 1 and
between 0V and 0.5V for logic 0.

The amount of difference between the range from the input and the output are
called the noise margins. CMOS has a higher noise margin than TTL, it will further
increase as the source voltage increases.

Noise margins refer to the amount of noise a gate can tolerate without its output
being misinterpreted or distorted, a higher noise margin is typically more
preferable.

b. TTL vs CMOS
CMOS is short for “Complementary Metal Oxide Semiconductor” and it is the
most common MOSFET fabrication type, while TTL is short for “Transistor-transistor
logic”, it instead uses bipolar junction transistors.
CMOS TTL
More costly than TTL, but
becomes cheaper at higher
Cost Less expensive than CMOS
numbers, CMOS based gates
are also smaller in size
Delay 20 to 50 nanoseconds 10 nanoseconds
Output
Normally 50 under operation 10
Connections
 Input
10 Inputs 12-14 Inputs
Connections
Noise
Better noise immunity Lower Noise Immunity
Immunity
Design Simpler design with MOSFETs More complex design with BJTs
Table 1, CMOS vs TTL

Using the table above, we can see that CMOS has an advantage of having a
higher number of outputs, better noise immunity and simpler design. Though TTL
leads with delay and input connections.

As said before, CMOS has better noise immunity because of its higher noise-
margins, and this noise immunity increases as the source voltage becomes
higher. Nonetheless, the type of application will determine the type of system
being used.

c. Basic Logic Gates

1. OR Gates
A B A+B An OR gate exhibits the characteristic of
outputting a logic 1 if and only if one of the
0 0 0
inputs is a logic 1 or both inputs is a logic 1.
0 1 1 The Boolean expression of an OR Gate uses an
1 0 0 addition sign.
1 1 1

Figure 2, OR Gate
2. AND Gates

A B A*B As the name implies, an AND gate will only

0 0 0 output a logic 1 if both inputs are also a logic 1.
In Boolean algebra, it is represented either by a
0 1 0
period or the absence of an operation, e.g.
1 0 0
(A*B) or (AB)
1 1 1

Figure 2a, AND Gate

3. NOT Gates
A A̅ A NOT gate, or an INVERTER, exhibits the characteristic of
0 1 outputting the opposite of its input. In Boolean algebra, it
1 0 is represented by the output having a bar.

Figure 2b, NOT Gate

4. NOR Gates
 A B A̅ ̅+̅ ̅B̅ A NOR gate (NOT OR), as the name suggests is
the opposite of OR. The gate outputs a logic 1
0 0 1
only if both inputs are a logic 0. In Boolean
0 1 0
algebra it is represented by a bar over the
1 0 0
output, X̅ ̅+̅ ̅Y̅.
1 1 0

The symbol is represented with having a circle at the output.

Figure 2c, NOR Gate

5. NAND Gates

A B A̅ ̅*̅ ̅B̅ a NAND gate (NOT AND), is an opposite of an

0 0 1 AND gate as the name suggests. It outputs a
logic 0 with both inputs being a logic 1. It is
0 1 1
represented by a bar over the output, X̅ ̅*̅ ̅Y̅.
1 0 1
1 1 0

It is again represented with a symbol having a circle at the output.

Figure 2c, NAND Gate

6. XOR Gates

A B A̅ ̅*̅ ̅B̅ an XOR gate (Exclusively-OR), is a “stricter”

0 0 0 version of an OR gate, it only outputs a logic 1 if
only one of the inputs are a logic 1. It is
0 1 1
represented by an addition sign with a circle,
1 0 1
X⊕Y.
1 1 0

It is represented by having a line in the input side of the symbol.

Figure 2d, XOR Gate

II. Data and Results

Using the block in the KL-300 for all the following measurements, while at the same time using
the respective logic gates required for each letter.
 Figure 3, Block D KL-300

a. AND Gate Characteristics Measurement

AND GATE Using a truth table, an AND gate exhibits a
INPUT OUTPUT characteristic of outputting a logic 1, if and
STATE only if both inputs are also logic 1.
A2 A1 F3
0 0 0 0
1 0 1 0
2 1 0 0
3 1 1 1

By Connecting A2 to the 10Hz TTL level output of the Clock Generator, the following data was
gathered.

A1 = 0 A1 = 1
A2 A2
I
N
P
U
T

O
F1 F1
U
T
P
U
T

At A1 = 0, F2 is constantly a logic 0, though at A 1= 1, F2 is equal to A1, since for F2 to output a

logic 1, both inputs need to be turned on.
 A1 = 1 Hz
A2

I
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T

F1
O
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P
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T

At A1 = 1 Hz, on time increases and decreases as signals are out of sync, for reference, the turn
off and on pulse of A1 should be every second and the turn off and on pulse of a 10 Hz square
wave should be 100ms.
If the signals were at sync, F1 would output a logic 0 from 0s to 500ms and will be equal to A2
from 500ms to 1s.

b. OR Gate Characteristics Measurement

OR GATE Using a truth table, an OR gate exhibits an
INPUT OUTPUT output of logic 1, if and only if one or both of
STATE the inputs are logic 1.
A4 A3 F4
0 0 0 0
1 0 1 1
2 1 0 1
3 1 1 1

A3 = 0 A3 = 1
A4 A4
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O
F4 F4
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At A3 = 0, F4 is equal to A4, although at A3 = 1, F4 is constantly outputting a logic 1 since A3 is

always on, the on and off pulse of the square wave will have no effect.
A3 = 1 Hz
A4

I
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F4
O
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T

AT A3 = 1 Hz, the off time increases & decreases since the signals are out of sync, with the
oscilloscope showing the lowest off time to be 100 microseconds. If the two signals were at
sync, the output would constantly be at logic 1.

c. INVERTER Gate Characteristics Measurement

C1 F6/C2 An INVERTER gate or a NOT gate, as the

0 0 1 name suggests inverts the input. A logic 1
1 1 0 input will output a logic 0 and vice versa.

C2/F6 F7 Using two INVERTERs will essentially cancel

0 0 1 the input being inverted, and in this case C1
will be exactly equal to F7.
1 1 0
 d. NAND Gate Characteristics Measurement
e.
NAND GATE Using a truth table, a NAND Gate, or a “NOT
INPUT OUTPUT AND” gate, will output a logic 1 if and only if
STATE both inputs are NOT logic 1.
A2 A1 F1
0 0 0 1
1 A NAND gate will be the opposite of an AND
1 0 1
gate.
2 1 0 1
3 1 1 0

A1 = 0 A1 = 1
A2 A2
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O
F1 F1
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At A1 = 0, the system will always output a logic 1, in this case the system becomes F1 = A1. At
A1 =1 The output will be inverted because of the inherent characteristic of a NAND gate
outputting a logic 0 when both inputs are logic 1. In this configuration, a NAND gate behaves
exactly the same as an INVERTER.

A1 = 1 Hz
A2

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O F1
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At A1 = 1Hz, the oscilloscope displays that the off time decreases and increases but will never
be bigger than on time, however in this situation, the two input signals are not in sync.

If the two signals were at sync, the waveform would be as follows:

An inverted signal from 0 to 500ms and a constant logic 1 from 500ms to 1s, this signal will repeat
indefinitely until the system is tampered.

f. NOR Gate Characteristics Measurement

INPUT OUTPUT
STATE Using a truth table, a NOR (NOT OR) gate, will
A4 A3 F2 behave exactly the opposite of an OR gate.
0 0 0 1 The gate will output a logic 1 if and only if
1 0 1 0 both inputs are logic 0.
2 1 0 0
3 1 1 0

A3 = 0 A3 = 1
A4 A4
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O
F2 F2
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At A3 = 0, the system will output a waveform similar to the input, A3 = F2. At A3 = 1 the output
will always be at logic 0 because of the characteristic of a NOR gate to only output a 1 if all
inputs are logic 0.

A3 = 1 Hz
A4

I
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 F2
O
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At A3 = 1Hz, an oscilloscope had an output with the following characteristics:

Because the signals are out of sync, on time decreases and then increases, but on time will
never be more than off time.

If both were in sync, the output waveform would have a characteristic of:
Being the inverted from 0 to 500ms then a constant logic 0 from 500ms to 1s.
g. XOR Gate Characteristics

INPUT OUTPUT
STATE A XOR Gate, or an “Exclusively OR” Gate, will
C5 C4 F9 have the inherent characteristic of
0 0 0 0 outputting a 1 if and only if one input is logic
1 0 1 1 0. In simpler terms, it’s a “stricter” version of
an OR Gate.
2 1 0 1
3 1 1 0

C5 = 0 C5 = 1
C4 C4
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O
F9 F9
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When C5 = 0, the system will output a waveform exactly life C4, in this case C4 = F9. At C5 = 1,
the system will output an inverted waveform, at which case the system will behave like an
INVERTER.
 C5 = 1 Hz
C4

I
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F9
O
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Because the signals are not at sync, the on time & off time creases and increases in turns.
However, if they were at sync, the output would be:
A2 = F9 at 0 to 500ms then an inverted waveform, A̅2̅ = F9, from 500ms to 1s.
III. Answers to Questions

F (1) TRUTH TABLE F (2) TRUTH TABLE

A B A+B A Ā B Ā+B
0 0 0 0 1 0 1
0 1 1
0 1 1 1
1 0 1
1 1 1 1 0 0 0
1 0 1 1

Using these truth tables, its safe to deduct that these two logic systems are the same.
Though using F (2) would most likely be less efficient and slower than F (1) because of the
increased number of operations.
MULTIPLE CHOICE QUESTIONS
( )1. Fig. (a) is a ( )6. Fig (d). is a

1. AND gate 1. NOT gate

2. OR gate 2. BUFFER
3. NOT gate 3. NAND gate

( )2. What logic function does the circle a ( )7. In Fig. (e), F represents:

t the output of Fig. (c) represent? 1. A+B

2. AB
1. NOT gate
3. A⊕B
2. AND gate
3. OR gate
( )8. In Fig. (b), if B is to represent “0” when the

( )3. The corresponding input/output values circuit is open, a resistor should be connected

of a logic gate is called: from B to:

1. Trigger table 1. Ground

2. Truth Table 2. Supply Voltage
3. Specification Table 3. A

( )9. Fig. (d) is a

( )4. Fig. (c) is a
1. Note Gate
1. AND gate
2. NAND Gate
2. NOR gate
3. AND Gate
3. NAND gate

( )5. Which figure represents an OR gate? ( )10. If A=0 for the circuit of Fig. (a) then the
output F is:
1. Figure (a)
2. Figure (b) 1. 0
3. Figure (c) 2. 1
3. B
 IV. Observations

It is almost impossible to manually sync a 1hz and a 10hz square wave signal so
that at 0s, the signals will be at their off segment. In this case, almost all the output
signals that had these two input signals were out of sync, leading to some very unique
output signals.

Additionally, one cycle of the TTL clock was observed to be 250ms using an
oscilloscope, only making it 4
hertz. Further adjustments were needed and a complete restart of some of the
data measurements.

Finally, seeing as all the laboratory equipment are older than some of the students,
its only normal to see some of them malfunctioning. Our group had the trouble of the
first input not working and the source voltage only having a logic one of only 400mV,
with the second group having the trouble of their KL-300 logic board malfunctioning
at times.

V. Conclusion

Understanding the fundamental concepts of basic logic gates, like its

acceptable voltage ranges, its inherent characteristics, and the important
differences between CMOS and TTL, like how CMOS based logic gates are more
expensive than TLL based ones but are more economical for larger and more
complex systems, is essential for the understanding of more advanced Boolean
mathematics using logic gates.

Understanding different logic gates, such as the AND, OR, NOT, and their
counterparts will provide a deep grasp in their symbols, predicting their outputs based
on different input combinations, and in the end, be able to design, simplify, and
decipher more complex logic circuits.

VI. References

Logic Signal Voltage Levels. (n.d.). www.allaboutcircuits.com.

https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels

TTL vs. CMOS: Integrated circuit logic families. (n.d.). PCB Assembly,PCB Manufacturing,PCB design -
OURPCB. https://www.ourpcb.com/ttl-vs-cmos.html

Basic logic gates. (2019, October 21). BYJUS. https://byjus.com/jee/basic-logic-gates/