Brent-Kung adder
• Simplified representations of
parts a and c.
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Brent-Kung adder
• The lookahead logic for
an 8-bit adder. The inputs
0-7 are the propagate and
carry terms formed from
the inputs to the adder.
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Brent-Kung adder
• An 8-bit Brent-Kung CLA. The
outputs of the lookahead logic are
the carry bits that (together with the
inputs) form the sum.
• One advantage of this adder is that
delays from the inputs to the outputs
are more nearly equal than in other
adders. This tends to reduce the
number of unwanted and
unnecessary switching events and
thus reduces power dissipation.
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carry-select adder
• we duplicate two small adders (usually 4-bit or 8-bit adders-
often CLAs) for the cases CIN = '0' and ClN = ‘1' and then
use a MUX to select the case that we need - wasteful but
fast.
• A carry-select adder is often used as the fast adder in a
Datapath Library because its layout is regular.
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Conditional-sum Adder (CSA)
• An n-bit adder that generates two sums
• One sum assumes a carry-in condition of '0'.
• The other sum assumes a carry-in condition of’ 1’.
• Can split this n-bit adder into an i-bit adder for the i LSBs and an (n-i) -bit
adder for the (n-i) MSBs.
• Both adders generate two conditional sums as well as true and complement
carry signals.
• The two (true and complement ) carry signals from the LSB adder are used to
select between the two conditional sums from the MSB adder using two-
input MUXes.
• Example: we can split a 16-bit adder using i = 8 and n = 8: then we can split one or
both 8-bit adders again and so on
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Conditional-sum Adder (CSA)
• The simplest form
of an n-bit CSA that
uses n single-bit
conditional adders,
H (each with four
outputs; two
conditional sums,
true carry and
complementary
carry), together
with a tree of 2:1
MUXes (Qi_j).
9/4/20XX Presentation Title 48
Conditional-sum Adder (CSA)
(a) A 1-bit conditional adder that calculates the (b) The multiplexer that selects between sums
sum and carry out assuming the carry-in is either '1' or '0' and carries
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Conditional-sum Adder (CSA)
(c) A 4-bit conditional-sum adder
with carry input, C[0]
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Conditional-sum Adder (CSA)
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FIGURE 2.26: Datapath adders. This data is from a series of submicron datapath libraries. (a) Delay normalized to a two-input
NAND logic cell delay (approximately equal to 250 ps in a 0.5μm process). For example, a 64-bit ripple-carry adder (RCA) has a
delay of approximately 30 ns in a 0.5 μm process. The spread in delay is due to variations in delays between different inputs and
outputs. An n-bit RCA has a delay proportional to n. The delay of an n-bit carry select adder is approximately proportional to log2n.
The carry-save adder delay is constant (but requires a carry-propagate adder to complete an addition). (b) In a datapath library the
area of all adders are proportional to the bit size.
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Multipliers
a symmetric 6-bit array multiplier (an n-bit multiplier multiplies two
n-bit numbers; we shall use n-bit by m-bit multiplier if the lengths
are different).
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Multipliers
• Adders a0-f0 may be
eliminated, which then
eliminates adders a a0-a6.
leaving an asymmetric CSA
array of 30 (5 x 6) adders
(including one half adder).
• An n-bit array multiplier has
a delay proportional to n
plus the delay of the CPA
(adders b6-f6 in Figure
2_27).
• There are two items we can
attack to improve the
performance of a multiplier:
the number of partial
products and the addition of
the partial
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Multipliers
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Multipliers
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