TLV9001, TLV9002, TLV9004

SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021

TLV900x Low-Power, RRIO, 1-MHz Operational Amplifier for Cost-Sensitive Systems

The TLV900x devices include a shutdown mode
1 Features (TLV9001S, TLV9002S, and TLV9004S) that allow the
• Scalable CMOS amplifier for low-cost applications amplifiers to switch off into standby mode with typical
• Rail-to-rail input and output current consumption less than 1 µA.
• Low input offset voltage: ±0.4 mV
Micro-size packages, such as SOT-553 and WSON,
• Unity-gain bandwidth: 1 MHz
are offered for all channel variants (single, dual, and
• Low broadband noise: 27 nV/√Hz
quad), along with industry-standard packages such as
• Low input bias current: 5 pA
SOIC, MSOP, SOT-23, and TSSOP packages.
• Low quiescent current: 60 µA/Ch
• Unity-gain stable Device Information
• Internal RFI and EMI filter PART NUMBER(1) PACKAGE BODY SIZE (NOM)
• Operational at supply voltages as low as 1.8 V SOT-23 (5) 1.60 mm × 2.90 mm
• Easier to stabilize with higher capacitive load due SC70 (5) 1.25 mm × 2.00 mm
to resistive open-loop output impedance TLV9001
SOT-553 (5)(2) 1.65 mm × 1.20 mm
• Extended temperature range: –40°C to 125°C
X2SON (5) 0.80 mm × 0.80 mm
2 Applications SOT-23 (6) 1.60 mm × 2.90 mm
TLV9001S
• Sensor signal conditioning SC70 (6) 1.25 mm × 2.00 mm
• Power modules SOIC (8) 3.91 mm × 4.90 mm
• Active filters WSON (8) 2.00 mm × 2.00 mm
• Low-side current sensing
TLV9002 VSSOP (8) 3.00 mm × 3.00 mm
• Smoke detectors
• Motion detectors SOT-23 (8) 1.60 mm × 2.90 mm
• Wearable devices TSSOP (8) 3.00 mm × 4.40 mm
• Large and small appliances VSSOP (10) 3.00 mm × 3.00 mm
• EPOS TLV9002S X2QFN (10) 1.50 mm × 2.00 mm
• Barcode scanners DSBGA (9) 1.00 mm × 1.00 mm
• Personal electronics
SOIC (14) 8.65 mm × 3.91 mm
• HVAC: heating, ventilating, and air conditioning
SOT-23 (14) 4.20 mm × 2.00 mm
• Motor control: AC induction
TLV9004 TSSOP (14) 4.40 mm × 5.00 mm
3 Description WQFN (16) 3.00 mm × 3.00 mm
The TLV900x family includes single (TLV9001), dual X2QFN (14) 2.00 mm × 2.00 mm
(TLV9002), and quad-channel (TLV9004) low-voltage TLV9004S WQFN (16) 3.00 mm × 3.00 mm
(1.8 V to 5.5 V) operational amplifiers (op amps)
with rail-to-rail input and output swing capabilities. (1) For all available packages, see the orderable addendum at
These op amps provide a cost-effective solution the end of the data sheet.
(2) Package is for preview only.
for space-constrained applications such as smoke
detectors, wearable electronics, and small appliances
where low-voltage operation and high capacitive-load
drive are required. The capacitive-load drive of the
TLV900x family is 500 pF, and the resistive open-
loop output impedance makes stabilization easier with
much higher capacitive loads. These op amps are
designed specifically for low-voltage operation (1.8 V
to 5.5 V) with performance specifications similar to the
TLV600x devices.
The robust design of the TLV900x family simplifies
circuit design. The op amps feature unity-gain
stability, an integrated RFI and EMI rejection filter, and
no-phase reversal in overdrive conditions. Single-Pole, Low-Pass Filter

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................26
2 Applications..................................................................... 1 8.4 Overload Recovery................................................... 27
3 Description.......................................................................1 8.5 Shutdown.................................................................. 27
4 Revision History.............................................................. 2 8.6 Device Functional Modes..........................................27
5 Device Comparison Table...............................................6 9 Application and Implementation.................................. 28
6 Pin Configuration and Functions...................................7 9.1 Application Information............................................. 28
7 Specifications................................................................ 14 9.2 Typical Application.................................................... 28
7.1 Absolute Maximum Ratings...................................... 14 10 Power Supply Recommendations..............................34
7.2 ESD Ratings............................................................. 14 10.1 Input and ESD Protection....................................... 34
7.3 Recommended Operating Conditions.......................14 11 Layout........................................................................... 35
7.4 Thermal Information: TLV9001................................. 15 11.1 Layout Guidelines................................................... 35
7.5 Thermal Information: TLV9001S............................... 15 11.2 Layout Example...................................................... 35
7.6 Thermal Information: TLV9002................................. 15 12 Device and Documentation Support..........................36
7.7 Thermal Information: TLV9002S............................... 16 12.1 Documentation Support.......................................... 36
7.8 Thermal Information: TLV9004................................. 16 12.2 Receiving Notification of Documentation Updates..36
7.9 Thermal Information: TLV9004S............................... 16 12.3 Support Resources................................................. 36
7.10 Electrical Characteristics.........................................17 12.4 Trademarks............................................................. 36
7.11 Typical Characteristics............................................ 19 12.5 Electrostatic Discharge Caution..............................36
8 Detailed Description......................................................25 12.6 Glossary..................................................................36
8.1 Overview................................................................... 25 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram......................................... 25 Information.................................................................... 37

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Q (June 2021) to Revision R (November 2021) Page
• Added SOT-23 (14) package to Device Information table.................................................................................. 1
• Added SOT-23 DYY package to Device Comparison Table .............................................................................. 6
• Added SOT-23 (14) package to Pin Configuration and Functions section ........................................................ 7
• Added DYY (SOT-23) package thermal information to the Thermal Information: TLV9004 table.................... 16

Changes from Revision P (April 2021) to Revision Q (June 2021) Page

• Changed supply voltage (V+) – (V–) MAX from 6 V to 7 V in the Absolute Maximum Ratings table............... 14

Changes from Revision O (April 2020) to Revision P (April 2021) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added 9-pin DSBGA package to Device Information table................................................................................ 1
• Added 9-pin DSBGA package to Device Comparison Table ............................................................................. 6
• Added TLV9002S 9-pin DSBGA package to Pin Configuration and Functions section......................................7
• Added TLV9002S 9-pin DSBGA package to Thermal Information: TLV9002S ............................................... 16
• Deleted the Related Links section from the Device and Documentation Support section................................36

Changes from Revision N (January 2020) to Revision O (April 2020) Page

• Deleted PREVIEW designation on TLV9001S ...................................................................................................1
• Deleted TLV9001SIDCK (6-pin SC70) package preview note ...........................................................................7
• Added DCK (SC70) data to the Thermal Information: TLV9001S table ...........................................................15

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Changes from Revision M (September 2019) to Revision N (January 2020) Page

• Added 6-pin SC70 package to Device Information table.................................................................................... 1
• Added 6-pin SC70 package to Device Comparison Table .................................................................................6
• Added TLV9001SIDCK (6-Pin SC70) package pinout........................................................................................7
• Added TLV9001S 6-pin SC70 package to Pin Configuration and Functions section......................................... 7
• Added 6-pin SC70 pinout to Pin Functions: TLV9001S ..................................................................................... 7
• Added TLV9001S 6-pin SC70 package to Thermal Information: TLV9001S table........................................... 15

Changes from Revision L (May 2019) to Revision M (September 2019) Page

• Deleted preview notations for SOT-23-8 (DDF) package................................................................................... 6
• Added link to Shutdown section in all SHDN pin function rows.......................................................................... 7
• Added EMI Rejection section to the Feature Description section.....................................................................26
• Changed the Shutdown section to add more clarity regarding internal pull-up resistor....................................27

Changes from Revision K (March 2019) to Revision L (May 2019) Page

• Added SOT-23 (8) information to Device Information table................................................................................ 1
• Added SOT-23 DDF package to Device Comparison Table .............................................................................. 6
• Added SOT-23 (DDF) to Pin Configuration and Functions section.....................................................................7
• Added DDF (SOT-23) Thermal Information: TLV9002 table.............................................................................15

Changes from Revision J (January 2019) to Revision K (March 2019) Page

• Changed TLV9002S ESD Ratings heading to include all TLV9002S packages............................................... 14
• Deleted preview notation from TLV9002SIRUG in Thermal Information table................................................. 16

Changes from Revision I (November 2018) to Revision J (January 2019) Page

• Deleted preview notation for TLV9002SIRUGR..................................................................................................1
• Changed TLV9004 WQFN(14) package designator to X2QFN(14) package designator................................... 1
• Added RUG package to Device Comparison Table ...........................................................................................6
• Added DGS package to Device Comparison Table ........................................................................................... 6
• Added shutdown devices to Device Comparison Table .....................................................................................6
• Changed TLV9001 DRL package pinout drawing...............................................................................................7
• Changed TLV9001 DRL package pin functions..................................................................................................7
• Deleted package preview note from TLV9002SIRUGR (X2QFN) pinout drawing.............................................. 7
• Added TLV9004IRUC Thermal Information...................................................................................................... 16
• Changed legend of Closed-Loop Gain vs Frequency plot................................................................................ 19

Changes from Revision H (October 2018) to Revision I (November 2018) Page

• Added TLV9002SIDGS to ESD Ratings table...................................................................................................14

Changes from Revision G (September 2018) to Revision H (October 2018) Page

• Changed From: TLV9001 DCK Package To: TLV9001T DCK Package............................................................. 7

Changes from Revision F (August 2018) to Revision G (September 2018) Page

• Added Device Comparison Table ...................................................................................................................... 6
• Changed pin names for all devices and all packages.........................................................................................7
• Changed pin names and I/O designation on some TLV9001 pins .....................................................................7
• Changed the pin number for V+ in the SOIC, TSSOP column of the Pin Functions: TLV9004 table................. 7

Changes from Revision E (July 2018) to Revision F (August 2018) Page

• Added Scalabe CMOS Amplifier for Low-Cost Applications feature...................................................................1
• Deleted PREVIEW designation on TLV9002 and TLV9004 devices with the TSSOP package. ....................... 1
• Added TLV9001U DBV (SOT-23) pinout drawing to Pin Configuration and Functions section ......................... 7

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• Added SOT-23 U Pinout to Pin Functions section ............................................................................................. 7

Changes from Revision D (June 2018) to Revision E (July 2018) Page

• Corrected typo in Description section ................................................................................................................ 1
• Added TLV9001 5-pin X2SON package to Device Information table ................................................................ 1
• Added TLV9001S 6-pin SOT-23 package to Device Information table...............................................................1
• Added TLV9004 14-pin and 16-pin WQFN packages to Device Information table ............................................1
• Added TLV9001 DPW (X2SON) pinout drawing to Pin Configuration and Functions section............................ 7
• Added TLV9001S 6-pin SOT-23 package to Pin Configuration and Functions section...................................... 7
• Added TLV9004 RTE pinout information to Pin Configuration and Functions section .......................................7
• Added DPW (X2SON) and DRL (SOT-553) packages to Thermal Information: TLV9001 table.......................15
• Added Thermal Information: TLV9001S table to Specifications section........................................................... 15
• Added RUG (X2QFN) package to Thermal Information: TLV9002 table.......................................................... 15
• Added RTE (WQFN) and RUC (WQFN) packages to Thermal Information: TLV9004 table............................ 16

Changes from Revision C (May 2018) to Revision D (June 2018) Page

• Added shutdown text to Description section.......................................................................................................1
• Added TLV9002S and TLV9004S devices to Device Information table.............................................................. 1
• Added TLV9002S 10-pin X2QFN package to Device Information table............................................................. 1
• Added TLV9002S DGS package pinout information to Pin Configurations and Functions section.................... 7
• Added Thermal Information: TLV9001 table to Specifications section............................................................. 15
• Added Thermal Information: TLV9004 table to Specifications section............................................................. 16
• Added shutdown section to Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V
table.................................................................................................................................................................. 17
• Added Shutdown section.................................................................................................................................. 27

Changes from Revision B (March 2018) to Revision C (May 2018) Page

• Added TLV9002 16-pin TSSOP package to Device Information table............................................................... 1
• Added TLV9002 10-pin X2QFN package to Device Information table................................................................1
• Added TLV9002S DGS package pinout drawing in Pin Configurations and Functions section..........................7
• Added TLV9004 pinout diagram and pin configuration table to Pin Configuration and Functions section ........ 7
• Added TLV9004S pinout diagram and pin configuration table to Pin Configuration and Functions section ...... 7
• Changed TLV9002 D (SOIC) junction-to-ambient thermal resistance value from 147.4°C/W to 207.9°C/W... 15
• Changed TLV9002 D (SOIC) junction-to-case (top) thermal resistance from 94.3°C/W to 92.8°C/W..............15
• Changed TLV9002 D (SOIC) junction-to-board thermal resistance from 89.5°C/W to 129.7°C/W...................15
• Changed TLV9002 D (SOIC) junction-to-top characterization parameter from 47.3°C/W to 26°C/W.............. 15
• Changed TLV9002 D (SOIC) junction-to-board characterization parameter from 89°C/W to 127.9°C/W........ 15
• Added DGK (VSSOP) thermal information to Thermal Information: TLV9002 table ........................................15
• Added TLV9002 PW (TSSOP) thermal information to Thermal Information: TLV9002 table........................... 15
• Added PW (TSSOP) thermal information to Thermal Information: TLV9002 table ..........................................16

Changes from Revision A (December 2017) to Revision B (March 2018) Page

• Added package preview notes to TLV9001 packages, TLV9004 packages, and TLV9002 8-pin VSSOP
package in Device Information table ..................................................................................................................1
• Added package preview notes to TLV9001, TLV9004 and TLV9002 VSSOP package pinout drawings in Pin
Configuration and Functions section ................................................................................................................. 7
• Deleted package preview note from TLV9002 DSG (WSON) pinout drawing in Pin Configurations and
Functions section................................................................................................................................................7
• Deleted package preview note from TLV9002 RUG (X2QFN) pinout drawing in Pin Configurations and
Functions section................................................................................................................................................7
• Added DSG (WSON) package thermal information to the Thermal Information: TLV9002 table..................... 15
• Deleted package preview note from DSG (WSON) package in Thermal Information: TLV9002 table............. 15
• Added D (SOIC) package thermal information to the Thermal Information: TLV9004 table.............................16

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Changes from Revision * (October 2017) to Revision A (December 2017) Page

• Changed device status from Advance Information to Production Data/Mixed Status........................................ 1

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5 Device Comparison Table

NO. PACKAGE LEADS
DEVICE OF SC70 SOIC SOT-23 SOT-23 SOT-553 TSSOP VSSOP SOT-23 WQFN WSON X2QFN X2SON X2QFN VSSOP DSBGA
CH. DCK D DBV DYY DRL PW DGK DDF RTE DSG RUC DPW RUG DGS YCK
TLV9001 5 — 5 — 5 — — — — — — 5 — — —
1
TLV9001S 6 — 6 — — — — — — — — — — — —
TLV9002 — 8 — — — 8 8 8 — 8 — — — — —
2
TLV9002S — — — — — — — — — — — — 10 10 9
TLV9004 — 14 — 14 — 14 — — 16 — 14 — — — —
4
TLV9004S — — — — — — — — 16 — — — — — —

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6 Pin Configuration and Functions

OUT 1 5 V+ IN+ 1 5 V+

V± 2 V± 2

IN+ 3 4 IN± IN± 3 4 OUT

Not to scale Not to scale

Figure 6-1. TLV9001 DBV, TLV9001T DCK Package Figure 6-2. TLV9001 DCK Package, TLV9001 DRL
5-Pin SOT-23, SC70 Package, TLV9001U DBV Package
Top View 5-Pin SC70, SOT-553, SOT-23
Top View

OUT 1 5 V+

V±
IN± 2 4 IN+

Not to scale

Figure 6-3. TLV9001 DPW Package

5-Pin X2SON
Top View

Table 6-1. Pin Functions: TLV9001

PIN
SC70, I/O DESCRIPTION
SOT-23,
NAME SOT-23(U), X2SON
SC70(T)
SOT-553
IN– 4 3 2 I Inverting input
IN+ 3 1 4 I Noninverting input
OUT 1 4 1 O Output
V– 2 2 3 I or — Negative (low) supply or ground (for single-supply operation)
V+ 5 5 5 I Positive (high) supply

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OUT 1 6 V+ IN+ 1 6 V+

V± 2 5 SHDN V± 2 5 SHDN

IN+ 3 4 IN± IN± 3 4 OUT

Not to scale Not to scale

Figure 6-4. TLV9001S DBV Package Figure 6-5. TLV9001S DCK Package
6-Pin SOT-23 6-Pin SC70
Top View Top View

Table 6-2. Pin Functions: TLV9001S

PIN
I/O DESCRIPTION
NAME SOT-23 SC70
IN– 4 3 I Inverting input
IN+ 3 1 I Noninverting input
OUT 1 4 O Output
Shutdown: low = amp disabled, high = amp enabled. See Section 8.5 for more
SHDN 5 5 I
information.
V– 2 2 I or — Negative (low) supply or ground (for single-supply operation)
V+ 6 6 I Positive (high) supply

OUT1 1 8 V+
OUT1 1 8 V+
IN1± 2 7 OUT2
IN1± 2 7 OUT2
Thermal
IN1+ 3 6 IN2±
Pad
IN1+ 3 6 IN2±
V± 4 5 IN2+
V± 4 5 IN2+

Not to scale

Figure 6-6. TLV9002 D, DGK, PW, DDF Package Not to scale

8-Pin SOIC, VSSOP, TSSOP, SOT-23 A. Connect thermal pad to V–.

Top View Figure 6-7. TLV9002 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View

Table 6-3. Pin Functions: TLV9002

PIN
I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V– 4 I or — Negative (low) supply or ground (for single-supply operation)
V+ 8 I Positive (high) supply

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IN1+
OUT1 1 10 V+

IN1± 2 9 OUT2
V± 1 9 IN1±
IN1+ 3 8 IN2±

10
V± 4 7 IN2+
SHDN1 2 8 OUT1
SHDN1 5 6 SHDN2

Not to scale SHDN2 3 7 V+

Figure 6-8. TLV9002S DGS Package

5
10-Pin VSSOP
IN2+ 4 6 OUT2
Top View
Not to scale

IN2±
Figure 6-9. TLV9002S RUG Package
10-Pin X2QFN
Top View

1 2 3

C OUT1 V+ OUT2

B IN1– SHDN IN2–

A IN1+ V– IN2+

Not to scale
Figure 6-10. TLV9002S YCK Package
9-Pin DSBGA (WCSP)
Bottom View

Table 6-4. Pin Functions: TLV9002S

PIN
DSBGA I/O DESCRIPTION
NAME VSSOP X2QFN
(WCSP)
IN1– 2 9 B1 I Inverting input, channel 1
IN1+ 3 10 A1 I Noninverting input, channel 1
IN2– 8 5 B3 I Inverting input, channel 2
IN2+ 7 4 A3 I Noninverting input, channel 2
OUT1 1 8 C1 O Output, channel 1
OUT2 9 6 C3 O Output, channel 2
Shutdown: low = amp disabled, high = amp enabled, channel 1. See
SHDN1 5 2 — I
Section 8.5 for more information.

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Table 6-4. Pin Functions: TLV9002S (continued)

PIN
DSBGA I/O DESCRIPTION
NAME VSSOP X2QFN
(WCSP)
Shutdown: low = amp disabled, high = amp enabled, channel 1. See
SHDN2 6 3 — I
Section 8.5 for more information.
SHDN — — B2 Shutdown: low = both amplifiers disabled, high = both amplifiers enabled
V– 4 1 A2 I or — Negative (low) supply or ground (for single-supply operation)
V+ 10 7 C2 I Positive (high) supply

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OUT1

OUT4
OUT1 1 14 OUT4

IN1± 2 13 IN4±
IN1± 1 12 IN4±
IN1+ 3 12 IN4+

14

13
V+ 4 11 V± IN1+ 2 11 IN4+

IN2+ 5 10 IN3+

IN2± 6 9 IN3± V+ 3 10 V±

OUT2 7 8 OUT3
IN2+ 4 9 IN3+

7
Not to scale
IN2± 5 8 IN3±
Figure 6-11. TLV9004 D, DYY, PW Package
14-Pin SOIC, SOT-23 (14), TSSOP

OUT2

OUT3
Top View Not to scale

Figure 6-12. TLV9004 RUC Package

14-Pin X2QFN
Top View
OUT1

OUT4
IN1±

IN4±
16

15

14

13

IN1+ 1 12 IN4+

V+ 2 11 V±
Thermal
IN2+ 3 Pad 10 IN3+

IN2± 4 9 IN3±
5

8
OUT2

NC

NC

OUT3

Not to scale

A. Connect thermal pad to V–.

Figure 6-13. TLV9004 RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View

Table 6-5. Pin Functions: TLV9004

PIN
SOIC, I/O DESCRIPTION
NAME SOT-23 (14), WQFN X2QFN
TSSOP
IN1– 2 16 1 I Inverting input, channel 1
IN1+ 3 1 2 I Noninverting input, channel 1
IN2– 6 4 5 I Inverting input, channel 2
IN2+ 5 3 4 I Noninverting input, channel 2

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Table 6-5. Pin Functions: TLV9004 (continued)

PIN
SOIC, I/O DESCRIPTION
NAME SOT-23 (14), WQFN X2QFN
TSSOP
IN3– 9 9 8 I Inverting input, channel 3
IN3+ 10 10 9 I Noninverting input, channel 3
IN4– 13 13 12 I Inverting input, channel 4
IN4+ 12 12 11 I Noninverting input, channel 4
NC — 6, 7 — — No internal connection
OUT1 1 15 14 O Output, channel 1
OUT2 7 5 6 O Output, channel 2
OUT3 8 8 7 O Output, channel 3
OUT4 14 14 13 O Output, channel 4
V– 11 11 10 I or — Negative (low) supply or ground (for single-supply operation)
V+ 4 2 3 I Positive (high) supply

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OUT1

OUT4
IN1±

IN4±
16

15

14

13
IN1+ 1 12 IN4+

V+ 2 11 V±
Thermal
IN2+ 3 Pad 10 IN3+

IN2± 4 9 IN3±

8
OUT2

SHDN12

SHDN34

OUT3
Not to scale

A. Connect thermal pad to V–.

Figure 6-14. TLV9004S RTE Package

16-Pin WQFN With Exposed Thermal Pad
Top View

Table 6-6. Pin Functions: TLV9004S

PIN
I/O DESCRIPTION
NAME NO.
IN1+ 1 I Noninverting input
IN1– 16 I Inverting input
IN2+ 3 I Noninverting input
IN2– 4 I Inverting input
IN3+ 10 I Noninverting input
IN3– 9 I Inverting input
IN4+ 12 I Noninverting input
IN4– 13 I Inverting input
Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2. See Section 8.5 for
SHDN12 6 I
more information.
Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4. See Section 8.5 for
SHDN34 7 I
more information.
OUT1 15 O Output
OUT2 5 O Output
OUT3 8 O Output
OUT4 14 O Output
V– 11 I or — Negative (low) supply or ground (for single-supply operation)
V+ 2 I Positive (high) supply

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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage (V+) – (V–) 7 V
Common-mode (V–) – 0.5 (V+) + 0.5 V
Voltage(2)
Signal input pins Differential (V+) – (V–) + 0.2 V
Current(2) –10 10 mA
Output short-circuit(3) Continuous
Operating, TA –55 150 °C
Junction, TJ 150 °C
Storage, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

7.2 ESD Ratings

TLV9002S PACKAGE VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
ALL OTHER PACKAGES
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage 1.8 5.5 V
TA Specified temperature –40 125 °C

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7.4 Thermal Information: TLV9001

TLV9001
THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) DPW (X2SON) DRL (SOT-553)(2) UNIT
5 PINS 5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 232.9 239.6 470.0 TBD °C/W
RθJC(top) Junction-to-case (top) thermal resistance 153.8 148.5 211.9 TBD °C/W
RθJB Junction-to-board thermal resistance 100.9 82.3 334.8 TBD °C/W
ψJT Junction-to-top characterization parameter 77.2 54.5 29.8 TBD °C/W
ψJB Junction-to-board characterization parameter 100.4 81.8 333.2 TBD °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) This package option for TLV9001 is preview only.

7.5 Thermal Information: TLV9001S

TLV9001S
THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) UNIT
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 232.9 215.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 153.8 146.4 °C/W
RθJB Junction-to-board thermal resistance 100.9 72.0 °C/W
ψJT Junction-to-top characterization parameter 77.2 55.0 °C/W
ψJB Junction-to-board characterization parameter 100.4 71.7 °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

7.6 Thermal Information: TLV9002

TLV9002
D DGK DGS DSG PW DDF
THERMAL METRIC(1) UNIT
(SOIC) (VSSOP) (VSSOP) (WSON) (TSSOP) (SOT-23)
8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 8 PINS
Junction-to-ambient
RθJA 207.9 201.2 169.5 103.2 200.7 183.7 °C/W
thermal resistance
Junction-to-case (top)
RθJC(top) 92.8 85.7 84.1 120.1 95.4 112.5 °C/W
thermal resistance
Junction-to-board thermal
RθJB 129.7 122.9 113 68.8 128.6 98.2 °C/W
resistance
Junction-to-top
ψJT 26 21.2 15.8 14.7 27.2 18.8 °C/W
characterization parameter
Junction-to-board
ψJB 127.9 121.4 111.6 68.5 127.2 97.6 °C/W
characterization parameter

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

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7.7 Thermal Information: TLV9002S

TLV9002S
THERMAL METRIC(1) DGS (VSSOP) RUG (X2QFN) YCK (DSBGA) UNIT
10 PINS 10 PINS 9 PINS
RθJA Junction-to-ambient thermal resistance 169.5 194.2 101.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 84.1 90.3 0.9 °C/W
RθJB Junction-to-board thermal resistance 113 122.2 33.8 °C/W
ψJT Junction-to-top characterization parameter 15.8 3.5 0.5 °C/W
ψJB Junction-to-board characterization parameter 111.6 118.8 33.8 °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

7.8 Thermal Information: TLV9004

TLV9004
THERMAL METRIC(1) D (SOIC) DYY (SOT-23) PW (TSSOP) RTE (WQFN) RUC (X2QFN) UNIT
14 PINS 14 PINS 14 PINS 16 PINS 14 PINS
Junction-to-ambient thermal
RθJA 102.1 154.3 148.3 66.4 205.5 °C/W
resistance
Junction-to-case (top) thermal
RθJC(top) 56.8 86.8 68.1 69.3 72.5 °C/W
resistance
Junction-to-board thermal
RθJB 58.5 67.9 92.7 41.7 150.2 °C/W
resistance
Junction-to-top characterization
ψJT 20.5 10.1 16.9 5.7 3.0 °C/W
parameter
Junction-to-board
ψJB 58.1 67.5 91.8 41.5 149.6 °C/W
characterization parameter

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

7.9 Thermal Information: TLV9004S

TLV9004S
THERMAL METRIC(1) RTE (WQFN) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 66.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 69.3 °C/W
RθJB Junction-to-board thermal resistance 41.7 °C/W
ψJT Junction-to-top characterization parameter 5.7 °C/W
ψJB Junction-to-board characterization parameter 41.5 °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

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7.10 Electrical Characteristics

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT =
VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VS = 5 V ±0.4 ±1.6
VOS Input offset voltage mV
VS = 5 V, TA = –40°C to 125°C ±2
dVOS/dT VOS vs temperature TA = –40°C to 125°C ±0.6 µV/°C
PSRR Power-supply rejection ratio VS = 1.8 to 5.5 V, VCM = (V–) 80 105 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.1 (V+) + 0.1 V
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
86
TA = –40°C to 125°C
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
95
TA = –40°C to 125°C
CMRR Common-mode rejection ratio dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V,
63 77
TA = –40°C to 125°C
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V,
68
TA = –40°C to 125°C
INPUT BIAS CURRENT
IB Input bias current VS = 5 V ±5 pA
IOS Input offset current ±2 pA
NOISE
Input voltage noise (peak-to-
En ƒ = 0.1 Hz to 10 Hz, VS = 5 V 4.7 µVPP
peak)
ƒ = 1 kHz, VS = 5 V 30
en Input voltage noise density nV/√ Hz
ƒ = 10 kHz, VS = 5 V 27
in Input current noise density ƒ = 1 kHz, VS = 5 V 23 fA/√ Hz
INPUT CAPACITANCE
CID Differential 1.5 pF
CIC Common-mode 5 pF
OPEN-LOOP GAIN
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
104 117
RL = 10 kΩ
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
100
RL = 10 kΩ
AOL Open-loop voltage gain dB
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
115
RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
130
RL = 2 kΩ
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 5 V 1 MHz
φm Phase margin VS = 5.5 V, G = 1 78 °
SR Slew rate VS = 5 V 2 V/µs
To 0.1%, VS = 5 V, 2-V step, G = +1, CL = 100 pF 2.5
tS Settling time µs
To 0.01%, VS = 5 V, 2-V step, G = +1, CL = 100 pF 3
tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.85 µs
Total harmonic distortion + VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
THD+N 0.004%
noise ƒ = 1 kHz, 80-kHz measurement BW
OUTPUT

Voltage output swing from VS = 5.5 V, RL = 10 kΩ 10 20

VO mV
supply rails VS = 5.5 V, RL = 2 kΩ 35 55
ISC Short-circuit current VS = 5.5 V ±40 mA
ZO Open-loop output impedance VS = 5 V, ƒ = 1 MHz 1200 Ω

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7.10 Electrical Characteristics (continued)

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT =
VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V
TLV9002, TLV9002S TLV9004,
IO = 0 mA, VS = 5.5 V 60 75
TLV9004S
IQ Quiescent current per amplifier µA
TLV9001, TLV9001S IO = 0 mA, VS = 5.5 V 60 77
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C 85
SHUTDOWN(1)
IQSD Quiescent current per amplifier VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS– 0.5 1.5 µA
Output impedance during
ZSHDN VS = 1.8 V to 5.5 V, amplifier disabled 10 || 2 GΩ || pF
shutdown
High level voltage shutdown
VS = 1.8 V to 5.5 V (V–) + 0.9 (V–) + 1.1 V
threshold (amplifier enabled)
Low level voltage shutdown
VS = 1.8 V to 5.5 V (V–) + 0.2 V (V–) + 0.7 V V
threshold (amplifier disabled)
Amplifier enable time (full VS = 1.8 V to 5.5 V, full shutdown; G = 1,
70
shutdown) VOUT = 0.9 × VS / 2, RL connected to V–
tON µs
Amplifier enable time (partial VS = 1.8 V to 5.5 V, partial shutdown; G = 1,
50
shutdown) VOUT = 0.9 × VS / 2, RL connected to V–
VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2,
tOFF Amplifier disable time 4 µs
RL connected to V–

SHDN pin input bias current VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V 40
nA
(per pin) VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V 150

(1) Specified by design and characterization; not production tested.

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7.11 Typical Characteristics

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)

40 25

35
20
30

Population (%)
Population (%)

25 15

20

10
15

10
5
5

0 0
-1200 -900 -600 -300 0 300 600 900 1200 1500 1800 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
D001 Offset Voltage Drift (μV/°C) D002
Offset Voltage (μV)
VS = 5 V VS = 5 V, TA = –40°C to 125°C
Figure 7-1. Offset Voltage Distribution Histogram Figure 7-2. Offset Voltage Drift Distribution Histogram
1000 2000
800
1500
600
Input Offset Voltage (µV)

1000
400
Offset Voltage (μV)

200 500

0 0
-200
-500
-400
-1000
-600
-800 -1500

-1000 -2000
-40 -20 0 20 40 60 80 100 120 140 -4 -3 -2 -1 0 1 2 3 4
Temperature (°C) D003 Common-Mode Voltage (V) D004
Figure 7-3. Input Offset Voltage vs Temperature Figure 7-4. Offset Voltage vs Common-Mode
1000 6
IB
800 I B+
4
600 IOS
2
400
Offset Voltage (PV)

IB and IOS (pA)

200 0

0 -2
-200
-4
-400
-6
-600
-800 -8
-1000
-10
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
-40 -20 0 20 40 60 80 100 120 140
Supply Voltage (V) D005 Temperature (qC) D006
Figure 7-5. Offset Voltage vs Supply Voltage
Figure 7-6. IB and IOS vs Temperature

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7.11 Typical Characteristics (continued)

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)

3.5 160
3 IB IB+ IOS
140
2.5
2 120
1.5
IB and IOS (pA)

100

Gain (dB)
1
0.5 80
0
60
-0.5
-1 40
-1.5
20 VS = 5.5 V
-2
VS = 1.8 V
-2.5 0
-3 -2 -1 0 1 2 3 -40 -20 0 20 40 60 80 100 120 140
Common-Mode Voltage (V) D007 Temperature (qC) D008
Figure 7-7. IB and IOS vs Common-Mode Voltage Figure 7-8. Open-Loop Gain vs Temperature
100 120
160

80 100 140
Open-Loop Voltage Gain (dB)

120
60 80
100
Gain (dB)

Phase (q)

40 60
80

20 40 60

40
0 20
Gain 20
Phase
-20 0 0
1k 10k 100k 1M -3 -2 -1 0 1 2 3
Frequency (Hz) D009 Output Voltage (V) D010
CL = 10 pF
Figure 7-9. Open-Loop Gain and Phase vs Frequency Figure 7-10. Open-Loop Gain vs Output Voltage
80 3
Gain = 1 2.5
70 Gain = 1
Gain = 100 2
60
Gain = 1000 1.5 125°C
50 Gain = 10 85°C 25°C
1 -40°C
Output Voltage (V)

40
Gain (dB)

0.5
30 0
20 -0.5
-1 85°C 25°C -40°C
10
-1.5 125°C
0
-2
-10 -2.5
-20 -3
100 1k 10k 100k 1M 0 5 10 15 20 25 30 35 40 45 50
Frequency (Hz) D011
Output Current (mA) D012

CL = 10 pF
Figure 7-11. Closed-Loop Gain vs Frequency Figure 7-12. Output Voltage vs Output Current (Claw)

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7.11 Typical Characteristics (continued)

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)

120 120
PSRR+
PSRR

Power Supply Rejection Ratio (dB)

Power Supply Rejection Ratio (dB)

100 100

80 80

60 60

40 40

20 20

0 0
100 1k 10k 100k 1M -40 -20 0 20 40 60 80 100 120 140
Frequency (Hz) Temperature (qC) D014
D013

VS = 1.8 V to 5.5 V
Figure 7-13. PSRR vs Frequency Figure 7-14. DC PSRR vs Temperature
120 160
Common-Mode Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)

140
100
120
80
100

60 80

60
40
40
20
20 VS = 1.8 V
VS = 5.5 V
0 0
100 1k 10k 100k 1M -40 -20 0 20 40 60 80 100 120 140
Frequency (Hz) Temperature (qC) D016
D015
VCM = (V–) – 0.1 V to (V+) – 1.4 V
Figure 7-15. CMRR vs Frequency Figure 7-16. DC CMRR vs Temperature
Input Voltage Noise Spectral Density (nV/—Hz)

120

100
Amplitude (1 PV/div)

80

60

40

20

0
Time (1 s/div) 10 100 1k 10k 100k
D017 Frequency (Hz) D018
Figure 7-17. 0.1-Hz to 10-Hz Integrated Voltage Noise Figure 7-18. Input Voltage Noise Spectral Density

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7.11 Typical Characteristics (continued)

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)

-50 0
G = +1, RL = 2 k: G = 1, RL = 2 k:
G = +1, RL = 10 k: G = 1, RL = 10 k:
-60 -20
THD + N (dB)

THD + N (dB)
-70 -40

-80 -60

-90 -80
RL = 2K
RL = 10K
-100 -100
100 1k 10k 0.001 0.01 0.1 1 2
Frequency (Hz) D019
Amplitude (V RMS) D020

VS = 5.5 V VCM = 2.5 V G=1 VS = 5.5 V VCM = 2.5 V ƒ = 1 kHz

BW = 80 kHz VOUT = 0.5 VRMS G=1 BW = 80 kHz
Figure 7-19. THD + N vs Frequency Figure 7-20. THD + N vs Amplitude
70 70

60 60
Quiescent Current (PA)
Quiescent Current (PA)

50 50

40 40

30 30

20 20

10 10

0 0
1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 -20 0 20 40 60 80 100 120 140
Voltage Supply (V) Temperature (qC) D022
D021
Figure 7-21. Quiescent Current vs Supply Voltage Figure 7-22. Quiescent Current vs Temperature
2000 50
1800 45
Open-Loop Output Impedance (:)

1600 40
1400 35
Overshoot (%)

1200 30
1000 25
800 20
600 15
400 10
200 5 Overshoot (+)
Overshoot (–)
0 0
1k 10k 100k 1M 10M 0 200 400 600 800 1000
Frequency (Hz) D023 Capacitance Load (pF) D024

G=1 VIN = 100 mVpp

Figure 7-23. Open-Loop Output Impedance vs Frequency Figure 7-24. Small Signal Overshoot vs Capacitive Load

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7.11 Typical Characteristics (continued)

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)

50 90
45 80
40 70
35

Phase Margin (q)

60
Overshoot (%)

30
50
25
40
20
30
15
10 20

5 Overshoot (+) 10
Overshoot (–)
0 0
0 200 400 600 800 1000 0 200 400 600 800 1000
Capacitance Load (pF) D025
Capacitance Load (pF) D026

G = –1 VIN = 100 mVpp

Figure 7-25. Small Signal Overshoot vs Capacitive Load Figure 7-26. Phase Margin vs Capacitive Load

VOUT VOUT
VIN VIN
Amplitude (1 V/div)

Amplitude (1 V/div)

Time (100 Ps/div) Time (20 Ps/div)

D027 D028

G=1 VIN = 6.5 VPP G = –10 VIN = 600 mVPP

Figure 7-27. No Phase Reversal Figure 7-28. Overload Recovery

VOUT VOUT
VIN VIN
Voltage (20 mV/div)

Voltage (1 V/div)

Time (10 Ps/div) Time (10 Ps/div)

D029 D030

G=1 VIN = 100 mVPP CL = 10 pF G=1 VIN = 4 VPP CL = 10 pF

Figure 7-29. Small-Signal Step Response Figure 7-30. Large-Signal Step Response

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7.11 Typical Characteristics (continued)

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)

Output Voltage (1 mV/div)

Output Voltage (1 mV/div)

Time (1 μs/div) Time (1 Ps/div)

D031 D032

G=1 CL = 100 pF 2-V step G=1 CL = 100 pF 2-V step

Figure 7-31. Large-Signal Settling Time (Negative) Figure 7-32. Large-Signal Settling Time (Positive)
80 6
VS = 5.5 V
60 VS = 1.8 V
5
Maximum Output Voltage (V)
Short Circuit Current (mA)

40
4
20

0 3

-20
2
-40
1
-60 Sinking
Sourcing
-80 0
-40 -20 0 20 40 60 80 100 120 1 10 100 1k 10k 100k 1M 10M 100M
Temperature (qC) Frequency (Hz) D034
D033

Figure 7-33. Short-Circuit Current vs Temperature Figure 7-34. Maximum Output Voltage vs Frequency
140 0

120 -20
Channel Separation (dB)

100 -40
EMIRR (dB)

80 -60

60 -80

40 -100

20 -120

0 -140
10M 100M 1G 10G 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz) D036
D035
Figure 7-35. Electromagnetic Interference Rejection Ratio Figure 7-36. Channel Separation
Referred to Noninverting Input (EMIRR+) vs Frequency

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8 Detailed Description
8.1 Overview
The TLV900x is a family of low-power, rail-to-rail input and output op amps. These devices operate from 1.8 V
to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input
common-mode voltage range includes both rails and allows the TLV900x family to be used in virtually any
single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in
low-supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).
8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Operating Voltage
The TLV900x family of op amps are for operation from 1.8 V to 5.5 V. In addition, many specifications such
as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C.
Parameters that vary significantly with operating voltages or temperature are shown in Section 7.11.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV900x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage:
an N-channel input differential pair in parallel with a P-channel differential pair, as shown in Section 8.2. The
N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV above
the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative supply to
approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both
pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus, the transition
region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+) – 1 V to
(V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can
degrade compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLV900x family delivers a robust output
drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.4 EMI Rejection
The TLV900x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV900x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
8-1 shows the results of this testing on the TLV900x. Table 8-1 shows the EMIRR IN+ values for the TLV900x at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
140

120

100
EMIRR (dB)

80

60

40

20

0
10M 100M 1G 10G
Frequency (Hz) D035

Figure 8-1. EMIRR Testing

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Table 8-1. TLV900x EMIRR IN+ For Frequencies of Interest

FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
400 MHz 59.5 dB
applications
Global system for mobile communications (GSM) applications, radio communication, navigation,
900 MHz 68.9 dB
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 77.8 dB
802.11b, 802.11g, 802.11n, Bluetooth®,
mobile personal communications, industrial, scientific and
2.4 GHz 78.0 dB
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.8 dB

8.4 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV900x family is approximately 850 ns.
8.5 Shutdown
The TLV9001S, TLV9002S, and TLV9004S devices feature SHDN pins that disable the op amp, placing it into
a low-power standby mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are
active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 620 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown
pin circuitry includes a pull-up resistor, which will inherently pull the voltage of the pin to the positive supply rail
if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid logic
high. To disable the amplifier, the SHDN pins must be driven to a valid logic low. While we highly recommend
that the shutdown pin be connected to a valid high or a low voltage or driven, we have included a pull-up resistor
connected to VCC. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level
will damage the device.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
used to greatly reduce the average current and extend battery life. The enable time is 70 µs for full shutdown of
all channels; disable time is 4 µs. When disabled, the output assumes a high-impedance state. This architecture
allows the TLV9002S and TLV9004S to operate as a gated amplifier (or to have the device output multiplexed
onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load
to midsupply (VS / 2) is required. If using the TLV9001S, TLV9002S, or TLV9004S without a load, the resulting
turnoff time significantly increases.
8.6 Device Functional Modes
The TLV900x family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

The TLV900x family of low-power, rail-to-rail input and output operational amplifiers is specifically designed for
portable applications. The devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving less than or equal to
10‑kΩ loads connected to any point between V+ and V–. The input common-mode voltage range includes both
rails, and allows the TLV900x devices to be used in any single-supply application.
9.2 Typical Application
9.2.1 TLV900x Low-Side, Current Sensing Application
Figure 9-1 shows the TLV900x configured in a low-side current sensing application.
VBUS

ILOAD ZLOAD
5V
+
TLV9002 VOUT
+ í

VSHUNT RSHUNT
RF
0.1 Ÿ
57.6 NŸ
í

RG
1.2 NŸ

Figure 9-1. TLV900x in a Low-Side, Current-Sensing Application

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9.2.1.1 Design Requirements

The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
9.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is given in Equation 1.

VOUT ILOAD u RSHUNT u Gain (1)

The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
shown using Equation 2.

VSHUNT _ MAX 100mV

RSHUNT 100m:
ILOAD _ MAX 1A (2)

Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV900x to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the
TLV900x to produce the necessary output voltage is calculated using Equation 3.

VOUT _ MAX VOUT _ MIN

Gain
VIN _ MAX VIN _ MIN
(3)

Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the TLV900x to 49 V/V.

RF
Gain 1
RG (4)

Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 9-2 shows the
measured transfer function of the circuit shown in Figure 9-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.

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9.2.1.3 Application Curve

5

Output (V)
3

0
0 0.2 0.4 0.6 0.8 1
ILOAD (A) C219

Figure 9-2. Low-Side, Current-Sense Transfer Function

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9.2.2 Single-Supply Photodiode Amplifier

Photodiodes are used in many applications to convert light signals to electrical signals. The current through
the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred
picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert
the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in Figure 9-3 is
an example of a single-supply photodiode amplifier circuit using the TLV9002.
+3.3V

R1
CF
11.5 NŸ
10 pF
VREF

R2 RF
357 Ÿ 309 NŸ

3.3 V

±
TLV9002 VOUT
VREF +

IIN CPD
0-10 µA 47 pF RL
10 k

Figure 9-3. Single-Supply Photodiode Amplifier Circuit

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9.2.2.1 Design Requirements

The design requirements for this design are:
• Supply voltage: 3.3 V
• Input: 0 µA to 10 µA
• Output: 0.1 V to 3.2 V
• Bandwidth: 50 kHz
9.2.2.2 Detailed Design Procedure
The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF)
is defined in Equation 5.

VOUT IIN u RF VREF (5)

Where:

§ R u R2 ·
VREF V u¨ 1 ¸
© R1 R2 ¹ (6)

Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio
calculated in Equation 7.

VREF 0.1 V
0.0303
V 3.3 V (7)

The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω.
The required feedback resistance can be calculated based on the input current and desired output voltage.

VOUT VREF 3.2 V 0.1 V kV

RF 310 | 309 k:
IIN 10 PA A (8)

Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3dB) using
Equation 9.

1 1
CF 10.3 pF | 10 pF
2 u S u RF u f 3dB 2 u S u 309 k: u 50 kHz (9)

The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the
capacitance on the INx– pin of the TLV9002 which is equal to the sum of the photodiode shunt capacitance,
(CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10
shows.

CIN CPD CCM CD 47 pF 5 pF 1 pF 53 pF (10)

The minimum op amp bandwidth is calculated in Equation 11.

CIN CF
f BGW t t 324 kHz
2 u S u RF u CF2 (11)

The 1-MHz bandwidth of the TLV900x meets the minimum bandwidth requirement and remains stable in this
application configuration.

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9.2.2.3 Application Curves

The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in Figure 9-4. The
measured performance of the photodiode amplifier circuit is shown in Figure 9-5.

120 3

2.5
100

Output Voltage (V)

2
Gain (dB)

80 1.5

1
60
0.5

40 0
10 100 1k 10k 100k 1M 0 2E-6 4E-6 6E-6 8E-6 1E-5
Frequency (Hz) D001 Input Current (A) D002

Figure 9-4. Photodiode Amplifier Circuit AC Gain Figure 9-5. Photodiode Amplifier Circuit DC
Results Results

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10 Power Supply Recommendations

The TLV900x family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to 125°C. Section 7.11 presents parameters that may exhibit significant variance with regard to
operating voltage or temperature.

CAUTION
Supply voltages larger than 6 V may permanently damage the device; see Section 7.1.

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.1.
10.1 Input and ESD Protection
The TLV900x family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA. Figure 10-1 shows how a series input resistor can be added to the driven input to limit the input current.
The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in
noise-sensitive applications.

V+

IOVERLOAD
10-mA maximum
Device VOUT
VIN
5 kW

Figure 10-1. Input Current Protection

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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power connections of the board and propagate to the
power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a
low-impedance path to ground.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as
opposed to running the traces in parallel with the noisy trace.
• Place the external components as close to the device as possible, as shown in Figure 11-2. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
VIN 1 + VIN 2 +
RG VOUT 1 RG VOUT 2

RF RF

Figure 11-1. Schematic Representation

Place components OUT 1

close to device and to Use low-ESR,
VS+ ceramic bypass
each other to reduce
parasitic errors . capacitor . Place as
close to the device
as possible .

OUT1 V+ GND
RF
OUT 2
GND IN1 ± OUT2
RG RF
VIN 1 IN1 + IN2 ± GND
RG
V± IN2 + VIN 2

Keep input traces short

Use low-ESR,
and run the input traces
ceramic bypass GND as far away from
capacitor . Place as VS± Ground (GND) plane on another layer the supply lines
close to the device as possible .
as possible .

Figure 11-2. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TLV9001IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1OGF Samples

TLV9001IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1BZ Samples

TLV9001IDPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 DF Samples

TLV9001SIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1OJF Samples

TLV9001SIDCKR ACTIVE SC70 DCK 6 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1F8 Samples

TLV9001TIDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1D6 Samples

TLV9001UIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1ODF Samples

TLV9001ZIDPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (D, DF) Samples

TLV9002IDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T902 Samples

TLV9002IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 (1GNX, OBBI) Samples
| NIPDAUAG
TLV9002IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 (1GNX, OBBI) Samples
| NIPDAUAG
TLV9002IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TL9002 Samples

TLV9002IDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH Samples

TLV9002IDSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH Samples

TLV9002IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 9002 Samples

TLV9002SIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1GDX Samples

TLV9002SIRUGR ACTIVE X2QFN RUG 10 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 ENF Samples

TLV9002SIYCKR ACTIVE DSBGA YCK 9 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 JK Samples

TLV9004IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV9004 Samples

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TLV9004IDYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TLV9004I Samples

TLV9004IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TLV9004 Samples

TLV9004IRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9004 Samples

TLV9004IRUCR ACTIVE QFN RUC 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1DC Samples

TLV9004SIRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9004S Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV9001, TLV9002, TLV9004 :

• Automotive : TLV9001-Q1, TLV9002-Q1, TLV9004-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9001IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV9001IDCKR SC70 DCK 5 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
TLV9001IDPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q2
TLV9001SIDBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV9001SIDCKR SC70 DCK 6 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
TLV9001TIDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TLV9001UIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV9001ZIDPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q2
TLV9002IDDFR SOT-23- DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
THIN
TLV9002IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV9002IDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV9002IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV9002IDSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV9002IDSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV9002IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9002SIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV9002SIRUGR X2QFN RUG 10 3000 178.0 8.4 1.75 2.25 0.56 4.0 8.0 Q1
TLV9002SIYCKR DSBGA YCK 9 3000 180.0 8.4 1.1 1.1 0.4 2.0 8.0 Q1
TLV9004IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV9004IDYYR SOT-23- DYY 14 3000 330.0 12.4 4.8 3.6 1.6 8.0 12.0 Q3
THIN
TLV9004IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV9004IRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TLV9004IRUCR QFN RUC 14 3000 180.0 9.5 2.16 2.16 0.5 4.0 8.0 Q2
TLV9004SIRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV9001IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV9001IDCKR SC70 DCK 5 3000 210.0 185.0 35.0
TLV9001IDPWR X2SON DPW 5 3000 205.0 200.0 33.0
TLV9001SIDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0
TLV9001SIDCKR SC70 DCK 6 3000 210.0 185.0 35.0
TLV9001TIDCKR SC70 DCK 5 3000 190.0 190.0 30.0
TLV9001UIDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV9001ZIDPWR X2SON DPW 5 3000 205.0 200.0 33.0
TLV9002IDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0
TLV9002IDGKR VSSOP DGK 8 2500 356.0 356.0 35.0
TLV9002IDGKT VSSOP DGK 8 250 356.0 356.0 35.0
TLV9002IDR SOIC D 8 2500 356.0 356.0 35.0
TLV9002IDSGR WSON DSG 8 3000 210.0 185.0 35.0
TLV9002IDSGT WSON DSG 8 250 210.0 185.0 35.0
TLV9002IPWR TSSOP PW 8 2000 356.0 356.0 35.0
TLV9002SIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0
TLV9002SIRUGR X2QFN RUG 10 3000 205.0 200.0 33.0
TLV9002SIYCKR DSBGA YCK 9 3000 182.0 182.0 20.0

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Feb-2024

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV9004IDR SOIC D 14 2500 356.0 356.0 35.0
TLV9004IDYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8
TLV9004IPWR TSSOP PW 14 2000 356.0 356.0 35.0
TLV9004IRTER WQFN RTE 16 3000 367.0 367.0 35.0
TLV9004IRUCR QFN RUC 14 3000 205.0 200.0 30.0
TLV9004SIRTER WQFN RTE 16 3000 367.0 367.0 35.0

Pack Materials-Page 4
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
1.45 MAX

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214840/E 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/E 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/E 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DPW0005A SCALE 12.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

0.85 A
B
0.75

PIN 1 INDEX AREA 0.85

0.75

0.4 MAX C

SEATING PLANE

NOTE 3

(0.1)

4X (0.05) (0.324) 0.05

0.00

2 0.25 0.1

4
NOTE 3
2X 3
2X (0.26)
0.48

5
1
0.27
0.239 4X
0.17
0.139
0.1 C A B
0.288
3X 0.05 C
0.188

4223102/D 03/2022
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.

www.ti.com
 EXAMPLE BOARD LAYOUT
DPW0005A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.78)

SYMM ( 0.1)
4X (0.42) VIA 0.05 MIN
ALL AROUND
1 TYP

5
4X (0.22)

SYMM
4X (0.26)
(0.48)
3

2 4

(R0.05) TYP
SOLDER MASK
4X (0.06) OPENING, TYP
( 0.25)
(0.21) TYP METAL UNDER
EXPOSED METAL SOLDER MASK
CLEARANCE TYP

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED
SCALE:60X

4223102/D 03/2022
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DPW0005A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

4X (0.42) 4X (0.06)

5
4X (0.22) 1

( 0.24)

4X (0.26)
SYMM
(0.21) (0.48)
TYP
SOLDER MASK
EDGE 3

2
4

(R0.05) TYP
SYMM

(0.78)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X

4223102/D 03/2022
NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DPW0005B SCALE 12.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

0.85 A
B
0.75

0.85
PIN 1 INDEX AREA
0.75

0.4 MAX C

SEATING PLANE

0.05 NOTE 3
0.00

0.35 2X (0.36)
0.15 0.27 (0.1) TYP
4X
0.17

2
4
NOTE 3
3
2X 0.48 2X (0.26)

5
1

0.27
4X
PIN 1 ID 0.17
0.1 C A B
0.05 C

4228233/D 09/2023
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.

www.ti.com
 EXAMPLE BOARD LAYOUT
DPW0005B X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.78)

SYMM
4X (0.42) 4X (0.06) 0.05 MIN
ALL AROUND
TYP
5
4X (0.22) 1

SYMM (0.48)

3 4X (0.26)

2
4

(R0.05) TYP
SOLDER MASK
( 0.1) VIA OPENING, TYP
( 0.25)
METAL UNDER
(0.21) TYP SOLDER MASK, TYP
EXPOSED METAL
CLEARANCE

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED
SCALE:60X

4228233/D 09/2023
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DPW0005B X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

4X (0.42)
4X (0.06)

5
4X (0.22) 1
( 0.24)

SOLDER MASK
SYMM EDGE 3
(0.48)

(0.21)
TYP

2
4

(R0.05) TYP
SYMM

(0.78)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 5
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:60X

4228233/D 09/2023
NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214839/J 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/J 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/J 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1
0.1 C A B (0.9) TYP
0.0
NOTE 5

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/D 07/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.

www.ti.com
 EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/D 07/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/D 07/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
YCK0009 SCALE 12.000
DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

0.33 MAX
C

SEATING PLANE
BALL TYP 0.05 C
0.125
0.075

0.7 TYP

SYMM

0.7 TYP SYMM

B
D: Max = 0.98 mm, Min = 0.92 mm
0.35 TYP
E: Max = 0.98 mm, Min = 0.92 mm
A

1 2 3

0.195
9X
0.155 0.35 TYP
0.015 C A B

4225837/A 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YCK0009 DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY

(0.35) TYP
9X ( 0.18)
1 2 3

(0.35) TYP

SYMM
B

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 50X

0.0325 MAX 0.0325 MIN METAL UNDER

( 0.18) SOLDER MASK
METAL

SOLDER MASK EXPOSED EXPOSED ( 0.18)

OPENING METAL METAL SOLDER MASK
OPENING
SOLDER MASK
NON-SOLDER MASK DEFINED
DEFINED (PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225837/A 04/2020

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YCK0009 DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY

(0.35) TYP

9X ( 0.21) (R0.05) TYP

1 2 3

(0.35) TYP

SYMM
B

METAL
TYP SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL
SCALE: 50X

4225837/A 04/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
 GENERIC PACKAGE VIEW
DSG 8 WSON - 0.8 mm max height
2 x 2, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224783/A

www.ti.com
 PACKAGE OUTLINE
DSG0008A SCALE 5.500
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2.1 B
A
1.9

0.32
PIN 1 INDEX AREA 0.18
2.1
1.9

0.4
0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8 C
0.7

SEATING PLANE
0.05 SIDE WALL
0.08 C
0.00 METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2

EXPOSED
THERMAL PAD 0.9 0.1 (DIM A) TYP

4 5

6X 0.5

2X
9
1.5 1.6 0.1

8
1

PIN 1 ID 0.32
8X
(45 X 0.25) 0.4 0.18
8X
0.2 0.1 C A B
0.05 C

4218900/E 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DSG0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.9) ( 0.2) VIA

8X (0.5)
TYP
1
8

8X (0.25)
(0.55)
SYMM 9
(1.6)

6X (0.5)
5
4

(R0.05) TYP SYMM

(1.9)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218900/E 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DSG0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5) SYMM METAL

1
8

8X (0.25)
(0.45)
SYMM
9

6X (0.5) (0.7)

5
4

(R0.05) TYP (0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4218900/E 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6 SEATING PLANE
TYP
6.2

A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1

3.1 2X
2.9
NOTE 3 1.95

4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE

0.75 0.15
0 -8 0.05
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8

SYMM

6X (0.65)
5
4

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8

SYMM

6X (0.65)
5
4

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221848/A 02/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
RUC0014A X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

2.1 A
B 1.9

PIN 1 INDEX AREA 2.1

1.9

0.4 MAX
C

SEATING PLANE
0.08 C
0.05
0.00

2X 0.4 (0.15) TYP

6 7
8X 0.4
5
8

SYMM
1.6

12
1

14 13 14X 0.25
0.15
PIN 1 ID SYMM
(45oX0.1) 14X 0.5 0.1 C A B
0.3
0.05 C

4220584/A 05/2019
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RUC0014A X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

SYMM

14X (0.6)
14X (0.2)

8X (0.4) SYMM
(1.6) (1.8)

(R0.05)

2X (0.4)
(1.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 23X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND SOLDER MASK
METAL
OPENING

EXPOSED METAL SOLDER MASK EXPOSED METAL METAL UNDER

OPENING SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4220584/A 05/2019

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
RUC0014A X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD

SYMM

14X (0.6)
14X (0.2)

8X (0.4) SYMM
(1.6) (1.8)

(R0.05)

2X (0.4)
(1.8)

SOLDER PASTE EXAMPLE

BASED ON 0.100mm THICK STENCIL
SCALE: 23X

4220584/A 05/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A
0.25
GAGE PLANE

1.1 MAX

0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

TYPICAL

4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM
8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214862/A 04/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM

8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

(4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X

4214862/A 04/2023
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DDF0008A SCALE 4.000
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE

C
2.95 SEATING PLANE
TYP
2.65

A PIN 1 ID 0.1 C
AREA

6X 0.65
8
1

2.95
2.85 2X
NOTE 3 1.95

4
5
0.38
8X
0.22
1.65 0.1 C A B
B 1.1 MAX
1.55

0.20
TYP
0.08

SEE DETAIL A

0.25
GAGE PLANE

0.1
0 -8 0.6 0.0
0.3
DETAIL A
TYPICAL

4222047/C 10/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDF0008A SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05)
SYMM
1
8

8X (0.45)
SYMM

6X (0.65)
5
4

(R0.05)
TYP (2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4222047/C 10/2022
NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDF0008A SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05) SYMM
(R0.05) TYP
1
8

8X (0.45)
SYMM

6X (0.65)
5
4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4222047/C 10/2022
NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
RTE 16 WQFN - 0.8 mm max height
3 x 3, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225944/A

www.ti.com
 PACKAGE OUTLINE
RTE0016C SCALE 3.600
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

SIDE WALL
METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2
C
0.8 MAX

SEATING PLANE
0.05
0.00 0.08

1.68 0.07 (DIM A) TYP

5 8
EXPOSED
THERMAL PAD
12X 0.5
4
9

4X 17 SYMM
1.5

1
12
0.30
16X
0.18
PIN 1 ID 16 13 0.1 C A B
(OPTIONAL) SYMM
0.05

0.5
16X
0.3

4219117/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RTE0016C WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.68)
SYMM
16 13

16X (0.6)

1
12

16X (0.24)
17 SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4

( 0.2) TYP
VIA

5 8
(R0.05) (0.58) TYP
ALL PAD CORNERS
(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
SOLDER MASK METAL METAL UNDER
METAL
OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4219117/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RTE0016C WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.55)
16 13

16X (0.6)

1
12

16X (0.24)

17 SYMM
(2.8)

12X (0.5)

9
4

METAL
ALL AROUND

5 8
SYMM
(R0.05) TYP

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4219117/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

3.36 C
3.16 SEATING PLANE

A PIN 1 INDEX
AREA 0.1 C

12X 0.5
14
1

4.3 2X
4.1
NOTE 3 3

7
8

14X 0.31
0.11
0.1 C A B 1.1 MAX
B 2.1
1.9

0.2 TYP
0.08

SEE DETAIL A

0.25
GAUGE PLANE

0°- 8°
0.63 0.1
0.33 0.0
DETAIL A
TYP

4224643/B 07/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB

www.ti.com
 EXAMPLE BOARD LAYOUT
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

SYMM
14X (1.05)

1 14

14X (0.3)

SYMM

12X (0.5)

8
7

(R0.05) TYP
(3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

SOLDER MASK METAL UNDER

OPENING SOLDER MASK SOLDER MASK
METAL OPENING

NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4224643/B 07/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

SYMM
14X (1.05)

1 14

14X (0.3)

SYMM

12X (0.5)

8
7

(R0.05) TYP
(3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 20X

4224643/B 07/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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