Automatic solution to frame clock domain groupings

for efficient At-speed Structural testing

Hardik Bhagat (hardik.bhagat@globalfoundries.com),

Greeshma Jayakumar (greeshma.jayakumar@globalfoundries.com)
GLOBALFOUNDRIES, Bengaluru, India

the number of nodes or faults activated during test doesn’t

Abstract stress the power rails beyond limits and cause IR droop.
As the technology nodes keep shrinking, the ASIC chips are
growing in design complexities and the possible types of For creating optimized grouping solutions, the user should
defects during manufacturing have increased exponentially. be aware of the clock architecture of the design in detail and
With many clock domains operating at different should be aware of the complicated grouping criteria based
frequencies, it is imperative now for any ASIC chip provider on synchronous behavior across clock domains and the
to test the chip thoroughly at the functional operating functional timings closed on each of the domains. The
frequencies. At speed test on such multi-domain chips manual process is a tedious time consuming and error prone
requires identification of groups of domains to be tested process. The shorter design cycle further increases the risks
together. The efficiency of patterns and pattern volume are involved in manual clock grouping efforts.
directly dependent of the domain groupings and smarter
groupings thus save the test time and test cost. 2. Proposed Solution
This paper talks about an algorithm which can be applied a. Inputs Required
on any complicated design for getting the most efficient and
first time right clock domain groups for doing at-speed test.
i. Details of clock domains in the design and the
clock architecture details ( PLL instances, clock
Automating this algorithm has saved many days of manual
controller instances, their connections etc)
grouping efforts and TMD (Test Manufacturing Data) re-
ii. Functional timing closed frequency on each of the
spins due to human errors.
clock domains
iii. Details on interacting domains along with fencing
1. Introduction and Background information (which can be extracted from ATPG
tools)
a. At-Speed Structural Test iv. Number of nodes / faults per clock domains
At-speed Structural Test (ASST) or widely known as (which can be extracted from ATPG tools)
Transition Delay Test, performs structural logic tests at the
functional frequencies of the chip and thus screens for any b. Proposed Algorithm
delay or transition related defects during manufacturing. It An automated algorithm has been developed [1], which
helps in ensuring the quality of the shipped parts and can be understands the clock architecture, other design information
used for product performance sorting. and performs automated test grouping with first time correct
solution for efficient testing.
ASST tests on a large multi-domain chips are performed in
groups where a set of domains which qualifies the grouping i. Tabulate Clock Architecture Attributes For All
criteria are tested together and domains which cannot be Clock Domains (REFCLK, FREQUENCY,
tested together are tested under separate groups. Further the PLL_SOURCE, FENCING, CASCADING,
number of such domain groups must be kept optimum to SYNCHRONOUS, NODES)
optimize test timing, improve test effectiveness and test ii. Mark all Clock Domains with
power. UNPROGRAMMED Attribute and start with
putting all clock domains in a single “Test Group”
b. Importance of Clock domain grouping iii. Refine current “Test Group” based on
during ASST CASCADING, REFCLK, FREQUENCY,
Inefficient test grouping can result in higher test coverage PLL_SOURCE, SYNCHRONOUS, FENCING,
in some of the ASST test groups but may not give good NODES Attributes to separate out
coverage number for other test groups due to the pattern UNPROGRAMMED and PROGRAMMED
count constraints set. Also the number of groups must be Clock Domains
kept optimum otherwise it will have a huge impact on the iv. Repeat the process, till all the Clock Domains are
test time and test data volume which will impact the overall PROGRAMMED
test cost. The size of the groups should be chosen such that

Poster X INTERNATIONAL TEST CONFERENCE 1

3. Results
Experiments were performed on one OEM-ASIC design
with approximately 200M Gate Count, 12M Scanable
Flops, 400 Memories and 40 At-speed Clock Domains.

Manually combined test groups were made available from

the Design Centre Engineer. ATPG was performed with
manual test grouping and Automated Test Grouping by
above mentioned Algorithm. The following Table shows
the ATPG results for Launch-of-Shift (LOS) and Launch-
of-Capture (LOC) test modes.

With Manual Test With Automatic Test

Grouping Grouping
TestMode Total ASST DC Total ASST DC
Patterns (%) (%) Patterns (%) (%)
ASST
28036 91.33 97.94 22003 91.03 97.91
LOS
ASST
5071 93.51 98.56 3201 93.52 98.7
LOC

With Manual Test With Automatic Test

Grouping Grouping
TestMode Total Total Total Total
CPU Elapsed CPU Elapsed
Time Time Time Time
ASST LOS 15200 15520 16643 16988
ASST LOC 16080 16580 11160 11520

The following improvements in the results were observed

with almost same ASST coverage number.

TestMode Pattern Count CPU Time

ASST LOS 21.52% -0.09%
ASST LOC 36.87% 6.25%

It should be noted that both the experiments were performed

on same design (with same scan chain structures,
compression ratio etc.), thus reduction in pattern count
directly correlates to reduction in test application time and
test data volume. This reduction in test time directly
correlates to reduction in test cost.
4. Conclusion
Automated solution for test group creation analyses all the
design and grouping constraints and assures first time
correct test groupings which are test time efficient. The
optimized groupings reduces Pattern simulation time on
Simulator, Test Application time on tester and generation
time for the ATPG patterns. It also provides flexibility to
ATPG tool to target faults in complex design more
efficiently.
5. References
[1] H. Bhagat et al, “Auto Test grouping / clock sequencing
for At-speed Test”, US Patent Application US
2017/0108549 A1

Poster X INTERNATIONAL TEST CONFERENCE 2