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DT Chapter 1-3

Digital Techniques and Microprocessor (All India Shri Shivaji Memorial Society's College
of Engineering)

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Zeal Polytechnic Pune

Department of
Electronics & Telecommunication
Engineering

Digital Techniques
Subject Code: 22320
Course / Scheme: EJ3I

Faculty name: Prof. S. N. Navale

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Unit 1: Number Systems & Codes

We are familiar with the impact of modern digital computers,

communication systems, calculators, watches, etc. on society but we are not
familiar with the working principles of the above systems. The operation of
these systems is based on the principle of digital techniques and is referred
to as digital systems. One of the main causes of this revolution is the advent
of Integrated Circuits(IC’s), which became possible because of the
tremendous progress in semiconductor technology.

What is an Analog System ?

Electronic amplifiers are used to amplify electrical signals. These types

of signals are continuous signals and have any value in a limited range and
hence are known as analog signals. The electronic circuits used to amplify
these signals are known as analog circuits and the systems built around this
kind of operation are known as Analog Systems.

What is Digital System?

In an electronic calculator, input is given with the help of switches. This

is converted to electrical signals which have two discrete values i.e. either a
LOW level or HIGH level. Here the actual value of the signals immaterial as
long as it is within specified range of LOW or HIGH level. This type of
signal is known as digital signal. The electronic circuits inside the calculator
used to process these signals are known as digital circuits and the systems
built around this kind of operation are known as Digital Systems.

What are logic levels? Explain positive & negative logic.

HIGH
LOW

LOW
HIGH

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Positive Logic Negative Logic

In each of the two signals we observe that the voltage corresponding to a

given level is not fixed, rather voltages in a limited range are designated as
levels. As long as the voltage belongs to that level, it will be takn as that
level and the exact value of the voltage is immaterial.
For example any voltage in the range of 3.5 to 5V will be considered as
HIGH level in positive logic system and low leveling the negative logic
system. Similarly, voltage in the range 0-1V will be considered as LOW for
positive logic system and HIGH for negative logic system. Usually positive
logic system is used unless specified.
The two discrete signal levels HIGH & LOW can be represented by the
binary digits 1 & 0 respectively. A binary digit (0/1) is referred as a bit.
Since a digital signal can have only one of the two possible levels 1 or 0, the
binary number system can be used for analysis and design of digital systems.

What are advantages of Digital Circuits?

Some of the reasons for the wide spread use of digital techniques &
systems are:
1. The devices used in digital circuits generally operate in one of
the two states i.e. ON or OFF resulting in simple operation
2. There are very few basic operations which are easy to
understand.
3. Digital techniques require Boolean algebra which is very simple.
4. Digital circuits require basic concepts of electric network
analysis i.e. switching speed and loading characteristics only.
5. Large number of IC’s is available for performing various
operations. These are high reliable, accurate, small in size
with high speed operation.
6. Due to the availability of various logic families, optimization of
system design in
terms of power requirement & speed of operation is possible.
7. The effect of fluctuations in the characteristics of the
components, ageing of
components, temperature, noise, etc. is very small in digital
circuits.
8. Digital circuits have capability of memory which makes these
circuits highly
suitable for computers, calculators, watches, telephones, etc.

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9. The display of data and other information is very convenient,

accurate and elegant using digital techniques.
10.Almost all the electronic systems are digital in nature ,hence it
is one of the challenging fields.

List applications of Digital Systems.

The digital systems are extensively used in different areas of applications

such as:
1. Computation and data processing
2. Control systems
3. Process control
4. Used in communication
5. Used in instrumentation
6. Used in industrial automation
7. Used in biomedical engineering
8. Used in image processing

Compare Analog and digital systems.

Sr. Analog Systems Digital Systems

No
1. It uses analog signal It uses analog signal
2. It uses meter with pointer for It uses digital signal
display
3. It is greatly affected by noise. It is not much affected by
noise.
4. It has poor accuracy and It has better accuracy and
precision precision
5. It has no capability of memory It has capability of memory
6. It is not easy to design It is not easy to design
7. It is complex & costlier to It is easy& economical to
fabricate on chip fabricate on chip
8. It is not versatile It is versatile
9. The variety of operations are The variety of operations are
limited very large
10. It has more distortion It has less distortion
11. It has poor reliability It has poor reliability

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Give classification of Digital IC’S

Digital IC’s are classified based on the type of semiconductor devices
used i.e. bipolar & unipolar:

Digital IC’s

Bipolar Unipolar
logic logic
families families:
1. PMOS
2. NMOS
3. CMOS
Saturated: Unsaturated:
1. Resistor-Transistor logic (RTL) 1. Schottky TTL
2. Direct-Coupled transistor logic (DCTL) 2. Emitter-Coupled
3. Integrated-Injection logic (I2L) logic (ECL)
4. Diode-transistor logic (DTL)
5. High-threshold logic (HTL)
6. Transistor-transistor logic (TTL)

What is a Logic Family

A group of compatible IC’s with same logic level and supply
voltages for performing various logic functions have been fabricated using a
specific circuit configuration which is referred to as a logic family.

What are Bipolar Logic Families?

The main elements of bipolar IC are resistors, diodes, capacitors &
transistors.Since transistor is a bipolar device logic family is called as
bipolar.In saturated logic, the transistors in the IC are driven to saturation
and in unsaturated logic the transistors in the IC are not driven to
saturation.

What are Unipolar Logic Families?

The main element of unipolar IC is MOSFET. Since MOSFET is
unipolar device,logic family is termed as unipolar.In PMOS only p-channel
MOSFET’s are used and in NMOS only n-channel MOSFET’s are used. In

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CMOS both p-channel and n-channel MOSFET’s are employed on the same
Silicon chip.

Give the significance of 74,74H,74L,74S in IC numbering. (2 marks)

What are SSI,MSI,LSI,VLSI techniques?
Digital IC’s are classified either according to the complexity of the circuit,
as the number of gates required to build the circuit to accomplish the same
logic function or the number of components fabricated on the chip. The
classification is shown in table:

IC Classification Equivalent Number of

basic gates components
C Scale Integration (SSI)
Small Less than 12 Upto 99
h
Medium Scale Integration (MSI) 12-99 100-999
a
Large Scale Integration (LSI) 100-999 1000-9999
r
Very
a Large Scale Integration (VLSI) 1000-9999 10000-99999
c
Ultra
t Large Scale Integration (ULSI) 10000 or more 100000 and above
e

Give important Characteristics of Digital IC’s.

The various characteristics of digital IC’s used to compare their performance

are:

1. Speed of Operation:
The speed of a digital circuit is specified in terms of the propagation delay
time. The delay times are measured between the 50% voltage levels of the
input & output waveforms.
There are two delay times: tpHL, when output goes from high level to low
level and tpLH, corresponding to the output making a transition from low to
high state. The propagation delay time of the logic gate is taken as the
average of these two delay times.

2. Power Dissipation:
This is the amount of power dissipated in an IC. It is determined by the
current Icc that it draws from the Vcc supply and is given by
Vcc * Icc.
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Icc is the average value of Icc(0) and Icc(1). This power is specified in
terms of milliwatts.

3. Figure of Merit:
It is defined as the product of speed and power. The speed is specified in
terms of propagation delay time. A low value of speed-power product is
desirable.

Figure of merit = propagation delay time (nanoseconds) * power

(mW)
It is specified in pico joules (ns*mW=pJ).
In digital circuits if high speed is desired, then the power dissipation has to
be more.

4. Fan-Out:
This is the number of similar gates which can be driven by a gate. High
fan-out is advantageous because it reduces the need for additional drivers to
drive more gates.

5. Current & Voltage Parameters:

The following currents & voltages are specified which are useful in
the design of digital systems.
 High level input Voltage (VIH): This is the minimum input voltage
recognized by the gate as logic 1.
 Low level input Voltage (VIL): This is the maximum input voltage
recognized by the gate as logic 0.
 High level output Voltage (VOH): This is the minimum voltage
available at the output corresponding to logic 1.
 Low level output Voltage (VOL): This is the maximum voltage
available at the output corresponding to logic 0.
 High level input Current (IIH): This is the minimum input current that
must be supplied by a driving source corresponding to 1 level voltage.
 Low level input Current (ILH): This is the maximum input current
that must be supplied by a driving source corresponding to 0 level
voltages.
 High level output Current (IOH): This is the maximum current which
the gate can sink in 1 level.
 Low level output Current (IOH): This is the minimum current which
the gate can sink in 0 level.
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 High level supply Current (Icc (1)): This is the supply current when
the output of the gate is at logic1.
 Low level supply Current (Icc (0)): This is the supply current
when the output of the gate is at logic 0.

6. Noise Immunity:
Stray electric & magnetic fields may induce unwanted voltages,
known as noise, on the connecting wires between logic circuits. This may
cause the voltage at the input to either drop below VIH or rise above VIL
and may produce undesired operation. The circuit’s ability to tolerate noise
signals is referred to as the noise immunity. A quantitative measure of which
is called as noise margins.

7. Operating Temperature:
The temperature range in which the IC functions properly must be
known. The accepted temperature ranges are: 0 to 70°C for consumer and
industrial applications, -55°C to +125°C for military applications.

8. Power Supply Requirements:

The supply voltages and the amount of power required by an IC are
important characteristics required to choose the proper power supply.

9. Flexibilities Available:
Various flexibilities are available in different IC logic families and
these must be considered while selecting a logic family for a particular job.

Compare TTL, CMOS, ECL logic families.

Give any 4 charactristics of ECL family. (4 marks)
Compare CMOS & ECL families on basis of basic gates,noise
immunity,power dissipation,propogation delay. (4 marks)

Parameters Logic Families

TTL CMOS ECL
Basic Gate NAND NOR or NAND OR or NOR

Fan-out 10 or 20 20 or 50 25
Power dissipation(mW) 1-22 0.01 to 0.005 40-55

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Noise immunity Very Good Very Good Poor

Propagation delay(ns) 3 to 33 4.75 to 70 0.75 to 2

Figure of merit i.e.(Speed- 19 to 132 0.024 to 0.7 40 to 100
Power product) (pJ)

Clock Rate(MHz) for FF’s 3 to 125 10 to 100 60-600MHz

Available functions Very High High High

Give Base, Symbols & Example of various Number Systems.

These are widely used in digital systems like Microprocessor, logic

circuit, computers, etc and therefore the knowledge of these systems is
essential for understanding, analyzing and designing digital systems.
The information available in any form must be converted to binary form
before it is processed by digital circuits. To achieve this, a process of coding
is employed whereby each numeral, alphabet or special character is coded in
a unique combination of 0’s and 1’s using a coding scheme known as code.
This process of coding is known as encoding.

In any number system, there is an ordered set of symbols known as digits

with rules defined for performing arithmetic operations like addition,
subtraction, multiplication, etc. A collection of these digits makes a number
which in general has two parts – integer and fractional, set apart by a radix
point (.), i.e.
(N)b = dn-1 dn-2 dn-3……….d1 d0 . d-1 d-2…………d-f……d-m
where:
N = a number
b = radix or base of the number system
n = number of digits in integer portion
m = number of digits in fractional portion
dn-1 = most significant digit (msd)
d-m = Least significant digit (lsd)

and 0 < (di or d-f) < b-1

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The digits in a number system are placed side by side and each position
in the number is assigned a weight or index of importance by some
predesigned rule. Following are the details of commonly used number
systems:

Number Base Symbols Used Weight Assigned to Example

System or (di or d-f) position
Radix i -f
(b)
Binary 2 0,1 2i 2-f 0011.11
8 0,1,2,3,4,5,6,7 8i 8-f 5567.25
Octal
10 0,1,2,3,4,5,6,7,8, 10i 10-f 3974.57
Decimal 9
16 0,1,2,3,4,5,6,7,8, 16i 16-f 3FA9.56
Hexadecimal 9,
A,B,C,D,E,F

Explain Binary Number System. What is Bit, Nibble, Byte?

The number system with base two is known as binary number

system. Only two symbols are used to represent this system i.e. 0 and 1.
These are known as bits. This system has minimum base (0 is not possible
and 1 is not useful). It is a positional system i.e. every position is assigned a
specific weight. The left most bit is the most significant bit (MSB) and the
right most bit is the least significant bit (LSB). Any number of 0’scan be
added to the left of the number without changing the value of the number.

In binary number system, a group of four bits is called as nibble

and a group of eight bits is known as a byte.
Following table gives the 4-bit binary numbers and their corresponding
decimal numbers:

Binary Decimal
number Number
B3 B2 B1 B0 D1 D0
0 0 0 0 0 0

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0 0 0 1 0 1
0 0 1 0 0 2
0 0 1 1 0 3
0 1 0 0 0 4
0 1 0 1 0 5
0 1 1 0 0 6
0 1 1 1 0 7
1 0 0 0 1 8
1 0 0 1 1 9
1 0 1 0 1 0
1 0 1 1 1 1
1 1 0 0 1 2
1 1 0 1 1 3
1 1 1 0 1 4
1 1 1 1 1 5

Explain Binary to Decimal Conversion process.

To differentiate between numbers represented in different number

systems, either the corresponding number system may be specified
alongwith the number or a small subscript at the end of the number may be
added signifying the number system.
Example1. Find decimal equivalent of binary number (11111)2 .
= (1*24+1*23+1*22+1*21+1*20)
= 16 + 8 + 4 + 2 + 1
= (31)10
Example2. (0.10101)2
= (1*2-1+0*2-2+1*2-3+0*2-4+1*2-5)
= 0.5 + 0 + 0.25 + 0 + 0.03125
= (0.65625)10

Explain Double-dabble method or Decimal to Binary Conversion.

Any decimal number can be converted to its equivalent binary
number. For integers, the conversion is obtained by continuous division by 2
and keeping the track of remainders, while the fractional part the conversion
is affected by continuous multiplication by 2 and keeping track of the
integers generated.

Example1. Express (25.5)10 in binary form.

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Integer part
Quotient Remainder
25 / 2 12 1
12 / 2 6 0
6/2 3 0
3/2 1 1
1/2 0 1

(25)10 = (11001)2
Fractional Part

0.5 * 2 = 1.0
(0.5)10 = (1)2

(25.5)10 = (11001.1)2

What is Sign Magnitude representation ?

In a decimal number system, a plus (+) indicates positive number and a
minus (-) indicates a negative number. This representation is known as
signed number.
In Binary system ,an additional bit is used as the sign bit and is placed as the
MSB. A ‘0’ represents a positive number and a ‘1’ represents a negative
number. This type of representation for signed numbers is known as sign
magnitude representation.

Example1. Find the decimal equivalent of 1111 & 0111 and represent its
sign magnitude:

(1111)2 = (-7)10

(0111)2 = (+7)10

What is One’s Complement representation?

If a larger negative number is to be added or subtracted from smaller

number, it is very difficult. Hence, the positions of subtrahend and minuend
are to be interchanged for subtraction. This method will require two separate
circuits for addition and subtraction, hence not used in digital electronics or
computers.

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1’s and 2’s complement methods have the advantage that the circuits
which perform binary addition can also perform subtraction.
In a binary number, if each 1 is replaced by a 0 and each 0 by 1, the
resulting number is known as One’s complement of the first number. In fact
both the numbers are complement of each other. If one number is positive
then the other number will be negative with the same magnitude and
vise-versa. This method is widely used for representing signed numbers.

Example1. Find one’s complement of 11011010

= 00100101

Explain Two’s Complement representation.

If one is added to 1’s complement of a binary number, the resulting

number is known as two’s complement of the binary number. It is observed
that 2’s complement of the 2’s complement of a number is the number itself.

Example1. Find 2’s complement of 01001110

1’s complement = 10110001
Add 1 = + 1
10110010

What is Binary Arithmetic? Explain binary addition, subtraction.

We are familiar with arithmetic operations such as addition, subtraction,
multiplication &division in decimal numbers. Similar operations can be
performed on binary numbers. It is termed as Binary arithmetic.

1. Binary Addition

Rules of binary addition are given in tabular form below:

Augend Addend Sum Carry Results

0 0 0 0 0
0 1 1 0 1
1 0 1 0 1
1 1 0 1 10

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In the first three rows above, there is no carry i.e. carry=0, whereas in the
fourth row a carry=1, and similar to decimal addition, it is added to the next
higher binary position.

Example1.
Addition of binary numbers: 1 0 1 1
(+) 1 1 1 1
10 1 1 0

2. Binary Subtraction
Rules of binary Subtraction are given in tabular form below:

Minuend Subtrahend Difference Borrow

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Except in the second row, borrow=0. When Borrow=1, as in second row,

this is to be
subtracted from next higher binary bit as in decimal subtraction.

Example1.
Subtraction of binary numbers: 1 0 1 1
(-) 0 1 1 0
0 1 0 1

Explain procedure for Subtraction using One’s Complement.

The following procedure is used for subtraction using 1’s complement:

1. Find 1’s complement of the binary number to be subtracted i.e.

subtrahend

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2. Add this subtrahend to the minuend.

3. If carry is generated in MSB, then transfer it to the extreme
right position. This is called end around carry (EAC).
4. Add this EAC to the remainder. Ignore the carry 1 in its
original position.
5. If there is no EAC, the answer is negative and it is in the 1’s
complement form, while the answer is positive if there is a carry.

Example1.
(13) – (12) = 1 1 0 1 1101
(-) 1 1 0 0 1’s Complement of 12= + 0 0 1 1
00 0 1 Carry 1 0000
+ 1
0001

Explain Subtraction using Two’s Complement method.

It is possible to use the circuits designed for binary addition to

perform binary subtraction if the problem of subtraction is changed to that of
addition. This concept eliminates the need for additional circuits for
subtraction. This makes the design of arithmetic circuits very convenient &
cheaper. Hence 2’s complement is used for the same. The problem of EAC
and the ambiguity of positive and negative numbers in 1’s complement is
overcome by using this method.
Binary Subtraction is performed by adding the 2’s complement
of the subtrahend to the minuend. The procedure is as below:

1. Find 1’s complement of the binary number to be subtracted i.e.

subtrahend.
2. Add 1 to the above and get 2’s complement of the number.
3. Add the two numbers. If a final carry is generated, discard it
and the answer is given by the remaining bits which is positive.
If the carry is 0, then the answer is negative & it is in 2’s
complement form.

Example1. (7) - (5)

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0 1 1 1 Minuend
(+) 1 0 1 1 2’s complement of subtrahend
1 0 0 1 0
Discard Final carry and the answer is 0010.

What is an Octal Number System?

The number system with base 8 is known as octal number

system. In this system eight symbols 0, 1, 2, 3, 4, 5, 6, 7 are used to
represent numbers. Similar to decimal & binary number systems, it is also a
positional system. It is inconvenient to handle long strings of binary
numbers. Hence, octal numbers are used for entering the binary data & can
be efficiently used in microprocessors and other digital circuits.

Octal Decimal Binary

0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 1
2 2 0 0 0 0 1 0
3 3 0 0 0 0 1 1
4 4 0 0 0 1 0 0
5 5 0 0 0 1 0 1
6 6 0 0 0 1 1 0
7 7 0 0 0 1 1 1
10 8 0 0 1 0 0 0
11 9 0 0 1 0 0 1
12 10 0 0 1 0 1 0
13 11 0 0 1 0 1 1
14 12 0 0 1 1 0 0
15 13 0 0 1 1 0 1
16 14 0 0 1 1 1 0

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How to convert an Octal number to Decimal number?

Example1. (6327.4051)8
= (6*8 )+ (3*8 )+ (2*81)+ (7*80)+ (4*8-1)+ (0*8-2)+ (5*8-3)+(1*8-4)
3 2

= (3072 + 192 + 16 + 7 + 4/8 + 0 + 5/512 + 1/4096 )

= (3287.5100098)10
Thus, (6327.4051)8 = (3287.5100098)10

Give procedure to convert Decimal number to Octal number.

It is similar to conversion process for base-10 to base-2. The only

difference is that number 8 is used in place of 2 for division in case of
integers and for multiplication in case of fractional numbers.

Example1. Convert (3287.5100098)10 into Octal

Integer part
Quotient Remainder
3287 / 8 410 7
410 / 8 51 2
51 / 8 6 3
6/8 0 6
(3287)10 = (6327)8

Fractional Part
0.5100098 * 8 = 4.0800784 4
0.0800784 * 8 = 0.6406272 0
0.6406272 * 8 = 5.1250176 5
0.1250176 * 8 = 1.0001408 1
(0.5100098)10 = (0.4051)8

(3287.5100098)10 = (6327.4051)8

How to convert Octal number to Binary number?

It can be converted by replacing each octal digit by its 3-bit
equivalent binary.
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Example1. (52)8 = (101 010)2

Example2. (736)8 = (111 011 110)2

Explain Binary to Octal Conversion.

It can be converted by making group of three bits starting
from LSB and moving towards MSB for integer number and then replacing
each group of three bits by its octal representation. For fractional part, the
groupings of three bits are made starting from binary point.
Example1. (111 110 001.100 110 011 010)2 = (761.4632)8

Example2. (011 001 110 001.000 101 111 001)2 = (3161.0571)8

Explain base & symbols used in Hexadecimal Number System.

The base for hexadecimal number system is 16 which require
16 distinct symbols to represent the numbers. These are numerals from 0-9
and alphabets A-F, hence known as alphanumeric number system. The
binary and decimal equivalent of hexadecimal numbers is shown in the table
below.

Hexadecimal Decimal Binary

0 0 0 0 0 0
1 1 0 0 0 1
2 2 0 0 1 0
3 3 0 0 1 1
4 4 0 1 0 0
5 5 0 1 0 1
6 6 0 1 1 0
7 7 0 1 1 1
8 8 1 0 0 0
9 9 1 0 0 1
A 10 1 0 1 0
B 11 1 0 1 1
C 12 1 1 0 0
D 13 1 1 0 1
E 14 1 1 1 0
F 15 1 1 1 1
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Show an example of Hexadecimal to Decimal Conversion.

Example1. (3A.2F)16 = (3*161)+ (10*160)+ (2*16-1)+ (15*16-2)

= 48 + 10 + 2/16 + 15/256
= (58.1836)10
The fractional part may not be an exact equivalent and may give a small
error.

Show Decimal to Hexadecimal Conversion with an example.

It is similar to conversion process for base-10 to base-2. The only
difference is that number 16 is used in place of 2 for division in case of
integers and for multiplication in case of fractional numbers.

Example1. Convert (95.5)10 into Hexadecimal

Integer part
Quotient Remainder
95 / 16 5 15
5 / 16 0 5
(95)10 = (5F)16
Fractional Part

0.5 * 16 = 8.0 8
(0.5)10 = (8.0)16

(95.5)10 = (5F.8)16

How to convert Hexadecimal number to Binary number?

It can be converted by replacing each hex digit by its 4-bit
equivalent binary.

Example1. (2F9A)16 = (0010 1111 1001 1010)2

Show Binary to Hexadecimal Conversion.

State the rules for Binary to Hexadecimal Conversion. (2 marks)
It can be converted by making group of four bits starting from
LSB and moving towards MSB for integer number and then replacing each

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group of four bits by its hexadecimal representation. For fractional part, the
groupings of four bits are made starting from binary point.

Example1. (0010 1001 1010 1111)2 = (29AF)16

Example2. (0.0001 1110 1011 0100)2 = (0.1EB4)16

Show Hexadecimal to Octal and Octal to Hexadecimal Conversion.

Hexadecimal numbers can be converted to equivalent octal
numbers and octal numbers can be converted to equivalent hex numbers by
converting the hex/octal number to its equivalent binary and then to
octal/hex respectively.

Example1. (A72E)16 = (1010 0111 0010 1110)2

= 001 010 011 100 101 110
= (123456)8

Example2. (247.36)8 = (010 100 111 . 011 110)2

= (0 1010 0111 . 0111 1000)2
= (A7.78)16

What are Binary Coded Decimal (BCD) Numbers?

In this code, decimal digits 0-9 are represented by their natural
binary equivalents using four bits and each decimal digit of a decimal
number is represented by this four bit code individually. It is a very
convenient and useful code for input and output operations in digital
systems. To simplify the communication process between man and machine,
BCD codes are used.
There are several types of BCD codes. They are weighted codes. The
weighted codes may be either positive or negative. There are 17 positively
weighted BCD codes. Excess-3 is a non weighted code.
This code is also known as 8-4-2-1 code because 8, 4, 2 and 1 are the
weights of the four bits of binary code of each decimal digit similar to binary
number system. Therefore, it is a weighted code and arithmetic operations
like addition and subtraction are required to be performed using this code.
Encoding is the procedure for representing each of ten symbols 0, 1, 2……9
in decimal number system by a unique combination of the symbols (0 and 1)
of the binary system. It is usually used in calculators. BCD code for decimal
digits 0-9 are given in the below table.
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Decimal BCD (Binary Coded Decimal)

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Encoding is the procedure for representing each of ten symbols 0, 1,

2……9 in decimal number system by a unique combination of the symbols
(0 and 1) of the binary system.BCD arithmetic is rather complex in
comparison to binary arithmetic. Therefore, BCD arithmetic requires more
hardware and results in reduction of speed. Also more number of bits is
required to represent a given BCD number. However, digital calculators use
BCD because the input data from the keyboard as well as the output display
are digital. It is used in digital voltmeters, electronic calculators, digital
computers, arithmetic operations and simplification of binary number
system.
Explain BCD Addition.
State the rules of BCD addition. (2 marks)

In this, if the four bit sum output is not a valid BCD digit, or if a carry is
generated, then decimal 6 (0110 binary) is to be added to the sum to get the
correct result. The 4-bit binary adder IC (7483) can be used to perform
addition of BCD numbers.

Example1. (7+5)

Binary value of 7= 0111

Binary value of 5= + 0 1 0 1
1 1 0 0 => Invalid BCD Number
+ 0 1 1 0 => Add (6) i.e 0110
10010
Thus, Ans.= (0001 0010)2

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Example2. 6468 + 4938

0110 0100 0110 1000

+0 1 0 0 + 1001 + 0011 +1000
1010 1101 1010 0 0 0 0 =>InvalidBCD
+0110 +0110 + 0110 + 0 1 1 0 =>Add (6)
10001 0100 0000 0110

Thus, Ans: (0001 0001 0100 0000 0110)2 = (11406)10

Explain BCD Subtraction.

In this, nine’s complement of the subtrahend is added to the minuend.

The nine’s complement of a BCD number is given by nine minus that
number.

Example1. 9-5
9 = 1001
+ (-5) = 0 1 0 0 => (nine’s complement, 9-5 = 4 = 0100)
1 1 0 1 => (Invalid BCD)
+ 0 1 1 0 => (Add Six i.e 0110)
1 0011
+ 1 => (Add end around carry)
0100

Questions:

1. Compare Analog and digital signals.

2. What are the advantages of digital systems?

3. Tabulate the decimal numbers from 0 to 15 for binary, octal and

hexadecimal numbers.

4. Convert the following numbers to their binary, octal and hexadecimal

equivalents: (2 marks each)
(a). (3461)10 (b). (0.4375)10 (e).(49.25)10
(c). (25.625)10 (d). (23.3)10 (f).(15)10

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5.Convert following binary numbers to their decimal, octal and hexadecimal

equivalents: (2 marks each)
(a) (110011)2 (b) (0.110)2 (c) (1011.110)2
(d) (110011.101)2 (e) (1101001.110)2 (f) (10110)2
(g) (0.1011)2

6.Convert following Octal numbers to their decimal, binary and

hexadecimal equivalents: (2 marks each)
(a) (174)8 (b) (126) 8
(c) (23.6) 8 (d) (0.65) 8

7. Convert following hexadecimal numbers to their binary, octal and

decimal equivalents: (2 marks each)
(a) (ADD)16 (c) (DAD) 16 (e) (5C7)16

(b) (BAD) 16 (d) (FFFFF) 16 (f) (6AC)16

8. Perform binary operations using 2’s complement method:

(a) (110101)2 – (10101) 2 (4 marks each)
(b) (1010) 2 + (1100) 2
(c) (46)8 – (3A)16
(d) (101)2 – (011) 2
(e) (1010)2 – (1101) 2

9.What are the advantages and disadvantages of BCD code?

10. Perform BCD operations for the following numbers:

(a) 132 + 59 (4 marks each)
(b) 78 + 12
(c) 570 + 630
(d) 77 - 39
(e) 353 – 217
(f) 750 - 490
(g) 24-19
(h) 12 + 9
(i) 57+26

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Unit 2: Logic Gates & Boolean Algebra

Introduction:

In a digital system there are only a few basic operations performed,

irrespective of the complexities of the system. These operations are required
to be performed a number of times in large digital systems. The basic
operations are AND, OR, NOT and flip-flop.

What is a Logic Gate? [2 Marks]

A logic gate performs a logical operation on one or more logic inputs and
produces a single logic output. The logic normally performed is Boolean
logic and is most commonly found in digital circuits. Logic gates are
primarily implemented electronically using diodes or transistors, but can
also be constructed using electromagnetic relays, fluidics, optics, molecules,
or even mechanical elements. The term gate is used because of the similarity
between a gate and digital circuit.

Define Truth Table. [2 Marks]

A truth table is a table that describes the behavior of a logic gate. It lists the
value of the output for every possible combination of the inputs and can be
used to simplify the number of logic gates and level of nesting in an
electronic circuit. Therefore, any logical expression can be defined in the
form of truth table containing all possible input combinations.

Draw Symbol, Truth table and Logical Expression for gates given
Below. Each gate for 2 Marks.
Explain AND Operation.

AND gate has N inputs (N>2) and one output. Digital signals are applied at
the input terminals marked A, B…N and the output is obtained at the output
terminal marked as Y.
The AND operation is defined as “the output is 1 if and only if all the
inputs are 1”.
Truth table for a two input AND gate is as shown below. Mathematically, it
is written as:
Y = A AND B “Y equals A AND B”

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=A.B

The symbol of AND gate is shown below.

Explain OR Operation.

The OR operation is defined as “the output of an OR gate is 1 if

and only if one or more inputs are1”.
Its logical expression is given by:
Y = A OR B “Y equals A OR B”
Y = A + B.
The symbol of OR gate is shown below.

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What is a NOT gate/inverter ? Explain it’s working using Truth table,

Symbol.
NOT gate is also known as an inverter. It has one input and one
output. Its logic equation is:

Y = NOT A “Y equals NOT A”

Y=Ā
The output of NOT gate is always opposite of the input.

The symbol of NOT gate is shown below.

Which gates are Universal Gates? Why?

NAND and NOR logic gates are the called the universal gates
because all other types of Boolean logic gates (i.e., AND, OR, NOT, XOR,

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XNOR) can be created from a suitable network of just NAND or just NOR
gate(s).

Explain NAND Operation.

The NOT-AND operation is known as NAND operation. Here the

bubble on the output side of the NAND gate represents NOT operation,
inversion or complement.
The output of NAND gate is logic 1 ,when one of the inputs is logic 0.
It is represented as:
Y = A NAND B “Y equals NOT (A AND B)”
Y = A.B

The symbol of NOT gate is shown below.

Show how NAND gate works as Universal gate. [S-04, W-05,

W-06,W-07, S-08, W-10, W-12] [4 Marks]

1) NOT gate using NAND:

a)All NAND input pins are connect to the input signal A gives an output
A’.

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b)One NAND input pin is connected to the input signal A while all other
input pins are connected to logic 1. The output will be A’.

2) AND gate using NAND:

An AND gate can be replaced by NAND gates as shown in the figure
(The AND is replaced by a NAND gate with its output complemented by
a NAND gate inverter).

How can you connect NAND gates to get an OR gate ? (2 marks)

3) OR gate using NAND:
An OR gate can be replaced by NAND gates as shown in the
figure (The OR gate is replaced by a NAND gate with all its inputs
complemented by NAND gate inverters).

Why NOR gate is called as universal gate? (2marks)

Explain NOR gate .Also show how it works as Universal gate.

The NOT-OR operation is known as NOR operation. Here the

bubble on the output side of the NOR gate represents NOT operation,
inversion or complementation. It is represented as:
Y = A NOR B “Y equals NOT (A OR B)”

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Y = A+B

The symbol of NOR gate is shown below.

1)Inverter Using NOR Gate :

The figure shows two ways in which a NOR gate can be used as an
inverter (NOT gate).

a) All NOR input pins are connected to the input signal A ,gives an output
A’.

b) One NOR input pin is connected to the input signal A while all other
input pins are connected to logic 0. The output will be A’.

2) OR gate using NOR Gates :

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An OR gate can be replaced by NOR gates as shown in the figure (The

OR is replaced by a NOR gate with its output complemented by a NOR gate
inverter).

3) AND gate using NOR Gates :

An AND gate can be replaced by NOR gates as shown in the figure (The
AND gate is replaced by a NOR gate with all its inputs complemented by
NOR gate inverters)

What is an EX-OR Operation?Explain with truth table,symbol &

equation.
For 2 input Ex-OR gate.Draw it’s symbol.Write truth table.
(2 marks)

The Exclusive-OR operation is widely used in digital circuits. It

can be performed using basic gates – AND, OR and NOT or universal gates
NAND or NOR. The circuit finds application where two signals are to be
compared. It is observed that when both the inputs are same, the output
is 0. It is represented as:
Y = A EX-OR B “Y equals A EX-OR B”
Y=

The symbol of Ex-OR gate is shown below.

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Applications of EX-OR gate :

EX-OR gate is widely used in parity generator, binary to gray convertor,

adder and subtractor circuits, etc.

Explain EX-NOR gate with truth table and symbol.

Draw the symbol for 2 input Ex-NOR gate,write truth table & logical output
equation. (4 marks)

The NOT EX-OR operation is known as EX-NOR operation. Here the

bubble on the output side of the EX-NOR gate represents NOT operation,
inversion or complement. It is represented as:
Y = A EX-NOR B “Y equals A EX-NOR B”
Y=

The symbol of Ex-NOR gate is shown below.

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Basic laws of Boolean Algebra:

The digital signals are discrete in nature and can only assume one
of the two values i.e. 0 or 1. A number system based on these two digits is
known as binary number system. Rules were developed for manipulations of
binary variables, known as Boolean algebra. Binary variables can be
represented by a letter symbol such as A, B, X, Y,… The variable can have
only one of the two possible values at any time i.e. 0 or 1.

The rules of Boolean algebra are different from those of

conventional algebra in the following manner:
1. Symbols used in Boolean algebra do not represent numerical
values.
2. Logical operations are performed in Boolean algebra and operations
are not Arithmatic operations.
3. It allows only two possible values for any variable.

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State & explain De Morgan’s Theorems (4 marks)

Two theorems suggested by De-Morgan which are widely used in

Boolean algebra:

Theorem 1:

It states that the complement of input product is equal to the sum of

complemented input. The LHS of the theorem represents a NAND gate
with inputs A and B whereas RHS of the theorem represents an OR gate
with inverted inputs (bubbled OR).

NAND = Bubbled OR
Theorem 1 Theorem 2
A B A.B + A+B

0 0 1 1 0 1 1 0 1 1

0 1 1 0 0 1 1 1 0 0

1 0 0 1 0 1 1 1 0 0

1 1 0 0 1 0 0 1 0 0
A.B=A+B

Give expression for De-Morgan’s second theorem. (2 marks)

Theorem 2:

It states that the complement of input sum is equal to the product of

complemented input. The LHS of the theorem represents a NOR gate with
inputs A and B whereas RHS of the theorem represents an AND gate with
inverted inputs (bubbled AND).
NOR = Bubbled AND
A+B=A.B

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State Commutative laws.

It allows the change of position of OR and AND variables. Thus,

1. A+B = B+A
2. A.B = B.A

State Associative laws:

It allows grouping of variables. Thus,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

State Distributive laws:

It states that factoring or multiplication of different terms in an expression is
allowed. Thus,
1. A.(B+C) = AB + AC
2. A+(B.C) = (A+B).(A+C)
3.

State Idempotence laws:

Idempotence means the same value. Thus,
1. A.A=A
2. A+A=A

State Negation laws:

It is expressed as:
1. =0 2. =1

State Double Negation laws:

It is expressed as:

A =A

State Identity laws:

It is expressed as:
1. A.1=A
2. A+1=1

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State Null laws:

It is expressed as:
1. A.0=0
2. A+0=A

State Absorption laws:

It is expressed as:
1. A+(A.B) =A
2. A.(A+B) =A

State Transposition Theorem:

It is expressed as:

State Duality Theorem.

It states that in a two valued boolean algebra the “Dual” of an

algebraic expression can be obtained by:
1. Interchanging OR and AND signs
2. Interchanging 0 and 1

Theorems related in this way are called as Duality theorems.

The Boolean algebraic theorem/ laws are summarized in below table:

Sr No. Theorem
1. A+0=A
2. A*1=A
3. A+1=1
4. A*0=0
5. A+A=A
6. A*A=A
7. A+A=1
8. A*A=0
9. A * (B+C) = AB + AC
10. A + BC = (A+B)(A+C)
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11. A + AB = A
12. A(A+B) = A
13. A + AB = (A+B)
14. A(A+B) = AB
15. AB + AB = A
16. (A+B)(A+B) = A
17. AB + AC = (A+B)(A+C)
18. (A+B)(A+C) = AC + AB
19. AB + AC + BC = AB + AC
(A+B)(A+C)(B+C) =
20.
(A+B)(A+C)
21. A.B.C….. = A + B + C
22. A+B+C+….. = A . B . C. …..

Specify characteristics of 74LS family .

Define Fan in & propogation delay related to logic families.

(2 marks)

The characteristics of TTL family are given below.

 Supply: 5V ±0.25V, it must be very smooth, a regulated supply is best.

In addition to the normal supply smoothing, a 0.1µF capacitor should be
connected across the supply near the IC to remove the 'spikes' generated as it
switches state, one capacitor is needed for every 4 ICs.
 Inputs 'float' high to logic 1 if unconnected, but do not rely on this in a
permanent (soldered) circuit because the inputs may pick up electrical noise.
1mA must be drawn out to hold inputs at logic 0. In a permanent circuit it is
wise to connect any unused inputs to +Vs to ensure good immunity to noise.
 Outputs can sink up to 16mA (enough to light an LED), but they can
source only about 2mA. To switch larger currents you can
connect a transistor.
 Fan-out: one output can drive up to 10, 74LS inputs, but many more
74HCT inputs.
 Gate propagation time: about 10ns for a signal to travel through a gate.

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 Frequency: up to about 35MHz (under the right conditions).

 Power consumption (of the IC itself) is a few mW.

Some of the available IC gates are:

 7400 quad 2-input NAND

 7403 quad 2-input NAND with open collector outputs
 7408 quad 2-input AND
 7409 quad 2-input AND with open collector outputs
 7432 quad 2-input OR
 7486 quad 2-input EX-OR
 74132 quad 2-input NAND with Schmitt trigger inputs

Questions:
1. List the various types of gates along with Boolean expression and logical
symbols.

2. State Demorgan’s theorem and prove it.

3. Design AND, OR and NOT gates using NOR gates

4. Design AND, OR and NOT gates using NAND gates.

5. Write any eight boolean laws

6. What do you mean by universal gates? Why are they so called?

Explain how NAND can be used as an Universal gate.

7. Implement EX-OR gate using NAND and NOR.

8. Design 3 input OR gate and 4 input NAND gate.

9. What are the TTL IC numbers for NOT, AND, NOR,

NAND, EX-OR and OR gates?

10. Draw logic circuit for the following expression:

(a). (b).
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(c). Y = AB + BC + CA (d) Y=ABC

(e) Y=(A+B)(C+D)
11. Construct logic circuit for the below equation using basic gates
only: (4 marks each)
(a). Y= AB+A.B+A.B
(b). T = XYZ + XZ
(c).
12. Design logic circuit for following expression using Universal gates:
(a).
(b).
(c).
(d). Y = AB + AC + BC

13. Realize using only NAND gates ,Y=(AB+BC)C.

14. Prove the following logic expression using Boolean algebra:

(a). AB + CD = (A+C) (A+D) (B+C) (B+D)

(b).

(c). (A+B+AB)(A+B)(A . B )=0

(d). AB+ABC+AB = A

(e). A B C + A BC+ AB = A C+ AB

15. For F= X Y +X Y ,find complement of F.

16. Simplify
(a)Y=(A+B)(A+C)
(b)Y=XY+XYZ+XYZ+XZ Y
(c)Y=A(A+C)(A B+C )
(d)Y=A B(D + D C )+(A+DAC)B
(e)Y=ABC+A B C +A B C
(f)Y=A B +A B +AB+ A B
(g)Y=A B C + A BC +ABC

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(g)Y=(AB+C)(AB+D)

18. Prove that OR-AND configuration is equivalent to a NOR-NOR

configuration.

Unit 3: Combinational Logic Design / Circuits

Introduction:
Digital circuits are divided in two broad categories:

What are Combinational Circuits?

What is the difference between combinational & sequential circuits.
(4 marks)

The circuits in which the outputs at any instant of time depend

on the inputs present at that instant of time are combinational circuits.
This means that there is no memory in these circuits. The design
requirements of combinational circuits may be specified in one of the
following ways:
 A set of statements
 Boolean expression
 Truth table
The aim is to design a circuit using gates or minimum components
to ensure low cost, saving in space, power requirements, etc. There can be
two different approaches to design combinational circuits. One of these is
the traditional method, wherein the given Boolean expression or truth table
is simplified using the standard methods and the simplified expression is
realized using gates. The other method does not require any simplification,
instead the complex logic functions available in MSI and LSI circuits.

The following methods can be used to simplify the Boolean

function:
(a). Algebraic method:
(b). Karnaugh map technique:
It is the simplest and commonly used method. It can be
used up to 6 variables.
(c). Variable entered mapping (VEM)
(d). Quine-McCluskey method

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What are Sequential Circuits?

In this circuit, the output at any instant of time depends upon

the present input as well as the past input/output are called as
sequential circuits. This means that there are elements used to store past
information known as memory elements. A sequential logic system may
have combinational logic sub-system.

What is Standard Representation for Logical functions?

The values assumed by the logical functions as well as the logical

variables are in the binary form. Any logic function can be expressed in the
following forms:

1. Sum-of-products form (SOP)

2. Product-of-sums form (POS)

If each term in SOP and POS forms contains all the literals then
these are known as standard SOP and POS respectively. Each individual
term in standard SOP form is called as “minterm” and in standard POS form
as “maxterm”.

SOP form can be converted to standard SOP form by ANDing the

terms in the expression with terms formed by ORing the variable and its
complement which are not present in that term. For a three variable
expression with variables A, B and C, if there is a term A, where B and C
variables are missing, then we form two terms (B+B) and (C+C) and AND
them with A. Therefore, we get

POS form can be converted to standard POS form by ORing the

terms in the expression with terms formed by ANDing the variable and its
complement which are not present in that term. For a three variable
expression with variables A, B and C, if there is a term A, where B and C
variables are missing, then we form two terms (B.B) and (C.C) and OR them
with A. Therefore, we get

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The following table gives the minterms & maxterms for a four variable
logical function where the number of minterms as well as maxterms is 16.

Each minterm is represented as mi where i is the decimal equivalent of

the natural binary number corresponding to the minterm with normal
variables taken as 1’s and the complemented variables as 0’s.

Each maxterm is represented as Mi where i is the decimal equivalent of

the natural binary number corresponding to the minterm with
uncomplemented variables taken as 0’s and the complemented variables as
1’s.

How are Minterm and Maxterm obtained?

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KARNAUGH MAP REPRESENTATION OF BOOLEAN FUNCTIONS:

Concept:
The Karnaugh map is similar to Venn diagram, in the sense that a diagram of
unit area is divided to sub-areas. A Boolean function in algebraic form is normally
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represented in the form of truth table. It may also be represented graphically in a map
called Karnaugh map or K-map.
The information contained in the K-map is identical with that given in the truth
table. This map gives the true or false (1 or 0) values of Boolean functions for a
possible combinations of its variables. Thus, a Karnaugh map, is a graphical method
for representing a Boolean function in a truth table (or a variable) in POS or SOP
form. The Karnaugh map, hence after is called K-maps. K-maps are used in
simplifying Boolean functions into standard (or canonical) form prior to minimization
process. It can be used up to six variables but normally it us used up to four variables.
There are many ways in which a k-map can be arranged.

The most important considerations of arranging terms in a K-map are:

1. There must be a unique location on the K-map for entering the true/false value
of the function corresponding to each possible combinations of input variables
(minterm or maxterm)

2. The locations should be arranged in a manner that is convenient to allow the

reduction of the Boolean function. This means that a proper mapping arrangement
should lead to groups of minterms and maxterms which give reduced forms.

Applications of K-map :

1. It is very useful in minimizing Boolean functions.

2. It is useful in expanding the Boolean function into canonical (or standard)
form prior to minimization process.
3. It is used to simplify the logic circuits.

Advantage of K-map:

The advantage of K-map is that it is very much useful to represent

Boolean functions with less than six variables and more convenient for
functions having four or less variables.

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Disadvantage :

The disadvantage of K-map is that it is difficult to handle, if the number of

Boolean variables exceed six.

Representation of Truth Table on K-maps:

(a)Two variables K-maps :

We take the example of the truth table shown below. It is required to construct
the K-map for this.

Y = A B + AB
= m2 + m3
Or Y =  2,3
On a K-map, 1 is placed in locations corresponding to minterms 2 and 3, while
0 is placed in all other locations in Fig.

Procedure to fill 2 Variable K – Map :

1. Draw K-Map as shown in fig 1 with the marking variables A, , B & as

shown in figure a.
2. Mark each cell by its equivalent Gray Code as shown in figure b.
3. Fill up the cell with “1”corresponding to Y=1.(Given by truth table).
4. Fill up the remaining cells with“0” shown in fig.

For output 1’s is in the truth table. The first 1 output to appearing for the input
of A =1 and B = 0. The fundamental product for this is AB. Now enter 1 on the
K-map as shown in fig. 1-b This 1 represents the product of AB because 1 is in
the A row and the B column. Similarly, the truth table has an output 1
appearing for inputs A = 1 and B = 1. The fundamental product for this is AB.
When we enter 1 on the K-map to represent AB, we get the map of Fig. 1-c.
The final step in construction of the K-map is to enter 0’s in the remaining
spaces. These zeros mean fundamental products are not needed for the
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corresponding inputs A = B = 0 and A = 0 and B = 1. Fig. 1-d shows the

complete K-map for the truth table.
Thus, in case of two variables A and B, four combinations corresponding to
four minterms (or maxterms), m0, m1, m2, m3, need four locations on the K-
map as shown in Fig. These correspond to the four rows in the truth table. Here
again each box represents one minterm (or maxterm). The minterm designations
are shown in the corners of each box. 1 is placed in those boxes where
minterms are included and 0 is placed, where the minterms are absent or
excluded in order to map :
Y = A B + AB
= m2 + m3
Or Y =  2,3
On a K-map, 1 is placed in locations corresponding to minterms 2 and 3, while
0 is placed in all other locations in Fig.

Truth Table (for two variable )

Sr.No. INPUT INPUT OUTPUT

A B Y
1 0 0 0
2 0 1 0
3 1 0 1
4 1 1 1

Construction of 2 – variables K-map

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(c) Three variables K-maps :

Procedure to fill 3 Variable K – Map :

1. Draw K-Map as shown in fig 1 with the marking variables A, A ,B & B

C & C as shown in figure a.
2. Mark each cell by its equivalent Gray Code as shown in figure.
3. Fill up the cell with“ 1”corresponding to Y=1.(Given by truth table)
4. Fill up the remaining cells with “ 0”.
This order is not binary progression, instead it follows the Gray code order of
00, 01, 11 and 10. It is done so that only one variable changes from
complemented to uncomplemented form or vice versa.
Now look for output 1’s in Table. The fundamental products for these 1 outputs
are A B C , AB C and ABC. Enter these 1’s on the Karnaugh map as shown in
Fig. The final step is to enter 0’s in the remaining spaces as shown in Fig. this
K-map is useful because it shows the fundamental products needed for the sum-
of-products circuit.

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Thus, for three variables, A, B and C, eight combinations of 1’s and 0’s are
possible. So, there are eight terms (o to 7) as shown in Table. These eight
combinations corresponding to eight minterms (or maxterms) mo, m1, m2, m3,
m4, m5, m6, and m7 need eight locations on the K-map as shown in Fig.(a).
These correspond to four rows and two columns. The eight positions of
minterms (or maxterms) are indicated as 0 to 7 in the corner of each box.
1 is placed in those boxes whose minterms are included and 0 is placed where
minterms are absent. In order to map :
Y = A B C +AB C +ABC
= m2 + m6 + m7
Or Y = 2, 6, 7
On a K-map, 1 is placed in locations corresponding to minterms 2 and 3, while
0 is placed in all other locations.

Now consider a truth table given below for filling of three variables K _map.
Truth Table ( for three variable )

Sr. INPUT OUTPUT

No
A B C Y
0 0 0 0 0
1 0 0 1 0
2 0 1 0 1
3 0 1 1 0
4 1 0 0 0
5 1 0 1 0
6 1 1 0 1
7 1 1 1 1

Construction of 3-variables K-map:

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GROUPING OF ADJACENT VARIABLES:

Concept :
There is a way of using the K-map to get simplified logic circuits.
Simplification of Boolean functions with K-map is based on the principle of
combining terms in adjacent boxes. Two boxes are said to be adjacent, if they
differ in any one variable. The simplification of Boolean function is achieved
by grouping adjacent 1’s or 0’s in groups of 2 i, where i = 1, 2 ……….n, where
n is the number of variables.
Depending on the grouping 2, 4 and 8 adjacent ones, there are pairs, quads and
octets. Before simplification of Boolean functions with K-map, we have to
understand the meaning of pairs, quads and octets.

Grouping Two Adjacent Ones (pairs)

If there are two adjacent 1’s on the K-map, these can be grouped together
and the resulting term will have one less literal than the original two terms.

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(d) Four variables K-map :

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Many digital computers and systems process words which are expressed in
bytes of 4 bits (nibble) each so that a number of logic circuits are often designed
to handle four input variables (or their complements). Therefore, the four
variables K-map is most important in digital computers.
Representation of Standard SOP from on K-map :
A Boolean equation in standard SOP from can be represented on K-map by
simply entering 1’s in the box of the K-map corresponding to each minterm
present in the equation. This will become clear from the following example.
Procedure to fill 4 Variable K – Map :
The method for constructing a K-map of 4 variables is identical to the methods
discussed earlier. Now consider a truth table consisting of 4 variables as shown
in Table. The first step is to draw a blank map Fig.(a). Again, notice the
progression, the vertical column is labelled as A B, A B, AB and A B . The
horizontal row is labeled as C D, C D, CD C D .
Now, look for output 1’s in Truth Table. The fundamental products are
A B C D, A BCD , A BC D and ABCD . Enter these 1’s on the K-map as shown in
Fig.(b). The final step is to enter 0’s in remaining spaces. The complete K-map
for variables is shown in Fig.(c).
Thus, for 4 variables A, B, C and D, sixteen (24) combinations of 1’s and 0’s
are possible. So these sixteen terms ( o to 15) are shown in Truth Table. These
sixteen combinations corresponding to sixteen minterms( or maxterms) m0, m1,
m2, …..m15 need sixteen locations on the K-map as shown in Fig.(c). These
correspond to four rows and four columns. The sixteen positions of minterms (
or maxterms) are indicated as 0 to 15 in the corner of each box. 1 is placed in
those boxes, where minterms are included and 0 is placed, where minterms are
absent, In order to map :
Y = A B C D  A BC D  A BCD  ABC D
= m1, m6, m7, m14
Or Y = 1, 6, 7,14
On a K-map, 1 is placed in locations corresponding to minterms 1, 6, 7, and 14,
while is placed in all other locations.
Thus, the procedure used above is used to represent a truth table on the K-map.
On the other hand, if K-map is given, we can make the truth table
corresponding to this by following the reverse process.
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Truth Table ( for four variable );

INPUTS OUTPUT
Sr.No A B C D Y
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 0

Construction of 4-variables K-map :

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Grouping Four Adjacent Ones (Quads)

A quad is a group of four 1’s that are end to end , as shown in Fig. or in the
form of a square.

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Grouping Eight Adjacent Ones (Octets) :

An octet is a group of eight adjacent 1’s like those shown in Fig.

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Don’t care conditions:

We enter 1’s and 0’s in the map corresponding to input variables that make
the function equal to 1 or 0. The maps are simplified and entries are made for
either 1’s or 0’s.The cells which do not contain 1 are assumed to contain 0 and
vise-versa. This is not always true since there are cases in which certain
combination of input variables does not occur. Also for some functions the
outputs corresponding to certain combinations of input variables do not matter.
In such situation, it is left to the designer to assume either a 0 or 1 as output for
each of these combinations. This condition is known as don’t care condition and
is represented on the K-map as “X”.

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Overlapping Groups:

When there are pairs, quads and octets occurring in a K-map, it is essential to
consider the possibility when one, two, three or all above groups are present
simultaneously in K-map. There is also a possibility that these groups overlap,
i.e. it is possible to combine a particular 1 in a K-map more than one way.
Therefore, you encircle groups. You are allowed to use the same 1 more than
once. Fig. illustrates the idea.

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Rolling The Maps:

Another thing to know about the K-map reduction is rolling. The rolling of a K-
map is also possible as shown in Above Fig., the pairs result in the Boolean
equation.
Visualize picking up the K-map and rolling it so that the left side touches the
right side. If you are visualizing correctly, you will realize that two pairs
actually form a quad. To indicate this, draw half circles around each pair as
shown in Fig.

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Representation of Standard POS form on K-map:

The Boolean expression in standard POS form can be expressed on K-map by
entering 0’s in the boxes of K-map corresponding to each maxterm present in
the expression.

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Example:

Realize HALF adder circuit using K map. (4 marks)

A logic circuit for the addition of two one bit numbers is referred to as a
half adder. The addition process is reproduced in the truth table below. Here A
and B are the two inputs and S (SUM) and C (Carry) are the two outputs.

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Fig. Block Diagram of Half Adder.

Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

S= =
C = A.B

Design FULL Adder circuit with it’s truth table (4 marks)

A half adder has only two inputs and there is no provision to add a
carry coming from the lower order bits when multi-bit addition is performed.
Hence, a third input terminal is added and the circuit is used to add An, Bn
and Cn-1, where An and Bn are the nth order bits of A and B respectively
and Cn-1 is the carry generated from the addition of (n-1)th order bits. Its
truth table is as shown below:

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Fig. Block Diagram of Full Adder.

Inputs Outputs
An Bn Cn-1 Sn Cn
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The K-maps for outputs Sn and Cn are given below:

Sn=

Cn = AnBn + BnCn-1 + AnCn-1

Cn= An.Bn.Cn-1

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Explain HALF Subtractor using truth table. (4 marks)

A logic circuit for the subtraction of B (subtrahend) from A (minuend)

where A and B are one bit numbers is referred to as a half subtractor. The

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subtraction process is reproduced in the truth table below. Here A and B are the
two inputs and D (DIFFERENCE) and C (BORROW) are the two outputs.

Fig. Block Diagram of Half Subtractor

Inputs Outputs
A B D C
(Difference) (Borrow)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Difference (D) = =

Borrow (C) =

Explain & realize FULL subtractor. (4 Marks)

Similar to full adder, we require a full subtractor circuit for

performing multi-bit subtraction where in borrow from the previous bit is
also there. A full subtractor has three inputs, An (minuend), Bn (subtrahend)
and Cn-1 (borrow). Its truth table is as shown below:
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Fig. Block Diagram of Full Subtractor

Inputs Outputs
An Bn Cn-1 Dn Cn
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

The K-maps for outputs Sn and Cn are given below:

……..
…..(It is similar to full Adder)

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What is Multiplexer? Give it’s advantages. (4 marks)

Multiplexer is a special combinational circuit which is widely used in digital

system design. The MUX is also called as data selector. The data selector is a logic
circuit that gates one out of several inputs to a single output. The input selected is
controlled by set of select inputs.
For selecting one out of several “ n “inputs for connection to output a set of M
lines is required, where 2m = n There is a enable input called as strobe G which is
used for cascading & generally active low.

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Types of Multiplexers:
Depending upon the number of data inputs The multiplexers are classified as shown in
table below.

Design procedure:

Following procedure is used for design of multiplexers.

1. Identify the decimal number corresponding to each minterm in logic expression.
The
input lines corresponding to these numbers are to be connected to logic ‘1’
level.
2. All other inputs are to be connected to logic ‘0’ level.
3. The inputs are to be applied to select inputs.

Give advantages of multiplexers. (2 marks)

1. It reduces the number of wires required to pass from source to

destination.
2. It does not require simplification of logic expressions.
3. It minimizes the component count.
4. It reduces the cost of circuit.
5. It simplifies the logic design.
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Give applications of multiplexers. [W-06] (2 marks)

1. It is used as data selector.

2. It is used for data sorting.
3. It is used for data sequencing.
4. It is used for parallel to serial data conversion.

Design 4 : 1 Multiplexer.: (4 marks)

There are four data inputs D0 , D1 , D2, D3. & only one output. It has 2 select
inputs as 2m = 4 hence m=2. Data select inputs S0 & s1 which are termed as address
lines. The enable input G which is used to activate the circuit. It is active low
meaning multiplexer works if it low. The Multiplexer circuit can be implemented
using AND _ OR gates as shown in figure below. Secondly same circuit can be
implemented using NAND –NAND gates.

4 : 1 Multiplexer using AND – OR gates:

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4 : 1 Multiplexer using NAND -NAND gates

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The logic levels ( high or low ) applied to the select inputs S0 & S1determine which
AND gate is enabled so that its input data passes through OR gate to the output Y.
The output is given by

Working:

When S1 =S0 = 0 AND gate A0 is enabled and other gates are disabled. Hence Y=D0.

When S1 = 0 , S0 = 1 AND gate A1 is enabled and other gates are disabled. Y=D1.
When S1 = 1 , S0 = 0 AND gate A2is enabled and other gates are disabled. Y=D2.
When S1 =S0 = 1 AND gate A3 is enabled and other gates are disabled. Y=D3.

Truth Table(for 4 :1 Multiplexers)

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STROBE INPUTS OUTPUT

S1 S0
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3

1 X X 0

IC 74153( Dual 4 : 1 Multiplexer ):

IC 74153 is a dual 4 input multiplexer IC which is from TTL family.
The block diagram is shown below. It has two sets of inputs lines( I0a, I1a I2a, I3a) & (
I0b, I1b I2b, I3b). There are two outputs Y0 & Y1. There are STROBE signals Ea & Eb for
section-0 & section -1 respectively. The select inputs (S0, S1) are common for both
the sections. The Switch Equivalent of IC 74153 is shown below.

Design 8 : 1 Multiplexer (4 marks)

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IC 74151A ( 8 : 1 Multiplexer ):
It is a 8 input Multiplexer from TTL family. It has 8 Data inputs , 3 Data select inputs
The block diagram is shown below.

Truth Table(for 8 :1 Multiplexers):

STROBE SELECT INPUTS OUTPUTS

G S2 S1 S0 Yn
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
1 X X X 0

Multiplexer IC:
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What is a Demultiplexer ? (2 Marks)

Demultiplexer is opposite to MUX. Demultiplexer is a combinational logic

circuit and is used to transmit information from one line to any one line out of number
of output lines.
Demultiplex means “ One to many “ The input signal can be transferred to one of
the many outputs with the help of control signal. It is called as data distributor.It is
like a multiway switch.
1 : n Demultiplexer

Principle of Demultiplexer :
It has only one data input line. The number of output lines ‘ n’ ,& that of select
inputs is m where 2m = n. The outputs areY1, Y2 Y3,……,Yn. The select inputs are
also called control signal.
The select input code determines to which output the data input will be
transmitted There is a strobe i/p G which help in cascading and which is generally
active low. i.e Demutiplexer performs its operation when G is low. This circuit can
be used as binary to decimal decoder with binary inputs applied at the select inputs &
output obtained at corresponding output line.
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Table shows the types of demultiplexers .

Applications of demultiplexer : (2 marks)

1. It is used in communication system eg EPABX.

2. It is used in combinational logic design.
3. It is used in data routing applications.

1 : 4 Demultiplexer

Working of 1 : 4 Demultiplexer :
D is data input data line S0 & S1 are select input lines.
If G = 0 & S1 = S0 = 0 ; then output of first NAND gate will be low i. e. Y0 =0 .
If G = 0 & S1 = 0 , S0 = 1 ; then output of secondt NAND gate will be low i. e. Y1
=0 &
Thus , the circuit produces low output voltages at suitable outputs for given select
inputs.
The data bit at input D is transmitted to one of the four outputs depending on the
status of S0 & S1.
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When the strobe input G = 1 the data input will not be transmitted to output.

The fig shows implementation of 1 : 4 Demutiplexer using NAND gates:

IC 74155/ 74156 ( Dual 1 : 4 Demultiplexer ) :

It consists of two sections A & B with independent data ( D ) inputs, strobe
( G ), & Data outputs (Y0, Y1, Y2, Y3 ). There is a common set of select inputs S1 &
S0 for both sections . Section ‘A ‘ has an active -high data input (Da) and section ‘ B’
has active- low data input ( Db ).

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Design 1 : 8 Demultiplexer : (4 marks)

It has only one input D & eight outputs namely Y0 ,Y1,…..Y7. It has three
select lines S0 , S1 , S2 used to control signals The strobe is active low. The truth
table is shown below.

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Draw logical diagram and Truth table of Octal to Binary Encoder. 4 marks)

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Describe the working of Parity Generators/ Checkers.

(4 marks)
The parity means number of 1’s in binary number or data. In digital systems,
an additional bit known as the parity-bit is added to have even or odd parity in the
new word formed. The circuits for the generation of parity bits and checking parity of
the given word can be designed using gates. The same circuit is available as a MSI
chip (74180 ). The block Diagram of IC 74180 ( 8 bit parity input ) is shown below.

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The function table of IC 74180 ( As a parity checker ):

The function table of IC 74180 ( As a parity generator )

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Describe the operation of Decimal to BCD Encoder IC74147.(4 marks)

It is one of the commonly used input device in digital system.If adigital system
consists of asset of ten switches, one for each number ( 0 to 9). These switches
generates 1 or 0 logic levels for turning OFF or ON. When a particular number is to
be fed to the digital circuit in terms of BCD code, the switch corresponding to that
number is pressed.
There is a special IC performing same function ( 741474 ). It is a priority
encoder.
The block diagram of IC 74147 is shown below

Truth table of IC 74147 :

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It has active low inputs & outputs . meaning of Priority can be seen from the truth
table.
For example, if 2 inputs 2 & 5 are low, the output will be corresponding to 5 which
has ahigher prioritythan 2 i. e. the highest numbered input has priority over the lower
numbered inputs.

Draw the logical diagram of BCD to 7 segment Decoder IC7447.

In many digital systems we want the output in decimal for ease of reading.
 The outputs can be displayed using display devices like LEDs Nixie tubes .
 Seven segment display is the most popular display device used in digital
systems For displaying data using this device , the data have to be converted
from BCD to 7 – segment code. A number of MSI ICs are available for
performing this function. The decoder / driver circuit has 4 in put lines for BCD
data & 7 output lines for driving 7 segment display.Output terminals a to g of
the decoder are to be connected to the a to g terminals of seven segment
display.
 If the outputs are active-low, then the seven segment LED must be of the
common anode type ,whereas if the outputs are active- high then the 7 segment
LED must of common cathode type.

BCD – to – 7 – segment decoder /driver ICs

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Use of IC7447 to drive common anode display;

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Explain the functions of various pins of IC7447 (4 marks)

LT: Lamp Test

This is used to check the segments of LED. If it is connected to logic 0 level, all
the segments of the display connected to the decoder will be ON For normal decoding
operation, this terminal is to be connected to logic 1 level.

RBI : Ripple Blanking Input

It is to be connected to logic 1 for normal operation. If it is connected to
0 level, the segment outputs will generate data for normal 7 – segment decoding for all
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BCD inputs except zero. Whenever the BCD inputs correspond to zero, the 7-
segment display switches off This is used for blanking out leading zeros in multi-digit
display.

BI : Blanking Input
If it is connected to logic 0 level , the display is switched off irrespective
of BCD inputs This is used for conserving power in multiplexed displays RBO
This output, which is normally at logic 1 goes to logic 0 during zero blanking
interval This is used for cascading purpose.

Question Bank
1. Give the expressions of gray code equivalent of a 4 bit binary using K –
map.
2. Minimize the following SOP expressions using Kmap
(a) F(A,B,C,D) = m(0,1,4,5,7,8,9,12,13,15)
(b) f= m(0,3,5,6,9,10,12,15)
(c) F= m(0,1,2,3,11,12,14,15)
(d) f(A,B,C)= m(0,1,3,4,5)
(e) f(A,B,C)= m(0,1,2,3,6,7)
(f) f(A,B,C,D)= m(0,1,3,5,7)
(g) f(A,B,C)= m(0,1, 4,5,6,7)
(h)f(A,B,C,D)= m(1,6,7,11,12,13,15)
(i) f(A,B,C,D)= m(1,3,4,5,6,7,8,9,13,15)
(j) f(A,B,C,D)= m(0,1,2,4,8,9,11,12)
(k) f(A,B,C)= m(0,1,3,4,6)
(l) f(A,B,C,D)= m(0,1,3,4,5,6,7,13,15)
(m) Y= m(1,3,7,11,15
3. Realize full adder & full subtractor using K-map.
4. Reduce the expression Y= m(1,3,5,9,11,13)using K-map & implement
using K map.
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5. Minimize the POS expression F= m(0,3,5,6,9,10,12,15) using K map.

6. Minimize the POS expression F= m(0,1,2,3,11,12,14,15)using K-map
& implement in AND-OR logic.
7. Reduce Y= m( 1, 2, 4, 6, 7 ) & implement by universal gates.
9. Give advantages of multiplexer.
10. Draw the logic diagram of 4 : 1 multiplexer & explain its working.
11. Draw the functional diagram of 4 : 1 MUX using NAND gates.
12 Draw the functional diagram of 4 : 1 MUX using basic gates. (4marks)
13. Design 16 : 1 multiplexer using 4 : 1multiplexer. (4marks)
14. Design 32 : 1 multiplexer using 16 : 1multiplexer.
15. Design 64 : 1 multiplexer using 16 : 1multiplexer.
16. what is a demultiplexer? State its application.
17. Draw the logic diagram of 1 :8 demultiplexer & explain its working.
18. Draw the functional diagram of 1 : 4 Demultiplexer using basic gates.
19. Design 1 : 16 Demultiplexer using 1 : 8 Demultiplexer.
20. Design 1 : 8Demultiplexer using 1 : 2Demultiplexer
21. Differentiate between demux & mux. (4marks)
22. What is a decoder? how a demultiplexer can be used as
Decoder. (4 marks)

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