TPS61162A, TPS61163A

SLVSC26B – NOVEMBER 2013 – REVISED MAY 2024

TPS6116xA Dual-Channel WLED Drivers For Smart Phones

1 Features 3 Description
• 2.7V to 6.5V input voltage The TPS61162A and TPS61163A are dual-channel
• Integrated 1.5A/40V MOSFET WLED drivers which provide highly integrated
• 1.2MHz switching frequency solutions for single-cell Li-ion battery powered smart
• Dual current sinks of up to 30mA current each phone backlight. The devices have a built-in high
• 1% typical current matching and accuracy efficiency boost regulator with integrated 1.5A, 40V
• Optional 26.5V/37.5V OVP threshold power MOSFET and support as low as 2.7V input
– TPS61162A: 26.5V OVP voltage. With two high current-matching capability
– TPS61163A: 37.5V OVP current sink regulators, the devices can drive up
• Adaptive boost output to WLED voltages to 10s2p WLED diodes. The boost output can
• Very low voltage headroom control (90mV) automatically adjust to the WLED forward voltage
• Flexible digital and PWM brightness control and allow very low voltage headroom control, thus to
• One-Wire control interface ( EasyScale™) improve LED strings efficiency effectively.
• PWM dimming control interface The TPS61162A and TPS61163A support both
• Up to 100:1 PWM dimming ratio the PWM dimming interface and one-wire digital
• Up to 9-bit dimming resolution EasyScale™ dimming interface and can realize 9-bit
• Up to 90% efficiency brightness code programming.
• Built-in soft start
• PFM mode at light load The TPS61162A and TPS61163A integrate built-in
• Overvoltage protection soft start, as well as overvoltage, overcurrent, and
• Built-in WLED open/short protection thermal shutdown protections.
• Thermal shutdown Device Information(1)
• Supports 4.7µH inductor application PART NUMBER PACKAGE OPEN LED PROTECTION

2 Applications TPS61162A
DSBGA (9)
TPS61162A use 26.5V (typical)
TPS61163A TPS61163A use 37.5V (typical)
• Smart phones
• PDAs, handheld computers (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• GPS receivers
• Backlight for small and media form-factor LCD L1
display with single-cell battery input 2.7V ~ 6.5V 4.7µH D1
VBAT
C1 R2
C2
1µF 10 SW 1µF
VIN
C3
1µF

Enable /
EN
Disable
TPS61162A/3A
PWM
Dimming PWM
IFB1
COMP IFB2
C4
330nF ISET
R1
GND
63.4k

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 6.3 Feature Description.....................................................9
2 Applications..................................................................... 1 6.4 Device Functional Modes..........................................13
3 Description.......................................................................1 6.5 Programming............................................................ 15
4 Pin Configuration and Functions...................................3 7 Application and Implementation.................................. 18
Pin Functions.................................................................... 3 7.1 Application Information............................................. 18
5 Specifications.................................................................. 4 7.2 Typical Application.................................................... 18
5.1 Absolute Maximum Ratings........................................ 4 7.3 Power Supply Recommendations.............................26
5.2 ESD Ratings............................................................... 4 7.4 Layout....................................................................... 26
5.3 Recommended Operating Conditions.........................4 8 Device and Documentation Support............................28
5.4 Thermal Information....................................................5 8.1 Device Support......................................................... 28
5.5 Electrical Characteristics.............................................5 8.2 Related Links............................................................ 28
5.6 EasyScale Timing Requirements................................ 6 8.3 Community Resources..............................................28
5.7 Typical Characteristics................................................ 7 8.4 Trademarks............................................................... 28
6 Detailed Description........................................................8 9 Revision History............................................................ 28
6.1 Overview..................................................................... 8 10 Mechanical, Packaging, and Orderable
6.2 Functional Block Diagram........................................... 8 Information.................................................................... 28

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4 Pin Configuration and Functions

Top View Bottom View

1 2 3 3 2 1

A ISET IFB2 IFB1 IFB1 IFB2 ISET A

B PWM COMP GND GND COMP PWM B

C EN VIN SW SW VIN EN C

Figure 4-1. YFF Package 9-Pin DSBGA

Pin Functions
PIN
I/O DESCRIPTION
NUMBER NAME
Full-scale LED current set pin. Connecting a resistor to the pin programs the full-scale LED
A1 ISET I
current.
A2 IFB2 I Regulated current sink input pin
A3 IFB1 I Regulated current sink input pin
B1 PWM I PWM dimming signal input
Output of the transconductance error amplifier. Connect external capacitor to this pin to
B2 COMP O
compensate the boost loop.
B3 GND — Ground
C1 EN I Enable control and one-wire digital signal input
C2 VIN I Supply input pin
C3 SW I Drain connection of the internal power MOSFET

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN, EN, PWM, IFB1, IFB2 –0.3 7
Voltage(2) COMP, ISET –0.3 3 V
SW –0.3 40
PD Continuous power dissipation See Section 5.4
TJ Operating junction temperature –40 150
°C
Tstg Storage temperature –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750 V
Machine model (MM) 200 (max)

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 2.7 6.5 V
TPS61162A
VOUT Output voltage
TPS61163A
L Inductor 4.7 10 µH
CI Input capacitor 1 µF
CO Output capacitor 1 2.2 µF
CCOMP Compensation capacitor 330 nF
FPWM PWM dimming signal frequency 10 100 kHz
TJ Operating junction temperature –40 125 °C

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5.4 Thermal Information

TPS61162A/63A
THERMAL METRIC(1) YFF (DSBGA) UNIT
9 PINS
RθJA Junction-to-ambient thermal resistance 107 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W
RθJB Junction-to-board thermal resistance 18.1 °C/W
ψJT Junction-to-top characterization parameter 4.0 °C/W
ψJB Junction-to-board characterization parameter 18 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance NA °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

5.5 Electrical Characteristics

VIN = 3.6V, EN = high, PWM = high, IFB current = 20mA, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 2.7 6.5 V
VIN falling 2.2 2.3
VVIN_UVLO Undervoltage lockout threshold V
VIN rising 2.45
VVIN_HYS VIN UVLO hysteresis 100 mV
Operating quiescent current into Device enable, switching 1.2MHz and no
Iq 1.2 2 mA
VIN load, VIN = 3.6V
ISD Shutdown current EN = low 1 2 µA
EN and PWM
VH EN Logic high 1.2 V
VL EN Logic Low 0.4 V
VH PWM Logic high 1.2 V
VL PWM Logic Low 0.4 V
EN pin and PWM pin internal
RPD 400 800 1600 kΩ
pulldown resistor
tPWM_SD PWM logic low width to shutdown PWM high to low 20 ms
tEN_SD EN logic low width to shutdown EN high to low 2.5 ms
CURRENT REGULATION
VISET_full ISET pin voltage Full brightness 1.204 1.229 1.253 V
KISET_full Current multiplier Full brightness 1030
IISET = 20μA, D = 100%, 0°C to 70°C –2% 2%
IFB_avg Current accuracy
IISET = 20µA, D = 100%, –40°C to 85°C –2.3% 2.3%
D = 100% 1% 2%
KM (IMAX – IAVG) / IAVG
D = 25% 1%
IIFB_max Current sink max output current IISET = 35μA, each IFBx pin 30 mA
POWER SWITCH
VIN = 3.6V 0.25
RDS(on) Switch MOSFET on-resistance Ω
VIN = 3V 0.3
ILEAK_SW Switch MOSFET leakage current VSW = 35V, TJ = 25°C 1 µA

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VIN = 3.6V, EN = high, PWM = high, IFB current = 20mA, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCILLATOR
fSW Oscillator frequency 1000 1200 1500 kHz
Measured on the drive signal of switch
Dmax Maximum duty cycle 89% 95%
MOSFET
BOOST VOLTAGE CONTROL
IIFBx = 20mA, measured on IFBx pin which
VIFB_reg IFBx feedback regulation voltage 90 mV
has a lower voltage
Isink COMP pin sink current 12 µA
Isource COMP pin source current 5 µA
Gea Error amplifier transconductance 30 55 80 µmho
Rea Error amplifier output resistance 45.5 MΩ
Error amplifier crossover
fea 5pF connected to COMP pin 1.65 MHz
frequency
PROTECTION
ILIM Switch MOSFET current limit D = Dmax, 0°C to 70°C 1 1.5 2 A
Switch MOSFET start-up current
ILIM_Start D = Dmax 0.7 A
limit
tHalf_LIM Time window for half current limit 5 ms
TPS61162A 25 26.5 28
VOVP_SW SW pin overvoltage threshold V
TPS61163A 36 37.5 39
VOVP_IFB IFBx pin overvoltage threshold Measured on IFBx pin 4.2 4.5 5 V
Acknowledge output voltage low
VACKNL Open drain, Rpullup = 15kΩ to VIN 0.4 V
(2)

THERMAL SHUTDOWN
Tshutdown Thermal shutdown threshold 160 °C
Thys Thermal shutdown hysteresis 15 °C

(1) To select EasyScale interface, after tes_delay delay from EN low to high, drive EN pin to low for more than tes_det before tes_win expires.
(2) Acknowledge condition active 0, this condition is only applied when the RFA bit is set to 1. To use this feature, master must have an
open drain output, and the data line needs to be pulled up by the master with a resistor load.

5.6 EasyScale Timing Requirements

MIN NOM MAX UNIT
tes_delay EasyScale detection delay, measured from EN low to high 100 µs
tes_det EasyScale detection time, EN pin low time 260 µs
tes_win EasyScale detection window, easured from EN low to high(1) 1 ms
tstart Start time of program stream 2 µs
tEOS End time of program stream 2 360 µs
tH_LB High time of low bit (Logic 0) 2 180 µs
tL_LB Low time of low bit (Logic 0) 2 x tH_LB 360 µs
tH_HB High time of high bit (Logic 1) 2 x tL_HB 360 µs
tL_HB Low time high bit (Logic 1) 2 180 µs
tvalACKN Acknowledge valid time 2 µs
tACKN Duration of acknowledge condition 512 µs

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5.7 Typical Characteristics

50 PWM
Voltage
2V/div
DC
40
Io - Output Current (mA)

Inductor
Current
200mA/div
30 DC

Output
Voltage
20 VIN = 3V 20V/div
DC
VIN = 3.6V Output
10 Current
VIN = 4.2V 20mA/div
PWM Freq = 20kHz, Duty = 50%
DC
VIN = 5V t - Time - 10ms/div
0
0 20 40 60 80 100 Figure 5-2. Startup Waveform
Dimming Duty Cycle (%)

Figure 5-1. Dimming Linearity

PWM PWM
Voltage Voltage
2V/div 2V/div
DC DC

Inductor Inductor
Current Current
200mA/div 200mA/div
DC DC

Output Output
Voltage Voltage
20V/div 20V/div
DC DC
Output Output
Current Current
20mA/div 20mA/div
DC Duty = 100% DC PWM Freq = 20kHz, Duty = 50%

t - Time - 10ms/div t - Time - 10ms/div

Figure 5-3. Shutdown Waveform Figure 5-4. Shutdown Waveform

PWM
Voltage
2V/div
DC

Inductor
Current
200mA/div
DC

Output
Voltage
20V/div
DC
Output
Current
20mA/div
Duty = 100%
DC
t - Time - 10ms/div

Figure 5-5. Startup Waveform

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6 Detailed Description
6.1 Overview
The TPS61162A, TPS61163A is a high-efficiency, dual-channel white LED driver for smart-phone backlighting
applications. Two current sink regulators of high current-matching capability are integrated in the
TPS61162A,TPS61163A to support dual LED strings connection and to improve the current balance and protect
the LED diodes when either LED string is open or short.
The TPS61162A, TPS61163A has integrated all of the key function blocks to power and control up to 20 white
LED diodes. It includes a 1.5A, 40V boost converter, two current-sink regulators, and protection circuit for
overcurrent, overvoltage, and thermal shutdown protection.
In order to provide high brightness backlighting for large size or high resolution smart phone panels, more and
more white LED diodes are used. Having all LED diodes in a string improves overall current matching; however,
the output voltage of a boost converter will be limited when input voltage is low, and normally the efficiency will
drop when output voltage goes very high. Thus, the LED diodes are arranged in two parallel strings.
6.2 Functional Block Diagram
L1 D1
VBAT VOUT

R2
C1 C2
10
1µF 1µF
VIN SW
C3
1µF SW OVP
UVLO /
Internal Regulator

R Q
OSC S OCP
GND
Slope
Compensation
S

Comp Vref
GM

COMP
OPAMP Vclamp 120mV

C4 COMP clamp circuit IFBx Voltage

330nF Detection / OVP

UVLO SW OVP
EN
Enable / Disable Shutdown Dual-Channel IFB1
Detection Control Current Sinks

EA

PWM
Duty Decoding

ISET Current Sink 1

Analog Dimming Control
R1
63.4k
IFB2
Current Sink 2

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6.3 Feature Description

6.3.1 Boost Converter
The boost converter of the TPS61162A, TPS61163A integrates a 1.5A, 40V low-side switch MOSFET and has
a fixed switching frequency of 1.2MHz. The control architecture is based on traditional current-mode Pulse
Width Modulation (PWM) control. For operation see the Section 6.2. Two current sinks regulate the dual-channel
current, and the boost output is automatically set by regulating voltage on the IFBx pin. The output of error
amplifier and the sensed current of switch MOSFET are applied to a control comparator to generate the boost
switching duty cycle; slope compensation is added to the current signal to allow stable operation for duty cycles
larger than 50%.
The forward voltages of two LED strings are normally different due to the LED diode forward voltage
inconsistency; thus, the IFB1 and IFB2 voltages are normally different. The TPS61162A, TPS61163A can select
out the IFBx pin which has a lower voltage than the other and regulate its voltage to a very low value (90mV
typical), which is enough for the two current sinks' headroom. In this way, the output voltage of the boost
converter is automatically set and adaptive to LED strings' forward voltages, and the power dissipation of the
current sink regulators can be reduced remarkably with this very low headroom voltage.
In order to improve the boost efficiency at light load, Pulse Frequency Modulation (PFM) mode is automatically
enabled under light load conditions. When the load current decreases along with the dimming duty, the output of
gm amplifier — COMP pin voltage decreases until it is clamped at an internal reference voltage. Because COMP
pin voltage controls the inductor peak current, when it is clamped the inductor peak current is also clamped
and cannot decrease. As a result, more energy than needed is transferred to the output stage, and the output
voltage and IFBx pin voltage increase. An internal hysteresis comparator detects the minimum IFBx pin voltage.
When the minimum IFBx voltage is detected as higher than the regulation voltage 90mV by around 120mV, the
boost stops switching. Then the output voltage, as well as IFBx pin voltage, decrease. When the minimum IFBx
voltage is lower than the hysteresis (around 40mV), the boost switches again. Thus, during PFM mode the boost
output trips between the low and high thresholds. When the load increases along with the dimming duty, the
COMP pin voltage will exit from the clamped status, and the boost will exit the PFM mode and return to the
PWM operation, during which the minimum IFBx pin voltage is regulated at 90mV again. Refer to Figure 7-10
and Figure 7-11 for PFM mode operation.
6.3.2 IFBx Pin Unused
If only one channel is needed, a user can easily disable the unused channel by connecting its IFBx pin to
ground. If both IFBx pins are connected to ground, the device will not start up.

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6.3.3 Enable and Start-up

In order to enable the device from shutdown mode, three conditions have to be met:
1. POR (Power On Reset, that is, VIN voltage is higher than UVLO threshold);
2. Logic high on EN pin; and
3. PWM signal (logic high or PWM pulses) on PWM pin.
When these conditions are all met, an internal LDO linear regulator is enabled to provide supply to internal
circuits and the device can start up.
The TPS61162A, TPS61163A support two dimming interfaces: one-wire digital interface (EasyScale interface)
and PWM interface. TPS61162A, TPS61163A begin an EasyScale detection window after start-up to detect
which interface is selected. If the EasyScale interface is needed, signals of a specific pattern should be input into
EN pin during the EasyScale detection window; otherwise, PWM dimming interface will be enabled (see details
in Section 6.4.1).
After the EasyScale detection window, the TPS61162A, TPS61163A check the status of IFBx pins. If one IFBx
pin is detected to connect to ground, the corresponding channel will be disabled and removed from the control
loop. Then the soft-start begins, and the boost converter starts switching. If both IFBx pins are shorted to ground,
the TPS61162A, TPS61163A will not start up.
Either pulling EN pin low for more than 2.5ms or pulling PWM pin low for more than 20ms can disable the
device, and the TPS61162A, TPS61163A enters into shutdown mode.
If the EasyScale is selected as unique control to enable/disable and change brightness for
TPS61162A,TPS61163A, it is required to pull EN pin more than 100ms to enable the TPS61162A, TPS61163A
from the previous disable. The 100ms time period can ensure the fully voltage discharge remained on IFBx pin.
6.3.4 Soft Start
Soft start is implemented internally to prevent voltage over-shoot and in-rush current. After the IFBx pin status
detection, the COMP pin voltage starts ramp up, and the boost starts switching. During the beginning 5ms
(tHalf_LIM) of the switching, the peak current of the switch MOSFET is limited at ILIM_Start (0.7A typical) to avoid the
input inrush current. After the 5ms, the current limit is changed to ILIM (1.5A typical) to allow the normal operation
of the boost converter.
6.3.5 Full-Scale Current Program
The dual channels of the TPS61162A, TPS61163A can provide up to 30mA current each. It does not matter
whether either the EasyScale interface or PWM interface is selected, the full-scale current (current when
dimming duty cycle is 100%) of each channel should be programmed by an external resistor RISET at the ISET
pin according to Equation 1.

VISET _ full
IFB _ full = ´ KISET _ full
RISET (1)

where
• IFB_full, full-scale current of each channel
• KISET_full = 1030 (Current multiple when dimming duty cycle = 100%)
• VISET_full = 1.229V (ISET pin voltage when dimming duty cycle = 100%)
• RISET = ISET pin resistor

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6.3.6 Brightness Control

The TPS61162A, TPS61163A controls the DC current of the dual channels to realize the brightness dimming.
The DC current control is normally referred to as analog dimming mode. When the DC current of LED diode is
reduced, the brightness is dimmed.
The TPS61162A, TPS61163A can receive either the PWM signals at the PWM pin (PWM interface) or digital
commands at the EN pin (EasyScale interface) for brightness dimming. If the EasyScale interface is selected,
the PWM pin should be kept high; if PWM interface is selected, the EN pin should be kept high.
6.3.7 Undervoltage Lockout
An undervoltage lockout circuit prevents the operation of the device at input voltages below undervoltage
threshold (2.2 V typical). When the input voltage is below the threshold, the device is shut down. If the input
voltage rises by undervoltage lockout hysteresis, the device restarts.
6.3.8 Overvoltage Protection
Overvoltage protection circuitry prevents device damage as the result of white LED string disconnection or
shortage.
The TPS61162A/TPS61163A monitors the voltages at SW pin and IFBx pin during each switching cycle. No
matter either SW OVP threshold VOVP_SW or IFBx OVP threshold VOVP_FB is reached due to the LED string open
or short issue, the protection circuitry will be triggered. Refer to Figure 6-1 and Figure 6-2 for the protection
actions.
If one LED string is open, its IFBx pin voltage drops, and the boost output voltage is increased by the control
loop as it tries to regulate this lower IFBx voltage to the target value (90mV typical). For the normal string, its
current is still under regulation but its IFBx voltage increases along with the output voltage. During the process,
either the SW voltage reaches its OVP threshold VOVP_SW or the normal string’s IFBx pin voltage reaches the
IFBx OVP threshold VOVP_FB, then the protection circuitry will be triggered accordingly.
If both LED strings are open, both IFBx pins’ voltages drop to ground, and the boost output voltage is increased
by the control loop until reaching the SW OVP threshold VOVP_SW, the SW OVP protection circuitry is triggered,
and the device is latched off. Only VIN POR or EN/PWM pin toggling can restart the IC.
One LED diode short in a string is allowed for the TPS61162A, TPS61163A. If one LED diode in a string is short,
the normal string’s IFBx voltage is regulated to about 90 mV, and the abnormal string’s IFBx pin voltage will be
higher. Normally with only one diode short, the higher IFBx pin voltage does not reach the IFBx OVP threshold
VOVP_FB, so the protection circuitry will not be triggered.
If more than one LED diodes are short in a string, as the boost loop regulates the normal string’s IFBx voltage
to 90 mV, this abnormal string’s IFBx pin voltage is much higher and will reach VOVP_FB, then the protection
circuitry is triggered.
The SW OVP protection will also be triggered when the forward voltage drop of an LED string exceeds the SW
OVP threshold. In this case, the device turns off the switch FET and shuts down.

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Soft Start /
Normal Operation

SW > VOVP for 16~32 No

switching cycles?

Yes

Latch off

Figure 6-1. SW OVP Action

Normal Operation

IFBx > VIFB_OVP for

24~32 switching
No (caused by transient)
cycles?

Yes

Yes (single string application,

Another string is no caused by transient)
use?

Boost stops
No switching, current
sink(s) keep on
No (dual string application,
caused by transient)
Another VIFBx < 0.5V?

Yes (caused by open string or

more than two LED diodes
short in a string)
Boost stops switching,
disable the current sink VIFBx < VIFB_OVP_hys?
with VIFBx < 0.5V

Yes (to recover boost

switching)

Figure 6-2. VIFBx OVP Action

6.3.9 Overcurrent Protection

The TPS61162A, TPS61163A have a pulse-by-pulse overcurrent limit. The boost switch turns off when the
inductor current reaches this current threshold, and it remains off until the beginning of the next switching cycle.
This protects the TPS61162A, TPS61163A and external component under overload conditions.
6.3.10 Thermal Shutdown
An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded.
The device is released from shutdown automatically when the junction temperature decreases by 15°C.

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6.4 Device Functional Modes

6.4.1 One-Wire Digital Interface (EasyScale Interface)
The EN pin features a simple digital interface to allow digital brightness control. The digital dimming interface can
save the processor power and battery life as it does not require PWM signals all the time, and the processor can
enter idle mode if possible. In order to enable the EasyScale interface, the following conditions must be satisfied,
and the specific digital pattern on the EN pin must be recognized by the device every time the TPS61162A,
TPS61163A starts up from shutdown mode.
1. VIN voltage is higher than UVLO threshold, and PWM pin is pulled high.
2. Pull EN pin from low to high to enable the TPS61162A, TPS61163A. At this moment, the EasyScale
detection window starts.
3. After EasyScale detection delay time (tes_delay, 100µs), drive EN to low for more than EasyScale detection
time (tes_detect, 260µs).
The third step must be finished before the EasyScale detection window (tes_win, 1ms) expires, and once this step
is finished, the EasyScale interface is enabled, and the EasyScale communication can start. Refer to Figure 6-3
for a graphical explanation.
Insert battery

high PWM Signal

PWM
low
Enter ES mode

ES Detection Programming Programming code

Window code

high

EN
low

EasyScale ES detect time Shutdown

mode delay Ramp up

ES detect delay
Ramp up
Programmed value IC
(if not programmed, full current default )
Shutdown
Startup delay Startup delay
IFBx

Figure 6-3. Easyscale Interface Detection

The TPS61162A, TPS61163A support 9-bit brightness code programming. By the EasyScale interface, a master
can program the 9-bit code D8(MSB) to D0(LSB) to any of 511 steps with a single command. The default code
value of D8~D0 is “111111111” when the device is first enabled, and the programmed value will be stored in an
internal register and set the dual-channel current according to Equation 2. The code will be reset to default value
when the device is shut down or disabled.

Code
IFBx = IFB_full ´
511 (2)

where
• IFB_full: the full-scale LED current set by the RISET at ISET pin.
• Code: the 9-bit brightness code D8~D0 programmed by EasyScale interface
When the one-wire digital interface at EN pin is selected, the PWM pin can be connected to either the VIN pin
or a GPIO (refer to Section 7.2.4). If PWM pin is connected to VIN pin, EN pin alone can enable and disable the
device — pulling EN pin low for more than 2.5ms disables the device; if PWM pin is connected to a GPIO, both
PWM and EN signals should be high to enable the device, and either pulling EN pin low for more than 2.5ms or
pulling PWM pin low for more than 20ms disables the device.

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6.4.2 PWM Control Interface

The PWM control interface is automatically enabled if the EasyScale interface fails to be enabled during startup.
In this case, the TPS61162A, TPS61163A receives PWM dimming signals on the PWM pin to control the
backlight brightness. When using PWM interface, the EN pin can be connected to VIN pin or a GPIO (refer to
Section 7.2.4). If EN pin is connected to VIN pin, PWM pin alone is used to enable and disable the device:
pulling PWM pin high or apply PWM signals at PWM pin to enable the device and pulling PWM pin low for more
than 20ms to disable the device; if EN pin is connected to a GPIO, either pulling EN pin low for more than 2.5ms
or pulling PWM pin low for more than 20ms can disable the device. Only after both EN and PWM signals are
applied, the TPS61162A/TPS61163A can start up. Refer to Figure 6-4 for a graphical explanation.
Insert battery Insert battery

high EN signal EN signal

high

EN
low
low
PWM signal PWM signal
high high
PWM PWM
low low

PWM
mode Startup Startup
Ramp up Shutdown delay Ramp up Shutdown delay
delay delay
Full current x PWM Duty Shut down by Full current x PWM Duty
Shut down by
PWM signal
EN signal
IFBx t IFBx t

Figure 6-4. PWM Control Interface Detection

When the PWM pin is constantly high, the dual channel current is regulated to full scale according to Equation 1.
The PWM pin allows PWM signals to reduce this regulation current according to the PWM duty cycle; therefore,
it achieves LED brightness dimming. The relationship between the PWM duty cycle and IFBx current is given by
Equation 3.

IFBx = IFB_full ´ Duty (3)

where
• IFBx is the current of each current sink
• IFB_full is the full-scale LED current
• Duty is the duty cycle information detected from the PWM signals

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6.5 Programming
6.5.1 EasyScale Programming
EasyScale is a simple, but flexible, one-pin interface to configure the current of the dual channels. The interface
is based on a master-slave structure, where the master is typically a microcontroller or application processor
and the device is the slave. Figure 6-5 and Table 6-1 give an overview of the protocol used by TPS61162A/
TPS61163A. A command consists of 24 bits, including an 8-bit device address byte and a 16-bit data byte.
All of the 24 bits should be transmitted together each time, and the LSB bit should be transmitted first. The
device address byte D7(MSB)~D0(LSB) is fixed to 0x8F. The data byte includes 9 bits D8(MSB)~D0(LSB) for
brightness information and an RFA bit. The RFA bit set to "1" indicates the Request for Acknowledge condition.
The Acknowledge condition is only applied when the protocol is received correctly. The advantage of EasyScale
compared with other one pin interfaces is that its bit detection is in a large extent independent from the bit
transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec.
DATA IN
Data Byte Address Byte

Bit 11 ~ D0 D1 D2 D3 D4 D5 D6 D7
Start D0 D1 D2 D3 D4 D5 D6 D7 D8 Bit 9 RFA EOS
Bit 15 1 1 1 1 0 0 0 1

DATA OUT ACK

Figure 6-5. Easyscale Protocol Overview

Table 6-1. Easyscale Bit Description

TRANSMISSION
BYTE BIT NUMBER NAME DESCRIPTION
DIRECTION
23 (MSB) DA7 DA7 = 1, MSB of device address
22 DA6 DA6 = 0
21 DA5 DA5 = 0
Device
Address 20 DA4 DA4 = 0
IN
Byte 19 DA3 DA3 = 1
(0x8F)
18 DA2 DA2 = 1
17 DA1 DA1 = 1
16 DA0 DA0 = 1, LSB of device address

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Table 6-1. Easyscale Bit Description (continued)

TRANSMISSION
BYTE BIT NUMBER NAME DESCRIPTION
DIRECTION
15 Bit 15 No information. Write 0 to this bit.
14 Bit 14 No information. Write 0 to this bit.
13 Bit 13 No information. Write 0 to this bit.
12 Bit 12 No information. Write 0 to this bit.
11 Bit 11 No information. Write 0 to this bit.
Request for acknowledge. If set to 1, device will pull low the data line
when it receives the command well. This feature can only be used
10 RFA when the master has an open drain output stage and the data line
needs to be pulled high by the master with a pullup resistor; otherwise,
acknowledge condition is not allowed and don't set this bit to 1.
Data Byte 9 Bit 9 IN No information. Write 0 to this bit.
8 D8 Data bit 8, MSB of brightness code
7 D7 Data bit 7
6 D6 Data bit 6
5 D5 Data bit 5
4 D4 Data bit 4
3 D3 Data bit 3
2 D2 Data bit 2
1 D1 Data bit 1
0 (LSB) D0 Data bit 0, LSB of brightness code

t start
Data Byte Address Byte

Static High Static High

DATA IN
D0 D8 Bit 9 RFA Bit 15 DA0 DA7
1 0 0 0 0 1 1
tEOS

Figure 6-6. Easyscale Timing, With RFA = 0

t start
Data Byte Address Byte

Static High Static High

DATA IN
D0 D8 Bit 9 RFA Bit 15 DA0 DA7
1 0 0 1 0 1 1
tvalACK
Acknowledge
true, Data line
DATA OUT ACKN pulled down by
the IC
(ACKN)
Master needs to pull up
Data line via a pullup
resistor to detect ACKN
Acknowledge
false, no pull
DATA OUT down
(ACK) ACK

Figure 6-7. Easyscale Timing, With RFA = 1

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tLow tHigh tLow tHigh

Low Bit High Bit

(Logic 0) (Logic 1)

Figure 6-8. Easyscale — Bit Coding

The 24-bit command should be transmitted with LSB first and MSB last. Figure 6-6 shows the protocol without
acknowledge request (Bit RFA = 0), Figure 6-7 with acknowledge request (Bit RFA = 1). Before the command
transmission, a start condition must be applied. For this, the EN pin must be pulled high for at least tstart (2μs)
before the bit transmission starts with the falling edge. If the EN pin is already at high level, no start condition is
needed. The transmission of each command is closed with an End of Stream condition for at least tEOS (2μs).
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and
tHIGH (refer to Figure 6-8). It can be simplified to:
Low Bit (Logic 0): tLOW ≥ 2 x tHIGH
High Bit (Logic 1): tHIGH ≥ 2 x tLOW
The bit detection starts with a falling edge on the EN pin and ends with the next falling edge. Depending on the
relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
• Acknowledge is requested by setting RFA bit to 1.
• The transmitted device address matches with the device address of the IC.
• Total 24 bits are received correctly.
If above conditions are met, after tvalACK delay from the moment when the last falling edge of the protocol is
detected, an internal ACKN-MOSFET is turned on to pull the EN pin low for the time tACKN, which is 512μs
maximum, then the Acknowledge condition is valid. During the tvalACK delay, the master controller keeps the line
low; after the delay, it should release the line by outputting high impedance and then detect the acknowledge
condition. If it reads back a logic 0, it means the device has received the command correctly. The EN pin can be
used again by the master when the acknowledge condition ends after tACKN time.
The acknowledge condition can only be requested when the master device has an open drain output. For a
push-pull output stage, the use of a series resistor in the EN line to limit the current to 500μA is recommended to
for such cases as:
• An accidentally requested acknowledge, or
• To protect the internal ACKN-MOSFET.

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

7.1 Application Information

The TPS61162A, TPS61163A provide a complete high-performance LED lighting solution for mobile handsets.
They can drive up to 2 strings of white LEDs with up to 10 LEDs per string. A boost converter generates the high
voltage required for the LEDs. LED brightness can be controlled either by the PWM dimming interface or by the
single-wire EasyScale dimming interface.
7.2 Typical Application
L1
2.7V ~ 6.5V 4.7µH D1
VBAT
C1 R2
C2
1µF 10 SW 1µF
VIN
C3
1µF

Enable /
EN
Disable
TPS61162A/3A
PWM
Dimming PWM
IFB1
COMP IFB2
C4
330nF ISET
R1
GND
63.4k

Figure 7-1. TPS61162A/63A Typical Application

7.2.1 Design Requirements

For TPS61162A, TPS61163A typical applications, use the parameters listed in Table 7-1 as the input
parameters.
Table 7-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 2.7V to 6.5V
Boost switching frequency 1.2MHz
Efficiency up to 90%

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7.2.2 Detailed Design Procedure

7.2.2.1 Inductor Selection
Because the selection of inductor affects power supply’s steady-state operation, transient behavior, loop stability
and the boost converter efficiency, the inductor is one of the most important components in switching power
regulator design. There are three specifications most important to the performance of the inductor: inductor
value, DC resistance, and saturation current. The TPS61162A, TPS61163A are designed to work with inductor
values from 4.7µH to 10µH to support all applications. A 4.7µH inductor is typically available in a smaller or
lower profile package, while a 10µH inductor produces lower inductor ripple. If the boost output current is limited
by the overcurrent protection of the device, using a 10µH inductor may maximize the controller’s output current
capability. A 22µH inductor can also be used for some applications, such as 6s2p and 7s2p, but may cause
stability issue when more than eight WLED diodes are connected per string. Therefore, customers need to verify
the inductor in their application if it is different from the values in Section 5.3.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current
approaches saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the
inductor vendor defines saturation. When selecting an inductor, please make sure its rated current, especially
the saturation current, is larger than its peak current during the operation.
Follow Equation 4 to Equation 6 to calculate the inductor’s peak current. To calculate the current in the worst
case, use the minimum input voltage, maximum output voltage and maximum load current of the application. In
order to leave enough design margin, the minimum switching frequency (1 MHz for TPS61162A, TPS61163A),
the inductor value with –30% tolerance, and a low power conversion efficiency, such as 80% or lower are
recommended for the calculation.
In a boost regulator, the inductor DC current can be calculated as Equation 4.

VOUT ´ IOUT
IDC =
VIN ´ h (4)

where
• VOUT = boost output voltage
• IOUT = boost output current
• VIN = boost input voltage
• η = boost power conversion efficiency
The inductor current peak-to-peak ripple can be calculated as Equation 5.

1
IPP =
æ 1 1 ö
L´ç + ÷ ´ FS
è VOUT - VIN VIN ø (5)

where
• IPP = inductor peak-to-peak ripple
• L = inductor value
• FS = boost switching frequency
• VOUT = boost output voltage
• VIN = boost input voltage
Therefore, the peak current IP seen by the inductor is calculated with Equation 6.

IPP
IP = IDC +
2 (6)

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Select an inductor with saturation current over the calculated peak current. If the calculated peak current is larger
than the switch MOSFET current limit ILIM, use a larger inductor, such as 10µH, and make sure its peak current
is below ILIM.
Boost converter efficiency is dependent on the resistance of its current path, the switching losses associated
with the switch MOSFET and power diode, and the inductor’s core loss. The TPS61162A, TPS61163A has
optimized the internal switch resistance; however, the overall efficiency is affected a lot by the inductor’s DC
Resistance (DCR), Equivalent Series Resistance (ESR) at the switching frequency, and the core loss. Core
loss is related to the core material and different inductors have different core loss. For a certain inductor,
larger current ripple generates higher DCR/ESR conduction losses as well as higher core loss. Normally a
datasheet of an inductor does not provide the ESR and core loss information. If needed, consult the inductor
vendor for detailed information. Generally, an inductor with lower DCR/ESR is recommended for TPS61162A,
TPS61163A applications. However, there is a trade-off among an inductor’s inductance, DCR/ESR resistance,
and its footprint; furthermore, shielded inductors typically have higher DCR than unshielded ones. Table 7-2 lists
some recommended inductors for the TPS61162A and TPS61163A. Verify whether the recommended inductor
can support target application by the calculations above as well as bench validation.
Table 7-2. Recommended Inductors
SATURATION CURRENT
PART NUMBER L (µH) DCR MAX (mΩ) SIZE (L x W x H mm) VENDOR
(A)
LPS4018-472ML 4.7 125 1.9 4 x 4 x 1.8 Coilcraft
LPS4018-682ML 6.8 150 1.3 4 x 4 x 1.8 Coilcraft
LPS4018-103ML 10 200 1.3 4 x 4 x 1.8 Coilcraft
PIMB051B-4R7M 4.7 163 2.7 5.4 x 5.2 x 1.2 Cyntec
PIMB051B-6R8M 6.8 250 2.3 5.4 x 5.2 x 1.2 Cyntec

7.2.2.2 Schottky Diode Selection

The TPS61162A, TPS61163A demands a low forward-voltage, high-speed and low-capacitance Schottky diode
for optimum efficiency. Ensure that the diode average and peak current rating exceeds the average output
current and peak inductor current. In addition, the diode’s reverse breakdown voltage must exceed the open
LED protection voltage. ONSemi MBR0540 and NSR05F40, and Vishay MSS1P4 are recommended for the
TPS61162A, TPS61163A.

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7.2.2.3 Compensation Capacitor Selection

The compensation capacitor C4 (refer to Section 7.2.4) connected from the COMP pin to GND, is used to
stabilize the feedback loop of the TPS61162A, TPS61163A. A 330nF ceramic capacitor for C4 is suitable for
most applications. A 470nF is also OK for some applications and customers are suggested to verify it in their
applications.
7.2.2.4 Output Capacitor Selection
The output capacitor is mainly selected to meet the requirement for the output ripple and loop stability. A 1-µF
to 2.2-µF capacitor is recommended for the loop stability consideration. This ripple voltage is related to the
capacitor’s capacitance and its ESR. Due to its low ESR, Vripple_ESR could be neglected for ceramic capacitors.
Assuming a capacitor with zero ESR, the output ripple can be calculated with Equation 7.

(VOUT - VIN ) ´ IOUT

Vripple =
VOUT ´ FS ´ COUT (7)

where
• Vripple = peak-to-peak output ripple.
The additional part of ripple caused by the ESR is calculated using Vripple_ESR = IOUT x RESR and can be ignored
for ceramic capacitors.
Note that capacitor degradation increases the ripple much. Select the capacitor with 50-V rated voltage to
reduce the degradation at the output voltage. If the output ripple is too large, change a capacitor with less
degradation effect or with higher rated voltage could be helpful.

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7.2.3 Application Curves

100 100
Vo = 15V, 5s2p, 20mA/string Vo = 18V, 6s2p, 20mA/string

90 90
Efficiency (%)

Efficiency (%)
80 80

VIN = 3V VIN = 3V

70 VIN = 3.6V 70 VIN = 3.6V

VIN = 4.2V VIN = 4.2V
VIN = 5V VIN = 5V
60 60
0 20 40 60 80 100 0 20 40 60 80 100
Dimming Duty Cycle (%) Dimming Duty Cycle (%)

Figure 7-2. Dimming Efficiency Figure 7-3. Dimming Efficiency

100 100
Vo = 21V, 7s2p, 20mA/string Vo = 24V, 8s2p, 20mA/string

90 90
Efficiency (%)

Efficiency (%)
80 80

VIN = 3V VIN = 3V

70 VIN = 3.6V 70 VIN = 3.6V

VIN = 4.2V VIN = 4.2V
VIN = 5V VIN = 5V
60 60
0 20 40 60 80 100 0 20 40 60 80 100
Dimming Duty Cycle (%) Dimming Duty Cycle (%)

Figure 7-4. Dimming Efficiency Figure 7-5. Dimming Efficiency

100 100
Vo = 27V, 9s2p, 20mA/string Vo = 30V, 10s2p, 20mA/string

90 90
Efficiency (%)

Efficiency (%)

80 80

VIN = 3V VIN = 3V

70 VIN = 3.6V 70 VIN = 3.6V

VIN = 4.2V VIN = 4.2V
VIN = 5V VIN = 5V
60 60
0 20 40 60 80 100 0 20 40 60 80 100
Dimming Duty Cycle (%) Dimming Duty Cycle (%)

Figure 7-6. Dimming Efficiency Figure 7-7. Dimming Efficiency

SW
SW Voltage
Voltage 20V/div
20V/div DC
DC Min
Output Feedback
Voltage Voltage
100mV/div 100mV/div
AC DC
Inductor Inductor
Current Current
200mA/div 200mA/div
DC DC
Output Output
Current Current
20mA/div 20mA/div
DC Duty = 100% DC Duty = 100%

t - Time - 1ms/div t - Time - 1ms/div

Figure 7-8. Switching Waveform Figure 7-9. Switching Waveform

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SW
SW Voltage
Voltage 20V/div
20V/div DC
DC Min
Output Feedback
Voltage Voltage
200mV/div 100mV/div
AC DC
Inductor Inductor
Current Current
100mA/div 100mA/div
DC DC
Output Output
Current Current
5mA/div 2mA/div
DC DC
PWM Freq = 20kHz, Duty = 10% PWM Freq = 20kHz, Duty = 10%
t - Time - 4ms/div t - Time - 4ms/div

Figure 7-10. Switching Waveform Figure 7-11. Switching Waveform

SW
Voltage
20V/div
DC
Inductor
Current
200mA/div
DC
Output
Voltage
2V/div
AC
Output
Current
20mA/div PWM Freq = 20kHz,
DC Duty = 10% - 80% - 10%

t - Time - 400ms/div

Figure 7-12. Dimming Transient Waveform

7.2.4 Additional Application Circuits

In Figure 7-13 the PWM Interface is enabled, and the PWM input signal is used to adjust the brightness level.
The PWM pin as well as the EN pin can be used to enable or disable the TPS61162A, TPS61163A.
L1
2.7V ~ 6.5V 4.7µH D1
VBAT
C1 R2
C2
1µF 10 SW 1µF
VIN
C3
1µF

Enable /
EN
Disable
TPS61162A/3A
PWM
Dimming PWM
IFB1
COMP IFB2
C4
330nF ISET
R1
GND
63.4k

Figure 7-13. TPS61162A/TPS61163A Typical Application

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Figure 7-14 shows PWM interface enabled, EN pin connected to VIN, with only the PWM Signal used to adjust
the brightness level and to enable or disable the TPS61162A, TPS61163A.
L1
2.7V ~ 6.5V 4.7µH D1
VBAT
C1 R2
C2
1µF 10 SW 1µF
VIN
C3
1µF

EN
TPS61162A/3A
PWM
Dimming PWM
IFB1
COMP IFB2
C4
330nF ISET
R1
GND
63.4k

Figure 7-14. TPS61162A/TPS61163A Typical Application

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In Figure 7-15 the one-wire digital interface is enabled. Brightness level is adjusted with the PWM pin using
EasyScale commands. The PWM signal must remain high for the device to be enabled.
L1
2.7V ~ 6.5V 4.7µH D1
VBAT
C1 R2
C2
1µF 10 SW 1µF
VIN
C3
1µF

EasyScale
Command EN
TPS61162A/3A
Enable /
Disable PWM
IFB1
COMP IFB2
C4
330nF ISET
R1
GND
63.4k

Figure 7-15. TPS61162A/TPS61163A Typical Application

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Figure 7-16 shows one-wire digital interface enabled, PWM pin connected to VIN, with only the EN signal used
to enable or disable the device. Brightness level adjustments (using EasyScale Commands) can be achieved via
the EN pin only.
L1
2.7V ~ 6.5V 4.7µH D1
VBAT
C1 R2
C2
1µF 10 SW 1µF
VIN
C3
1µF

EasyScale
Command EN
TPS61162A/3A

PWM
IFB1
COMP IFB2
C4
330nF ISET
R1
GND
63.4k

Figure 7-16. TPS61162A/TPS61163A Typical Application

7.3 Power Supply Recommendations

The TPS61162A and TPS61163A are designed to operate from an input supply range of 2.7V to 6.5V. This input
supply should be well regulated and be able to provide the peak current required by the LED configuration and
inductor selected without voltage drop under load transients (start-up or rapid brightness change). If the input
supply is located far from the TPS6116xA additional bulk capacitance may be required in addition to the ceramic
bypass capacitors.
7.4 Layout
7.4.1 Layout Guidelines
As for all switching power supplies, especially those providing high current and using high switching frequencies,
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C1 in Section
7.2.4, needs to be close to the inductor, as well as the VIN pin and GND pin in order to reduce the input ripple
seen by the device. If possible, choose higher capacitance value for it. If the ripple seen at VIN pin is so large
that it affects the boost loop stability or internal circuits operation, R2 and C3 are recommended to filter and
decouple the noise. In this case, C3 should be placed as close as possible to the VIN and GND pins. The SW
pin carries high current with fast rising and falling edges. Therefore, the connection between the SW pin to the
inductor and Schottky diode should be kept as short and wide as possible. The trace between Schottky diode
and the output capacitor C2 should also be as short and wide as possible. It is also beneficial to have the ground
of the output capacitor C2 close to the GND pin since there is a large ground return current flowing between
them. When laying out signal grounds, it is recommended to use short traces separated from power ground
traces, and connect them together at a single point close to the GND pin.

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7.4.2 Layout Example

ISET LED2 LED1

ISET IFB2 IFB1

Vias to GND
Plane

PWM PWM COMP GND

1 PF

EN EN VIN SW

Vias to GND VIN SW

GND
Plane
1 PF 4.7 P+

Minimize the
area of this trace
Figure 7-17. TPS61162A/TPS61163A Layout

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8 Device and Documentation Support

8.1 Device Support
8.2 Related Links
Table 8-1 below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TPS61162A Click here Click here Click here Click here Click here
TPS61163A Click here Click here Click here Click here Click here

8.3 Community Resources

8.4 Trademarks
EasyScale™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2015) to Revision B (May 2024) Page
• Updated Device InformationTable.......................................................................................................................1

Changes from Revision * (November 2013) to Revision A (May 2015) Page

• Added Pin Configuration and Functions section, ESD Rating table, Feature Description , Device Functional
Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and
Documentation Support , and Mechanical, Packaging, and Orderable Information sections; ...........................1
• Deleted Ordering Information ............................................................................................................................ 1

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS61162A TPS61163A

 PACKAGE OPTION ADDENDUM

www.ti.com 17-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS61162AYFFR ACTIVE DSBGA YFF 9 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -55 to 125 TPS Samples
61162A
TPS61163AYFFR ACTIVE DSBGA YFF 9 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TPS Samples
61163A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Apr-2024

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Jun-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61162AYFFR DSBGA YFF 9 3000 180.0 8.4 1.45 1.45 0.8 4.0 8.0 Q1
TPS61163AYFFR DSBGA YFF 9 3000 180.0 8.4 1.45 1.45 0.8 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Jun-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS61162AYFFR DSBGA YFF 9 3000 182.0 182.0 20.0
TPS61163AYFFR DSBGA YFF 9 3000 182.0 182.0 20.0

Pack Materials-Page 2
 PACKAGE OUTLINE
YFF0009 SCALE 10.000
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER
D

0.625 MAX C

SEATING PLANE
0.30
BALL TYP 0.05 C
0.12

0.8 TYP

B SYMM
0.8
TYP D: Max = 1.336 mm, Min =1.276 mm
0.4 TYP
E: Max = 1.336 mm, Min =1.276 mm
A
0.3 1 2 3
9X
0.2
0.015 C A B SYMM

0.4 TYP

4219552/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YFF0009 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

9X ( 0.23)
1 2 3
A

(0.4) TYP
SYMM
B

SYMM

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX METAL UNDER

( 0.23) 0.05 MIN
METAL SOLDER MASK

SOLDER MASK ( 0.23)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219552/A 05/2016
NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YFF0009 DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

9X ( 0.25) (R0.05) TYP

1 2 3
A

(0.4) TYP
B SYMM

METAL
TYP
C

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4219552/A 05/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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