Combinational vs.

Sequential Logic

In Out
Logic Logic
In Out
Circuit Circuit

State

(a) Combinational (b) Sequential

Output = f(In) Output = f(In, Previous In)

 Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
V DD or V ss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
 Static CMOS Circuits

In Static CMOS circuits with n inputs, 2n transistors are needed.

nMOS block is a dual of the pMOS block.
 What ever is in series in nMOS, appears in parallel in pMOS and
vice versa.
CMOS gates consume power only during the transition of inputs.

3
Static complementary gate structure

Pull-up and pull-down networks

VDD

pull-up
network
inputs out
Pull-down
network
VSS

4
 Pull-up/pull-down network design
Pull-up and pull-down networks are duals.

To design one gate, first design one network, then compute
dual to get other network.

5
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high

A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors in Series/Parallel Connection

PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

Complementary CMOS Logic Style Construction (cont.)
NAND Gate

Va Vb Vout
0 0 1
0 1 1
1 0 1
1 1 0
9
NOR2 Gate

Va Vb Vout
0 0 1
0 1 0
1 0 0
1 1 0
10
Example Gate: COMPLEX CMOS GATE

VDD

B
A
C

D
OUT = D + A• (B+C)
A
D
B C
 4-input NAND Gate

Vdd
VDD
VDD
In1 In2 In3 In4
Out
In1

In2
Out Out In3

In4
GND
In1 In2 In3 In4
GND

In1 In2 In3 In4

Complex CMOS Structures

13
Xor gate

14
 AOI/OAI gates

AOI = and/or/invert; OAI = or/and/invert.

Implement larger functions.
Pull-up and pull-down networks are compact: smaller area,
higher speed than NAND/NOR network equivalents.

15
AOI example

invert

or

and

16
Problems

A C

B D
Y
A B

C D

17
 Problems

Design a CMOS circuit to implement the logic

Y = A'B' + B'C + C'A
Make a 2 input CMOS XOR gate to implement
Y = A  B.
CMOS XOR and XNOR gates are similar. Just one of the input
pairs (A and A' are reversed).

18
 Pseudo-nMOS
• Adding a single pFET to otherwise nFET-only
circuit produces a logic family that is called
pseudo-nMOS
• Less transistor than CMOS
• For N inputs, only requires (N+1) FETs
• Pull-up device: pFET is biased active since the
grounded gate gives VSGp = VDD
• Pull-down device: nFET logic array acts as a large Figure 4.1 General structure
of a pseudo-nMOS logic gate
switch between the output f and ground
• However, since the pFET is always biased on, VOL
can never achieve the ideal value of 0 V
• A simple inverter using pseudo-nMOS as Figure
4.2 
2
n
2V  V V  V  
DD Tn OL

OL
2
V  V 
2 p
(1)
DD Tp
2

V  V  V   V  V  

V  V 
2 (2) p 2
Figure 4.2 Pseudo-nMOS inverter
OL DD Tn DD Tn
n DD Tp
nFET Array in Pseudo-nMOS
 The design of nFET array of pseudo-nMOS is the
same as in standard CMOS
» Series and parallel logic FETs
» Smaller simpler layouts, and interconnect is much simpler
» However, the sizes need to be adjusted to insure proper
electrical coupling to the next stage
» Resize in physical design (a) General circuit

(a) NOR2 (b) NAND2 (b) Layout

Figure 4.3 Pseudo-nMOS NOR and NAND gates Figure 4.4 AOI gate
 Tri-State Circuits
• A tri-state circuit produces the usual 0 and 1
voltages, but also has a third high impedance Z
(or Hi-Z)
• Useful for isolating circuits from common bus lines
• In Hi-Z case, the output capacitance can hold a
voltage even though n hardwire connection exists

• A non-inverting circuit ( a buffer) can be

obtained by adding a regular static inverter to
the input

Figure 4.6 Tri-state layout

(a) Symbol and operation (b) CMOS circuit

Figure 9.5 Tri-state inverter

Clock-CMOS (C2MOS)
• Static CMOS: the output of a static logic
gate is valid so long as the input value are
valid and the circuit has stabilized
• However, logic delays are due to the
“rippling” through the circuits
• Not reference to any specific time base
• So on, Clock CMOS, or C2MOS is proposed

• C2MOS concept: non-overlapping clock

 t    t   0 (3) Figure 4.7 Clock signals

  t   VDD   t  (4)
• But in physical signal, the clocks may overlap
slightly during a transition
C2MOS Networks
 C2MOS is composed of a static logic circuit with tri-state output network
(made up of FETs M1 and M2) that is controlled by  and 
» When   0 , both M1 and M2 are active, and become to a standard static logic gate
» When   1 , both M1 and M2 are cutoff, so the output is a Hi-Z state

Figure 4.8 Structure of a C2MOS gate

Example of C2MOS

(a) NAND2

(a) Inverter (b) NAND2

Figure 4.10 Layout examples of C2MOS circuits

(b) NOR2
Figure 4.9 Example of C2MOS logic gate
 Leakage in C2MOS (1/2)
• Charge leakage: since the output node cannot
hold the charge on Vout very long
• This places a lower limit on the allowable clock
frequency
• If a voltage is applied to the drain or source, a
small leakage current flows into, or out of, the
device
• One reason is due to the required bulk connections (a) Bulk leakage currents
• The current off of the capacitor by iout
iout  in  i p
dV (5)
 Cout
dt
dV
I L  Cout
dt
(6)

t I 
V (t )

V dV   0  Cout dt
 L (7)
1 (b) Logic 1 voltage decay

 I  Figure 4.11 Charge leakage problem

V (t )  V1   L t (8)
 Cout 
Dynamic CMOS Logic Circuits (1/2)
• A dynamic logic gate uses clocking and
charge storage properties of MOSFETs to
implement logic operations
• Provide a synchronized data flow
• Result is valid only for a short period of time
• Less transistors, and may be faster than
static cascades

• Based on the circuit in Figure 4.13

• The clock  drives a complementary pair of
transistors Mn and Mp
• An nFET array between the output node
and ground to perform the logic function
• When   0 , it is called precharge phase
• When   1 , it is called evaluation phase
Figure 4.13 Basic dynamic logic gate
Dynamic CMOS Logic Circuits (2/2)
• A dynamic NAND3 is shown in Figure 9.18

f  a bc

• When f = 1, charge leakage reduces the voltages held on

the output node

Figure 4.14 Dynamic logic gate example

Leakage
• Dynamic node floats high during evaluation
• Transistors are leaky (IOFF  0)
• Dynamic value will leak away over time
• Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
• Must be weak enough not to fight evaluation
weak keeper
 1 k
X
H Y
A 2
2

Circuit Families Slide 29

Charge Sharing
• Dynamic gates suffer from charge sharing


Y A
A x CY
Y
B=0 Cx

Circuit Families Slide 30

Charge Sharing
• Dynamic gates suffer from charge sharing


Y A
A x CY
Y
B=0 Cx Charge sharing noise

Vx  VY 

Circuit Families Slide 31

Charge Sharing
• Dynamic gates suffer from charge sharing


Y A
A x CY
Y
B=0 Cx Charge sharing noise

CY
Vx  VY  VDD
C x  CY

Circuit Families Slide 32

Secondary Precharge
• Solution: add secondary precharge transistors
• Typically need to precharge every other node
• Big load capacitance CY helps as well
secondary
 precharge
Y transistor
A x
B

Circuit Families Slide 33

Noise Sensitivity
• Dynamic gates are very sensitive to noise
• Inputs: VIH  Vtn
• Outputs: floating output susceptible noise
• Noise sources
• Capacitive crosstalk
• Charge sharing
• Power supply noise
• Feedthrough noise
• And more!

Circuit Families Slide 34

 Domino Logic (1/2)
• Domino logic is a CMOS logic style obtained by
adding a static inverter to the output of the
basic dynamic gate circuit
• Non-inverting
• Cascade operation
• “Domino chain reaction” that must start at the first
stage and then propagate stage by stage to the
output
Figure 4.16 Domino logic stage

(a) AND gate (b) OR gate

Figure 4.18 Layout for
Figure 4.17 Non-inverting domino logic gates
domino AND gate
Domino Logic (2/2)

 Note that the operation indicates that domino gates are only useful in cascades

(a) Single-FET charge keeper (b) Feedback controlled keeper

Figure 4.19 A domino cascade Figure 4.20 Charge-keeper circuits

f1  G
f2  F  G

(a) Percharge (b) Evaluate

Figure 4.21 Visualization of the domino effect Figure 4.22 Structure of a MODL circuit
 Dual-Rail Logic Networks
• Single-rail logic: the value of a variable is either a 0 or a 1 only

• Dual-rail logic: both the variable x and its complement x are

used to form the difference
f x  ( x  x)

df x  dx d x 
   
dt  dt dt 

dx dx

dt dt

df x dx
2
dt dt
 Differential Cascode Voltage Switch Logic, DCVS (1/2)
• DCVS or differential CVSL (CVSL) provides for
dual-rail logic gates, and the out results f and f
are held until the inputs induce a change

(a) AND/NAND

Figure 4.23 Structure of a CVSL logic gate (b) OR/NOR

Figure 4.24 CVSL gate example
Complementary Pass-Transistor Logic
• Complementary Pass-Transistor (CPL): an dual-
rail tech. that is based on nFET logic equations

f  a b  a a
(a) AND gate (b) AND/NAND array
 ab  a  a  b  ab
Figure 4.25 CPL AND/NAND circuit

• CPL has several 2-input gates that can be

created by using the same transistor topology
with different input sequences
• Less layout area
• However, threshold will be loss and the fact that
an input variable may have to drive more than
one FET terminal
(a) OR/NOR (b) XOR/XNOR

Figure 4.26 2-input CPL arrays