EEE411/ECE411

LECTURE 8
VLSI Design
Introduction

■ What makes a circuit fast?

– I = C dV/dt -> tpd ∝ (C/I) ∆V d
s
kC
– low capacitance R/k
kC
d 2R/k
– high current g k
d
kC
g g k
– small swing s kC s
g
kC
kC
■ pMOS are the enemy! s
d
– High capacitance for a given current
■ Can we take the pMOS capacitance off the input?
■ Various circuit families try to do this…

Article 9.2.4 – CMOS VLSI Design, 4th Edition

Pseudo-nMOS

■ In the old days, nMOS processes had no pMOS

– Instead, use pull-up transistor that is always ON
■ In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of pulldown network
𝑊
𝐼𝐷 ≈ 𝜇𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝐻 𝑉𝐷𝑆
𝐿 𝐺𝑆
1.8
load
P/2 1.5
𝐼𝐷 1 𝑊
Ids 1.2 = = 𝜇𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝐻
P = 24
𝑉𝐷𝑆 𝑅 𝐿 𝐺𝑆
Vout Vout 0.9

16/2 1
0.6
𝑃
Vin P = 14 𝑅∝ 𝑊=
0.3
P=4 𝑊 2
0 2
0 0.3 0.6 0.9 1.2 1.5 1.8 𝑅∝
Vin 𝑃
Pseudo-nMOS Power
=VDD
load
P/2
■ Pseudo-nMOS draws power whenever Vout = 0
Ids
– Called static power P = IDDVDD Vout =0
– A few mA / gate * 1M gates would be a problem 16/2
Vin
– Explains why nMOS went extinct
■ Use pseudo-nMOS sparingly for wide NORs
■ Turn off pMOS when not in use

en
Y
A B C
Dynamic Logic
■ Dynamic gates uses a clocked pMOS pullup
■ Two modes: pre-charge and evaluate

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

• Too much gate capacitance • Short circuit current when Y=0 • Problem ??
• Large delay • Large short circuit power loss
 2 2/3  1
Dynamic Logic A
1
Y
A 4/3
Y
A 1
Y

VDD VDD VDD

Static Pseudo-nMOS Dynamic
VDD VDD VDD

Y=GND

Y=VDD Y=VDD
Y=VDD Y=VDD Y=VDD

 Precharge Evaluate Precharge  Precharge Evaluate Precharge

Y Y

A A
 Dynamic Logic
VDD VDD VDD

Y=GND

Y=GND Y=VDD 2 2/3  1

A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

 Precharge Evaluate Precharge

A
 Compare

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

• Too much gate capacitance • Short circuit current when Y=0 • Input must be 0 during pre-charge
• Large delay • Large short circuit power loss
The Foot

VDD VDD
■ What if pulldown network is ON during precharge?
■ Use series evaluation transistor to prevent fight.

 
precharge transistor Y Y Y=VDD Y=VDD

Y inputs inputs
A f f
A=0 A=1
foot
footed unfooted
 Monotonicity
■ Dynamic gates require monotonically rising inputs during evaluation
– 0 -> 0 VDD
 VDD VDD
– 0 -> 1
A
– 1 -> 1
– But not 1 -> 0
Y=VDD Y=GND
violates monotonicity
Y=GND
during evaluation
A
A=1 A=1 A=0
 Precharge Evaluate Precharge

Output should rise but does not

Monotonicity Woes
=0 =1
=1 =0
■ But dynamic gates produce monotonically
=1 =1 =1 =0
falling outputs during evaluation
■ Illegal for one dynamic gate to drive
another!

A=1

  Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot
 Compare


2 2/3  1
A Y Y Y A
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic Foot

• Too much gate capacitance • Short circuit current when Y=0 • Input must be 0 • Input can only rise
• Large delay • Large short circuit power loss during pre-charge during evaluation
• Cannot drive next
stage
 Domino Gates
■ Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
 Precharge Evaluate Precharge

domino AND domino AND W

=1 =1 =0 =0 X
W X=0 Y Z=0 W X=1 Y Z=1
A A Y
=0 B
=1 C
B
=0 C
=0 =1 =1 Z
 
=0 =1
 
dynamic static dynamic static  
NAND inverter NAND inverter A W X A X
H Y =
B H Z B Z
C C
 Compare


2 2/3  1
A Y Y Y A
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic Foot Domino

• Too much gate • Short circuit current • Input must be 0 • Input can • Only
capacitance when Y=0 during pre-charge only rise noninverting
• Large delay • Large short circuit during output
power loss evaluation
• Cannot
drive next
stage
Dual-Rail Domino
sig_h sig_l Meaning
■ Domino only performs noninverting functions:
0 0 Precharged
– AND, OR but not NAND, NOR, or XOR
0 1 ‘0’
■ Dual-rail domino solves this problem
1 0 ‘1’
– Takes true and complementary inputs
1 1 invalid
– Produces true and complementary outputs

Y_l  Y_h

inputs
f f


Example: AND/NAND
 Example: XOR/XNOR

■ Sometimes possible to share transistors

Y_l  Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h


Leakage
 
=0 =1 =1
■ Dynamic node floats high during evaluation A
=1->0
A
– Transistors are leaky (IOFF ≠0) =0 =0
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds
■ Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper weak keeper
 1 k  1 k
=0 X
H Y =0 =1 X
H Y =0
A 2
=1 A 2
=1
=0 =0
2 2
Charge Sharing
■ Dynamic gates suffer from charge sharing


  =?
=0 =1 =1
Y Y
A x CY A =1 √x CY A
=0
Cx Cx Y
B=0 B=0
Charge sharing noise

𝑄𝑌 = 𝐶𝑌 𝑉𝑌 ⟺ 𝑄𝑌 =⇑ (𝐶𝑌 + 𝐶𝑌 )𝑉𝑌 ⇓
Secondary Precharge

■ Solution: add secondary precharge transistors

– Typically need to precharge every other node
■ Big load capacitance CY helps as well

secondary
 precharge
Y transistor
A x
B
Noise Sensitivity

■ Dynamic gates are very sensitive to noise

– Outputs: floating output susceptible noise
■ Noise sources
– Capacitive crosstalk
– Charge sharing
– Power supply noise
– Feedthrough noise
– And more!
Power

■ Domino gates have high activity factors

– Output evaluates and pre-charges
■ If output probability = 0.5, α = 0.5
– Output rises and falls on half the cycles
– Clocked transistors have α = 1
■ Leads to very high power consumption
Domino Summary

■ Domino logic is attractive for high-speed circuits

– 1.3 – 2x faster than static CMOS
– But many challenges:
■ Monotonicity, leakage, charge sharing, noise, power
■ Widely used in high-performance microprocessors in 1990s when speed was king
■ Largely displaced by static CMOS now that power is the limiter
■ Still used in memories for area efficiency
 Compare


2 2/3  1
A Y Y Y A
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic Foot Domino

• Too much gate • Short circuit current • Input must be 0 • Input can • Monotonicity
capacitance when Y=0 during pre-charge only rise • Leakage
• Large delay • Large short circuit during • Charge
power loss evaluation Sharing
• Cannot • Noise
drive next • power
stage
Pass Transistor Circuits
■ Use pass transistors like switches to do logic
■ Inputs drive diffusion terminals as well as gates

■ CMOS + Transmission Gates:

– 2-input multiplexer
– Gates should be restoring
S
S S
A
A A S Y
S Y S Y B
B B
S
S S
LEAP
■ LEAn integration with Pass transistors
■ Get rid of pMOS transistors
– Use weak pMOS feedback to pull fully high
– Ratio constraint

S =1

A
=1 =1
S L Y =0
B
CPL 𝑉𝐷𝐷
S 𝑆 = 𝑉𝐷𝐷
𝐺=𝐴
■ Complementary Pass-transistor Logic A 𝐷=𝐴
– Dual-rail form of pass transistor logic S L Y
𝐴
– Avoids need for ratioed feedback 𝑌=𝐴
B
– Optional cross-coupling for rail-to-rail swing
S =1
A 𝐴 𝐷=𝐴
S L Y 𝑌=𝐴
𝐺=𝐴
B 𝑆 = 𝑉𝐷𝐷
S 𝑉𝐷𝐷

A
S L Y
𝐴
B
Pass Transistor Summary

■ Researchers investigated pass transistor logic for general purpose applications in

the 1990’s
– Benefits over static CMOS were small or negative
– No longer generally used
■ However, pass transistors still have a niche in special circuits such as memories
where they offer small size, and the threshold drops can be managed
 Compare
S

2 2/3  1 A
S Y
A Y Y Y A
B
1 A 4/3 A 1
S

Static Pseudo-nMOS Dynamic Foot Domino Pass

• Too much gate • Short circuit current • Input must be 0 • Input can • Monotonicity • Input loading
capacitance when Y=0 during pre-charge only rise • Leakage • Signal
• Large delay • Large short circuit during • Charge degrade
power loss evaluation Sharing
• Cannot • Noise
drive next • power
stage