Experiment No.
-3
Date of Performance:
Date of Submission:
Circuit Implementation/Program
Execution/ formation/ Timely
correction/ Viva Experiment
Submission Sign with Date
ethical practices Answers Total
(06) (01) (03) (10)
Experiment3
3.1 Aim: Verify truth table of SR, JK, T and D flip flops.
3.2 Course Outcome: Implement Synchronous and Asynchronous Sequential Circuits and
Finite
state machine
3.3 Learning Objectives: To understand the fundamentals of sequential circuits.
3.4 Requirements: Trainer kit, IC 7400, IC7411, IC7410, Connecting wires.
3.5 Related Theory:
A flip flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers,
communications.
Types of flipflop: 1) S-R flip flop 2) D flip flop 3) J-K flip flop 4) T flip flop
1) S-R flip flop:
There are two inputs to flipflop defined as S and R. When S=R=0 then output remains
unchanged. when S=1, R=0 the flip flop switches to the stable state where output is 1 i.e SET.
when S=0, R=1 the flip flop switches to the stable state where output is 0 i.e RESET. when
S=1, R=1 the flip flop switches to the stable state where output is forbidden.
2) J-K flip flop:
A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is that the
intermediate state is more refined and precise than that of a S-R flip flop. The behavior of inputs J and K
are the same as the S and R inputs of the S-R flip flop. When both the inputs J and K have a HIGH state,
the flip-flop switches to the complement state. So, for a value of Q = 1, it switches to Q=0 and for a value
of Q = 0, it switches to Q=1. The combination J = 1, K = 0 is a command to set the flip-flop; the
combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command
to toggle the flip flop, i.e., change its output to the logical complement of its current value.
The output may be repeated in transitions once they have been complimented for J=K=1 because of the
feedback connection in the JK flip-flop. This can be avoided by setting a time duration lesser than the
propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a
master-slave or edge-triggered construction.
3) D flip flop:
A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop by connecting the R input
through an inverter, and the S input is connected directly to data input. The modified clocked SR flip-flop is known
as D-flip-flop and is shown below.
4) T flip flop:
T flip-flop is known as toggle flip-flop. The T flip-flop is a modification of the J-K flip-flop. Both the JK
inputs of the JK flip flop are held at logic 1 and the clock signal continues to change.
3.6 Procedure:
1. Place the breadboard gently on the observation table.
2. Fix the IC which is under observation between the half shadow line of the breadboard, so
there is no shortage of voltage.
3. Connect the wire to the main voltage source (Vcc) whose other end is connected to the last
pin of the IC (14 place from the notch).
4. Connect the ground of IC (7th place from the notch) to the ground terminal provided on
the digital lab kit.
5. Give the input at the gate of the ICs by using connecting wires. (In accordance with provided).
6. Connect output pins to the LED on the digital lab kit.
7. Switch on the power supply.
8. If led glows then output is true, if it doesn’t glow output is false, which is numerically denoted as 1 and 0
respectively.
9. Verify the truth table.
3.7 Precautions:
1. All ICs should be checked before starting the experiment.
2. All the connections should be tight.
3. Always connect ground first and then connect Vcc.
4. Use suitable wire should be used for different types of circuit.
5. The kit should be off before changing the connections.
6. After the completion of the experiment, switch off the supply of the apparatus.
1. SR Flip Flop
2. JK Flip Flop
3. D Flip Flop
4. T Flip Flop
3.8 Conclusion:
In conclusion, we successfully verified the truth tables of SR, JK, T, and D flip-flops. The
observed outputs for each flip-flop matched the expected values, confirming the correct
operation and behavior of these flip-flops in various input conditions.
3.9 Questions:
