Digital Systems Design: Synchronous Counter
BECE102L
Dr Sidharth Gautam
Sr. Assistant Professor
Department of Embedded Technology, SENSE
sidharth.gautam@vit.ac.in
Cabin : SJT-710K
𝟏
𝑻𝟎 𝑸𝟎
Synchronous Counter
𝑻𝟏 𝑸𝟏 𝑻𝟐 𝑸𝟐
FF-0 FF-1 FF-2
𝑪𝑳𝑲
All FF are triggered by common clock pulse.
Since all FF change their state in synchronization with clock pulse, so
any FF can be used (SR, JK, T, D) Designing of synchronous counter:
o/p of LSB FF is complemented with every clock pulse and i/p of
other FF are driven by some combination of FF o/p. 1) Find #no. of FF required:
Any-type of count sequence is possible. 2𝑛 ≥ 𝑀
2) Draw State-transition diagram for all valid states.
All FF’s are applied with same frequency. 3) Write transition table using excitation table(FF).
4) Find minimal expression for FF inputs using K-Map.
Parallel counter 5) Design the logic diagram of counter.
▪ Synchronoss counter Modulus (M): 2𝑛
▪ Ring counter Modulus (M): 𝑛 Present state Next state Required FF
▪ Johnson Counter Modulus (M): 2𝑛 Excitation Inputs
▪ Divide-by-M counter: 𝑸𝟐 𝑸𝟏 𝑸𝟎 𝑄2+ 𝑄1+ 𝑄0+
1 1
▪ Ring counter : 𝑓𝑑 = Johnson Counter: 𝑓𝑑 =
𝑛 2𝑛
Note: Excitation i/p’s corresponding to invalid state
are taken as don’t care
1. Design a Mod-3 Up Counter using JK-FF
Step-1: #No. of flip-flops Step-2: State Diagram:
2𝑛 ≥ 𝑀
2𝑛 ≥ 3, 𝑛=2
Step-3: Transition table
Step-5: Logic Diagram:
Step-4: K-map Simplification
2. Find the inputs of a Mod-10 Up Counter using JK-FF
Step-1: #No. of flip-flops Step-2: State Diagram:
𝑛
2 ≥𝑀
2𝑛 ≥ 10, 𝑛=4
Step-3: Transition table
Note that six states 1010, 1011, 1100, 1101, 1110 and 1111 are invalid, so the excitation inputs corresponding to these
states are taken as don’t care and hence these states are not included in state diagram as well as in the excitation table.
Step-4: K-map Simplification
3. Design a sequential counter as shown in the state
diagram using JK flip-flop
Step -1: The number of flip-flops
This counter has 7 different states, so it requires 3 FFs as:
Step-2: State transition Diagram
State diagram of desired counter is already given in the problem.
Step-3 : Transition-table
JK flip-flops are selected and the excitation table of this counter
using JK flip-flops is need to be drawn.
NOTE: The entries for excitations corresponding to invalid state
(101) is assumed as don’t cares and not included in the table
Transition-table
Now we can use K-map Simplification for finding minimal expression of FF Inputs and draw a logic diagram.
4. Design a synchronous counter that goes through states
0, 3, 5, 6, 0 using T-FF.
Step -1: The number of flip-flops
This counter has only four stable states, but it requires three
FFs, because it is counting up to 110 (2𝑛 ≥ 𝑀)
Ring Counter State-Diagram: 4-bit Ring Counter Count Sequence of a 4-bit
Johnson Counter
❑ 𝑛-bit counter = 𝑛-FF (D-type)
❑ Modulus (M) = 𝑛
▪ Count sequence of length 𝑛.
▪ Maximum used state: 𝑛
▪ Unused state: 2𝑛 − 𝑛
❑ Comprises of only D-FF.
❑ Constructed by providing output of the last-FF (MSB) to the D input of the first-FF.
Logic diagram: 4-bit Ring counter
Ring Counter
Let us assume that flip-flop FF-0 is initially set to a ‘1’ and all other flip-flops are reset to ‘0’.
The counter output is therefore 𝑄0 𝑄1 𝑄2 𝑄3 = 1000. With the first clock pulse, this ‘1’ gets
shifted to the second flip-flop output and the counter output becomes 0100. Similarly, with the
second and third clock pulses, the counter output will become 0010 and 0001. With the fourth
clock pulse, the counter output will again become 1000. The sequence repeats after four clock
pulses
Count Sequence of a 4-bit
Johnson Counter
Logic diagram: 4-bit Ring counter
Count Sequence of a 4-bit Johnson Counter
Johnson Counter
❑ 𝑛-bit counter = 𝑛-FF (D-type)
❑ Modulus (M) = 2𝑛
▪ Count sequence of length 2𝑛.
▪ Maximum used state: 2𝑛
▪ Unused state: 2𝑛 − 2𝑛
State-Diagram: 4-bit Johnson Counter
❑ Comprises of only D-FF.
❑ Constructed by providing inverted output of the last-FF (MSB) to the D input of the first-FF.
Logic diagram: 4-bit Johnson counter
