Digital Circuits Lap (MTE 223)

(ALL RIGHTS BELONG TO THEIR

RESPECTIVE OWNERS)

• Decoder
• Mux
• Flip Flop

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 Decoders
• A decoder is a digital circuit that detects the
presence of a specified combination of bits
(code) on its inputs and indicates the presence
of that code by a specified output level.
• General form, a decoder has n input lines to
handle n bits and from one to 2𝑛 output lines
to indicate the presence of one or more n-bit
combinations.

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 Decoders
• Extract “Information” from the code Only one
• Binary Decoder lamp will
turn on
– Example: 2-bit Binary Number

0 1 2 3
1
X1 0
0
Binary 0
X0 0 Decoder
0

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 Decoders
• 2-to-4 Line Decoder
Y3

Y2
y3
Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0

I1 I0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 = I1 I 0 Y0 = I1 I 0
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 Decoders
• Active-High / Active-Low
I1 I0 Y 3 Y 2 Y 1 Y 0 I1 I0 Y 3 Y 2 Y 1 Y 0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y1
Y3 Y3
Decoder

I1 I1 Decoder
Binary
Binary

Y2 Y2 Y0

Y1 Y1
I0 Y0 I0 Y0 I1
I0

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 Decoders
Y7 = I 2 I1 I 0
• 3-to-8 Line Decoder
Y6 = I 2 I1 I 0

Y5 = I 2 I1 I 0
Y7 Y4 = I 2 I1 I 0
Y6
Y5 Y3 = I 2 I1 I 0
Decoder

I2
Binary

Y4 Y2 =
I1 I 2 I1 I 0
Y3
I0 Y2 Y1 = I 2 I1 I 0
Y1
Y0 = I 2 I1 I 0
Y0
I2
I1
I0

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 Decoders
• “Enable” Control Y3

Y3 Y2

Decoder
I1
Binary Y2
I0
Y1 Y1
E
Y0
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0 If the enable is active, it behaves as a regular
decoder. If it's not active, then all outputs are
1 1 1 1 0 0 0 0. It is used to select one output
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 Multiplexers
• 2-to-1 MUX I0

I0 Y
I1
MUX Y I1
S
S
• The circuit has two data input lines, one output line,
and one selection line S.
• When
• S = 0 the upper AND gate is enabled and 𝐼0 has a
path to the output.
• S = 1, the lower AND gate is enabled and 𝐼1 has a
path to the output.

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 Assignment No. 2
▪ find output in a minterm
3x8 Decoder
▪ Determine the function
Y7
Y6
x Y5
I2
y Y4
I1
z Y3
I0 Y2
Y1
Y0

A B
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 Multiplexers
• 4-to-1 MUX
D0
D1
D2
MUX Y
D3
S1 S0

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 Implementation Using Multiplexers
• Example: F(x, y) = ∑(0, 1, 3)
The largest input number is 3 which is
represented in 2 bits, so it is required to use 2
select lines. Therefore we can use a 4 x 1 Mux
x y F 1 I0
0 0 1 1 I1
MUX Y F
0 1 1 0 I2

1 I3
1 0 0 S1 S0
1 1 1
x y

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 Implementation Using Multiplexers
• Example: F(x, y, z) = ∑(1, 2, 6, 7) using 4 to 1 MUX

x y z F
0 0 0 0 z I0

0 0 1 1
F=z z I1
F
0 I2 MUX Y
0 1 0 1
0 1 1 0
F=z 1 I3
S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1 When xy= 00 output F is equal Z
F=1 because F = 0 when z = 0 & F = 1
1 1 1 1
when z = 1.
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 Implementation Using Multiplexers
• Example: F(x, y, z) = ∑(1, 2, 6, 7)

0 I0
x y z F 1 I1
0 0 0 0 1 I2

0 0 1 1 0 I3
0 I4 MUX Y F
0 1 0 1
0 I5
0 1 1 0
1 I6
1 0 0 0 1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z
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 Implementation Using Multiplexers
• Example: F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
using 8-to-1 MUX
A B C D F
0 0 0 0 0
0 0 0 1 1
F=D D I0
0 0 1 0 0 I1
F=D D
0 0 1 1 1
0 1 0 0 1 D I2
F=D
0 1 0 1 0 I3
0
0
0
1
1
1
1
0
1
0
0
F=0 0 I4 MUX Y F
1 0 0 0 0 D I5
1 0 0 1 0 F=0
1 0 1 0 0 1 I6
F=D
1 0 1 1 1 I7
1 1 0 0 1
1
F=1 S2 S1 S0
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1
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A B C 14
 Sequential Circuits
• A combinational circuit with a memory element which is
connected feedback
• Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

• Synchronous
Inputs Outputs
Combinational
Circuit

Flip-flops
Clock

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 Latches
• The latch is a type of temporary storage device that has two
stable states (bistable)
• An active-HIGH input S-R (SET-RESET) latch is formed with two
cross-coupled NOR gates
• An active-LOW input 𝑆-ҧ 𝑅ത latch is formed with two cross-
coupled NAND gates
• Notice that the output of each gate is connected to an input
of the opposite gate.
R S
Q Q

Q Q
S R
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 Latches
S R Q0 Q Q’
• SR Latch 0 0 0 0 1 Q = Q0

0 0
R Q

S Q
0 1

Transition Table
Initial Value Or
Action Tble
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 Latches
S R Q0 Q Q’
• SR Latch 0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

0 1
R Q

S Q
0 0

Transition Table
Or
Action Tble
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 Latches
S R Q0 Q Q’
• SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
1 1
R Q
0 1 1 0 1 Q=0

S Q
0 0

Transition Table
Or
Action Tble
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 Latches
S R Q0 Q Q’
• SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
1 0
R Q

S Q
0 1

Transition Table
Or
Action Tble
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 Latches
S R Q0 Q Q’
• SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
0 0
Q=0
R Q
0 1 1 0 1
1 0 0 1 0 Q=1

S Q
1 1

Transition Table
Or
Action Tble
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 Latches
S R Q0 Q Q’
• SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
0 1
Q=0
R Q
0 1 1 0 1
1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

Transition Table
Or
Action Tble
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 Latches
S R Q0 Q Q’
• SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
1 0
Q=0
R Q
0 1 1 0 1
1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

Transition Table
Or
Action Tble
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 Latches
S R Q0 Q Q’
• SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
1 10
Q=0
R Q
0 1 1 0 1
1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’

S Q
1 0

Transition Table
Or
Action Tble
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 Latches
• SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset

1 0 1 Set

S Q 1 1 Q=Q’=0 Invalid (Hazard)

S S R Q
Q
0 0 Q=Q’=1 Invalid (Hazard)
0 1 1 Set

1 0 0 Reset
R Q
1 1 Q0 No change

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 Controlled Latches
• Determine the Q output waveform if the
inputs shown in figure are applied to a gated
S-R latch that is initially RESET.

R R
Q
EN
S Q
S

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 Controlled Latches
• SR Latch with Control Input ( Clock Pulses - Enable)
R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
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 Controlled Latches
• D Latch (D = Data) Timing Diagram

S C
D
Q
C D
R Q
Q

t
C D Q
Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

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 Controlled Latches
• D Latch (D = Data) Timing Diagram

S C
D
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

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 Homework
The D latch is constructed with four NAND gates and an
inverter. Consider the following three other ways for
obtaining a D latch. In each case, draw the logic diagram
and verify the circuit operation.
(a) Use NOR gates for the SR latch part and AND gates
for the other two. An inverter may be needed.
(b) Use NOR gates for all four gates. Inverters may be
needed.
(c) Use four NAND gates only (without an inverter). This
can be done by connecting the output of the upper gate
that goes to the SR latch to the input of the lower gate
instead of the inverter output.

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 Flip-Flops
• Controlled latches are level-triggered

• Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

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 D Flip-Flop
Timing Diagram

S
CLK
D
Q
CLK
D
R Q Q_FF

CLK D Q Q_Latch
0 0 Reset
1 1 Set

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 D Flip-Flop
• D Flip-Flop Symbols

D Q D Q

CLK Q CLK Q
Negative Edge Positive Edge
D Flip-Flop D Flip-Flop

D Q

E Q

D Latch
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 Edge-Triggered D Flip-Flop

• The dynamic indicator (>) denotes the fact

that the flip-flop responds to the edge
transition of the clock.
• A bubble outside the block adjacent to the
dynamic indicator designates a negative edge
for triggering the circuit.
• The absence of a bubble designates a positive-
edge response.

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 Flip-Flops
• Master-Slave D Flip-Flop
D D Q D Q Q
D FF D FF
(Master) (Slave)
Master Slave

CLK CLK

Q_M

CLK’
Q_S
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 Flip-Flops
• There are three operations that can be
performed with a flip-flop: Set it to 1, reset it to
0, or complement its output. With only a single
input.
• D flip-flop can set or reset the output, depending
on the value of the D input immediately before
the clock transition.
• Synchronized by a clock signal, the JK flip-flop has
two inputs and performs all three operations.
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 Flip-Flops
• JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q

D = JQ’ + K’Q K Q
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 Flip-Flops
• T Flip-Flop

T
D Q Q

CLK Q Q

D = TQ’ + T’Q

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 Flip-Flops
• T- Flip-Flop

T J Q T D Q

Q
K Q

T Q

D = TQ’ + T’Q = T  Q Q

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 Flip-Flop Characteristic Equations
• Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1 No change
J Q
0 1 0
Reset
0 1 1
K Q 1 0 0
Set
1 0 1
1 1 0
Toggle
1 1 1

When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.
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 Flip-Flop Characteristic Equations
• Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
J Q 0 0 1 1
0 1 0 0
Reset
0 1 1 0
K Q
1 0 0
Set
1 0 1
1 1 0
Toggle
1 1 1

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0

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 Flip-Flop Characteristic Equations
• Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0
No change
J Q 0 0 1 1
0 1 0 0
K Q 0 1 1 0 Reset
1 0 0 1
Set
1 0 1 1
1 1 0 Toggle
1 1 1
When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1

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 Flip-Flop Characteristic Equations
• Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 No change
0 1 0 0
0 1 1 0 Reset
K Q
1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle = Complement
1 1 1 0

When both J = K = 1 and D = Q’, the next clock edge complements the output.
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 Flip-Flop Characteristic Equations
• Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 K
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q 1 0 0 1 Q
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

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 JK Flip-Flop

• The waveforms in Figure are applied to the J, K, and clock

inputs as indicated. Determine the Q output, assuming that
the flip-flop is initially RESET.

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 Flip-Flop Characteristic Equations
• Analysis / Derivation
T Q(t) Q(t+1)
0 0 0
T D Q No change
0 1 1
Q 1 0
1 1 Reset

Set

Toggle

When T = 0 (J = K = 0), D = Q, so the clock edge leaves the output unchanged

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 Flip-Flop Characteristic Equations
• Analysis / Derivation
T Q(t) Q(t+1)
0 0 0
T D Q No change
0 1 1
Q 1 0 1 Toggle = Complement
1 1 0

When T = 1 (J = K = 1), D = Q’, the next clock edge complements the output.
The complementing flip-flop is useful for designing binary counters.

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 Flip-Flop Characteristic Tables
D Q D Q(t+1)
0 0 Reset

Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle
T Q T Q(t+1)
0 Q(t) No change
Q 1 Q’(t) Toggle
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 Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)
T Q T Q(t+1)

Q
0 Q(t)
Q(t+1) = T  Q
1 Q’(t)
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 Flip-Flops with Direct Inputs
• Asynchronous Reset
For active-LOW clear (reset) input

D Q R’ D CLK Q(t+1)
0 x x 0
Q
R
Reset

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 Flip-Flops with Direct Inputs
• Some flip-flops have asynchronous inputs that are used
to force the flip-flop to a particular state independently
of the clock.
• The input that sets the flip-flop to 1 is called preset
(PRE) or direct set .
• The input that clears the flip-flop to 0 is called clear
(CLR) or direct reset .
• When power is turned on in a digital system, the state
of the flip-flops is unknown. The direct inputs are
useful for bringing all flip-flops in the system to a
known starting state prior to the clocked operation.

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 Flip-Flops with Direct Inputs
• Asynchronous Reset
For active-LOW clear (reset) input

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset

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 Flip-Flops with Direct Inputs
• Asynchronous Preset and Clear
For active-LOW clear (reset) and preset (set) inputs
Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0

Q
CLR
Reset

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 Flip-Flops with Direct Inputs
• Asynchronous Preset and Clear
For active-LOW clear (reset) and preset (set) inputs
Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q
CLR
Reset

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 Flip-Flops with Direct Inputs
• Asynchronous Preset and Clear
For active-LOW clear (reset) and preset (set) inputs
Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset

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 Flip-Flops with Direct Inputs
• Asynchronous Preset and Clear
For active-HIGH clear (reset) and preset (set) inputs
Preset

PR PR CLR D CLK Q(t+1)

D Q 1 0 x x 1
0 1 x x 0
Q 0 0 0 ↑ 0
CLR 0 0 1 ↑ 1
Reset

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