Chapter –three

Common Digital Components

 Integrated Circuits
• Digital circuit are constructed with ICs
• IC is a small silicon semiconductor crystal,
called a chip, containing the electronic
components for the digital gates.
• The various gates are interconnected Inside
the chip to form the requited circuit.
• The chip is mounted in a ceramic or plastic
container, and connections are welded by thin
gold wires to external pins to form the
integrated circuit.
IC classified in to 4 by their logic operation

• SSI
– contain several independent gates in a single package.
– The inputs & outputs of the gates are connected directly to
the pins in the package.
– The number of gates is usually less than 10 and is limited
by the number of pins available in the IC.
• MSI
– have a complexity of approximately 10 to 200 gates in a
single package.
– They perform specific elementary digital functions such as
decoders, adders, and registers.
 …
• LSIC
– Contain between 200 and a few thousand gates in a
single package.
– They include digital systems such as processors,
memory chips, & programmable modules.
• VLSI
– contain thousands of gates within a single
package.
– Example are large memory arrays and complex
microcomputer chips.
Ic classify by the specific circuit technology
to which they belong.
• TTL Transistor-transistor logic
– is a widespread logic family
– Uses transistors to implement gates
• ECL Emitter-coupled logic
– Used in high-speed systems
– Uses special nonsaturated transistors to achieve
super fast speed.
 …
• MOS Metal-oxide semiconductor
– Used in circuits that have high component density
– uses unipolar transistors
• CMOS Complementary metal-oxide semiconductor

– also used in circuits that have high component density

– also uses unipolar transistors but connects them in a
complementary fashion
– more economical than MOS because of low power
consumption.
 Decoders
• A binary code of n bits is capable of representing up to 2n distinct
elements of the coded information.
• A decoder is a combinational circuit that converts binary
information from the n coded inputs to a maximum of 2n unique
outputs.
• If the n-bit coded information has unused bit combinations, the
decoder may have less than 2n outputs.
• Their purpose is to generate the 2n (or fewer) binary combinations
of the n input variables.
• A decoder has n inputs and m outputs and is also referred to as an
n x m decoder.
• Decoders include one or more enable inputs to control the
operation of the circuit.
 2-to-4 Binary Decoder
Truth Table:

X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0 F0 = X'Y'
1 0 0 0 1 0
1 1 0 0 0 1
F1 = X'Y

• From truth table, circuit for 2x4 F2 = XY'

decoder is:
• Note: Each output is a 2-variable F3 = XY
minterm (X'Y', X'Y, XY' or XY)

F0
X Y
X 2-to-4 F1
Y Decoder F2
F3
 3-
to-8
Bina Table:
Truth
ry F0 = x'y'z'
Dec
x y z F0 F1 F2 F3 F4 F5 F6 F7 F1 = x'y'z
oder
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 F2 = x'yz'
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0 F3 = x'yz
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0 F4 = xy'z'
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1 F5 = xy'z

F6 = xyz'
F0
F1 F7 = xyz
X
F2
Y
3-to-8 F3
Z
Decoder F4
F5
F6
x y z
F7

ENGIN112 L17: Encoders and Decoders October 10, 2003

 ….. binary-to-octal conversion
• The logic diagram of a 3-to-8-line decoder is the three data
inputs, A0, AI, and A2, are decoded into eight outputs,
each output representing one of the combinations of the
three binary input variables.
• Commercial decoders include one or more enable inputs
to control the operation of the circuit.
• The decoder is enabled when E is equal to 1 and disabled
when E is equal to O (At this time, none of the outputs
are selected & all out puts are equal to 0).
• Only one output is equal to 1 at any given time the other 7
out puts are equal to 0.
 2-to-4-Line Decoder
(with Enable input)-Active LOW output (1)...
 Encoders
• An encoder is a combinational circuit that performs the inverse
operation of a decoder.
• It has 2n (or less) input lines and n output lines.
• The output lines generate the binary code corresponding to the
input value.
• It is assumed that only one input has a value of 1 at any given
time; otherwise, the circuit has no meaning.
• The encoder can be implemented with OR gates whose inputs are
determined directly from the truth table.
• Output A0 =1 if the input octal digit is 1 or 3 or 5 or 7. Similar
conditions apply for the other two outputs.
• Al = D2 + D3 + D6 + D7
• A2 = D4 + Ds + D6 + D7
 8-to-3 Binary Encoder

At any one time, only

Inputs Outputs
one input line has a value of 1.
I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
I0
I1 y2 = I4 + I5 + I6 + I7
I2
I3 y1 = I2 + I3 + I6 + I7
I4
I5
I6
y0 = I1 + I3 + I5 + I7
I7
 multiplexer
• is a combinational circuit that receives binary information
from one of 2n input data lines and directs it to a single
output line.
• A 2n-to-1 multiplexer has 2n input data lines and n input
selection lines, whose bit combinations determine which input
data are selected for the output.
• The two selection inputs S1 and S0 are decoded to select a
particular AND gate.
• The outputs of the AND gates are applied to a single OR gate
to provide the single output.
• A function table can be used to describe the functionality of a
multiplexer.
 4-to-1 line multiplexer
• consider the case when S1S0 = 10.
• The AND gate associated with input I2 has two of
its inputs equal to 1.
• The third input of the gate is connected to I2,
• The other three AND gates have at least one input
equal to 0, which makes their outputs equal to O.
• The OR gate output is now equal to the value of
I2, thus providing a path from the selected input
to the output.
 .

Select Output
s1 s0 Y
0 0 D00
0 1 D01
1 0 D10
1 1 D11
 Registers
• It is a group of flip-flops capable of storing one bit
of information.
• An n-bit register has a group of n flip-flops and is
capable of storing any binary information of n bits.
• Registers can also have combinational gates that
perform certain data-processing tasks.
• The flip-flops hold the binary information and
• The gates control when and how new information
is transferred into the register.
 parallel Registers
• The transfer of new information into a register is
referred to as a register load.
• If the loading occurs simultaneously at a common clock
pulse transition, we say that the load is done in parallel.
• The load input in a register determines the action to be
taken with each clock pulse.
• When the load input is 1, the data from the input lines
is transferred into the register's flip-flops.
• When the load input is 0, the data inputs are inhibited
and the flip-flop maintains its present state.
 a register constructed with four D flip-
flops.
• The common clock input triggers all flip-flops, and
the binary data available at the four inputs are
transferred into the 4-bit register.
• The four outputs can be sampled at any time to
obtain the binary information stored in the register.
• The clear input goes to a special terminal in each
flip-flop. When this input goes to 0, all flip-flops are
reset.
• Note that the clock signal enables the D input but
that the clear input is independent of the clock.
 parallel & Shift Registers
• A register capable of shifting its binary
information in one or both directions is called
a shift register.
• It consists of a chain of flip-flops in cascade,
with the output of one flip-flop connected to
the input of the next flip-flop.
• All flip-flops receive common clock pulses
that initiate the shift from one stage to the
next.
 …
• A register capable of shifting its binary
information in one or both directions is called
a shift register.
• Shift registers are constructed by connecting
flip-flops in cascade, where the output of one
flip-flop is connected to the input of the next
flip-flop.
• All flip-flops receive common clock pulses that
initiate the shift from one stage to the next.
 Cont.………………
• A serial input shift register has a single external input
(called the serial input) entering an outermost flip-flop.
• Each remaining flip-flop uses the output of the
previous flip-flop as its input, with the last flip-flop
producing the external output (called the serial
output).
• A register capable of shifting in one direction is called a
unidirectional shift register.
• A register that can shift in both directions is called a bi-
directional shift register.
 Cont.………………..
• The most general shift register has the following capabilities:
– An input for clock pulses to synchronize all operations.
– A shift-right operation and a serial input line associated with the
shift- right.
– A shift-left operation and a serial input line associated with the shift-
left.
– A parallel load operation and n input lines associated with the
parallel transfer. N
– parallel output lines.
– A control state that leaves the information in the register unchanged
even though clock pulses are applied continuously.
• A mode control to determine which type of register operation
to perform.
 Cont.………………
• Function Table for Shift Register Mode Control
Mode Control
S1 S0 Register operation
0 0 No Change
0 1 Shift right (down)
1 0 Shift left (up)
1 1 Parallel load
 Binary Counters
• A register that goes through a predetermined sequence
of states upon the application of input pulses is called a
counter.
• The input pulses may be clock pulses or may originate
from an external source.
• A counter that follows a binary sequence is called a
binary counter.
• An n- bit binary counter is a register of n flip-flops along
with a combinational circuit that continually produces a
binary count of n bits having a value from 0 to 2n-1.
 …
• Going through a sequence of binary
numbers such as 0000, 0001, 0010, 0011,
and so on, we note that the lower-order
bit is complemented after every count
and every other bit is complemented
from one count to the next if and only if
all its lower-order bits are equal to 1.
 Cont.…………
• The most general binary counter register has the following
capabilities:
– An input for clock pulses to synchronize all operations.
– An increment operation that signals the register to increment its
value by 1.
– A parallel clear operation that sets all the flip-flop values to 0.
– A parallel load operation that sets all the flip-flop values
according to the values of n input lines associated with the
parallel load.
– n parallel output lines.
– A control state that leaves the information in the register
unchanged even though clock pulses are applied continuously.
 Memory Unit
• It is a collection of storage cells together with associated
circuits needed to transfer information in and out of storage.
• Memory stores binary information in groups of bits called
words.
• A memory word can be used to represent any type of binary-
coded information.
• A group of eight bits is called a byte.
• Most systems use memory words that are a multiple of eight.
• Thus, a 16-bit word contains two bytes. A 32-bit word
contains four bytes, and so on.
• The number of words it contains and the number of bits in
each word define the internal structure of a memory unit.
 Cont.………
• Special input lines called address lines select one particular
word.
• Each word in memory is assigned a unique address ranging
from 0 to 2k-1, where k is the number of address lines.
• Applying the k-bit binary address to the address lines does
the selection of a specific word in memory.
• A decoder inside the memory accepts the address and opens
the paths needed to select the bits of the specified word.
• Computer memories range from 1024 words, requiring an
address of 10 bits, to 2(32) words, requiring 3(2) address bits.
• Two major types of memory are used in computer systems:
 Random-Access Memory (RAM)
• The concept of random-access comes from the fact that the process of
locating a word in memory is the same and requires an equal amount of time
regardless of its physical location.
• Data transfers occur through the use of data input and output lines, address
selection lines, and control lines.
• The two operations that a random-access memory can perform are the read
and write.
• To perform the read operation, the address of the desired word in memory is
placed on the address selection lines and the read control line is activated.
The memory unit then places the desired data onto the data output lines.
• To perform the write operation, the address of the desired word to be placed
into memory is placed on the address selection lines, data to be written is
placed on the data input lines, and the write control line is activated.
 Read-Only Memory (ROM)
• Can only perform the read operation.
• Data placed in ROM must be done so during the hardware production
of the unit.
• The read operation on a ROM is identical to that of a RAM with the
exception being that there is no need for a read control line.
• One special type of ROM, called a programmable read-only memory
(PROM) allows the purchaser of the memory to write to the ROM one
time only.
• Another type of ROM, called an erasable PROM (EPROM) provides
the purchaser of the system the capability to modify the data in a
ROM.
• However, this must be done physically by placing the memory unit
under ultraviolet light for a specified amount of time.
 Chapter 4
Register Transfer language and
Micro operations

1
 Registers

BASIC COMPUTER REGISTERS

Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR

15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
 Registers
COMMON BUS SYSTEM

S1 S2
S0 Bus

Memory unit 7
4096 x 16
Address
Write Read
AR 1
LD INR CLR
PC 2
LD INR CLR

DR 3
LD INR CLR DR 16 Data Register
AR 12 Address Register
E AC 16 Accumulator
ALU AC 4 IR 16 Instruction Register
LD INR CLR PC 12 Program Counter
TR 16 Temporary Register
INPR INPR 8 Input Register
OUTR 8 Output Register
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 REGISTER TRANSFER AND MICROOPERATIONS

• Register Transfer Language

• Register Transfer

• Bus and Memory Transfers

• Arithmetic Micro operations

• Logic Micro operations

• Shift Microoperations

• Arithmetic Logic Shift Unit

 SIMPLE DIGITAL SYSTEMS

• Combinational and sequential circuits can be used to create simple

digital systems.

• These are the low-level building blocks of a digital computer.

• Simple digital systems are frequently characterized in terms of

- the registers they contain, and
- the operations that they perform.

• Typically,
- What operations are performed on the data in the registers
- What information is passed between registers
 Register Transfer Language
MICROOPERATIONS (1)

• The operations on the data in registers

are called microoperations.
• The functions built into registers are
examples of microoperations
- Shift
- Load
- Clear
- Increment
-…
 Register Transfer Language
MICROOPERATION (2)

An elementary operation performed (during one clock

pulse), on the information stored in one or more
registers

1 clock cycle
Registers ALU
(R) (f)

R  f(R, R)

f: shift, load, clear, increment, add, subtract, complement,

and, or, xor, …
 Register Transfer Language
ORGANIZATION OF A DIGITAL SYSTEM

• Definition of the (internal) organization of a computer

- Set of registers and their functions

- Microoperations set

Set of allowable microoperations provided

by the organization of the computer

- Control signals that initiate the sequence of

microoperations (to perform the functions)
 Register Transfer Language
REGISTER TRANSFER LEVEL

• Viewing a computer, or any digital system, in

this way is called the register transfer level

• This is because we’re focusing on

- The system’s registers
- The data transformations in them, and
- The data transfers between them.
 Register Transfer Language
REGISTER TRANSFER LANGUAGE

• Rather than specifying a digital system in words, a

specific notation is used, register transfer language

• For any function of the computer, the register

transfer language can be used to describe the
(sequence of) microoperations

• Register transfer language

- A symbolic language
- A convenient tool for describing the internal
organization of digital computers
- Can also be used to facilitate the design process
of digital systems.
 Register Transfer Language
DESIGNATION OF REGISTERS

• Registers are designated by capital letters, sometimes followed by

numbers (e.g., A, R13, IR)
• Often the names indicate function:
- MAR - memory address register
– PC - program counter
– IR - instruction register

• Registers and their contents can be viewed and represented in various

ways
- A register can be viewed as a single entity:

MAR

- Registers may also be represented showing the bits of data they

contain
 Register Transfer Language
DESIGNATION OF REGISTERS

• Designation of a register
- a register
- portion of a register
- a bit of a register

• Common ways of drawing the block diagram of a register

Register Showing individual bits

R1 7 6 5 4 3 2 1 0
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
 Register Transfer
REGISTER TRANSFER

• Copying the contents of one register to another is a register

transfer

• A register transfer is indicated as

R2  R1

- In this case, the contents of register R2 are copied (loaded)

into register R1
- A simultaneous transfer of all bits from the source R1 to
the destination register R2, during one clock pulse
- Note that this is non-destructive; i.e. the contents of R1 are
not altered by copying (loading) them to R2
 Register Transfer
REGISTER TRANSFER

• A register transfer such as

R3  R5

Implies that the digital system has

- the data lines from the source register (R5) to

the destination register (R3)
- Parallel load in the destination register (R3)
- Control lines to perform the action
 Register Transfer
CONTROL FUNCTIONS

• Often actions need to only occur if a certain condition is

true
• This is similar to an “if” statement in a programming
language
• In digital systems, this is often done via a control signal,
called a control function
- If the signal is 1, the action takes place

• This is represented as:

P: R2  R1

Which means “if P = 1, then load the contents of register

R1 into register R2”, i.e., if (P = 1) then(R2  R1)
 Register Transfer
HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Implementation of controlled transfer

P: R2 R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

•The same clock controls the circuits that generate the control
function and the destination register
• Registers are assumed to use positive-edge-triggered flip-
flops
 Register Transfer
SIMULTANEOUS OPERATIONS

• If two or more operations are to occur

simultaneously, they are separated with
commas

P: R3  R5, MAR  IR

• Here, if the control function P = 1,

- load the contents of R5 into R3, and
- at the same time (clock), load the
contents of register IR into register
MAR
 Register Transfer
BASIC SYMBOLS FOR REGISTER TRANSFERS

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2 R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A B, A
 Register Transfer
CONNECTING REGISTERS

• In a digital system with many registers, it is impractical to have

data and control lines to directly allow each register to be loaded
with the contents of every possible other registers

• To completely connect n registers  n(n-1) lines

• O(n2) cost
- This is not a realistic approach to use in a large digital system

• Instead, take a different approach

• Have one centralized set of circuits for data transfer - the bus
• Have control circuits to select which register is the source, and
which is the destination
 Bus and Memory Transfers
BUS AND BUS TRANSFER

Bus is a path (of a group of wires) over which information is

transferred, from any of several sources to any of several destinations.

From a register to bus: BUS  R

Register A Register B Register C Register D

Bus lines

How can we do it?

Register A Register B Register C Register D
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

B1C1 D1 B2C2D2 B3C3 D3 B4C4 D4

0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX

x
select
y

4-line bus
 Bus and Memory Transfers
TRANSFER FROM BUS TO A DESTINATION REGISTER

How can we do transfer to the registers?

Bus lines

Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3

z D0 D1 D2 D3
Select 2x4 E (enable)
w
Decoder

Register A Register B Register C Register D

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

B1 C1 D1 B2 C2 D2 B3 C3 D3 B4 C4 D4

4 x10 4 x1
0
4 x1
0
4 x1
0
MUX MUX MUX MUX

x
select
y

4-line bus
 Bus and Memory Transfers
BUS TRANSFER IN RTL

• Depending on whether the bus is to be mentioned

explicitly or not, register transfer can be indicated as
either

2 R1

orBUS R1, R2  BUS

• In the former case, the bus is implicit, but in the

latter, it is explicitly indicated
 Bus and Memory Transfers
MEMORY (RAM)

• Memory (RAM) can be thought as a sequential circuit

containing some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the
following
- n data input lines data input lines
- n data output lines n
- k address lines address lines
- A Read control line k RAM
Read
– A Write control line unit
Write

n
data output lines
 Bus and Memory Transfers
MEMORY TRANSFER

• Collectively, the memory is viewed at the register level as a

device, M.
• Since it contains multiple locations, we must specify which address
in memory we will be using
• This is done by indexing memory references
• Memory is usually accessed in computer systems by putting the
desired address in a special register, the Memory Address
Register (MAR, or AR)
• When memory is accessed, the contents of the MAR get sent to
the memory unit’s address lines

M
Memory Read
AR unit Write

Data out Data in

 Bus and Memory Transfers
MEMORY READ

• To read a value from a location in memory and load it into a

register, the register transfer language notation looks like
this:

R1  M[MAR]

• This causes the following to occur

- The contents of the MAR get sent to the memory
address lines
- A Read (= 1) gets sent to the memory unit
- The contents of the specified address are put on the
memory’s output data lines
- These get sent over the bus to be loaded into register
R1
 Bus and Memory Transfers
MEMORY WRITE

• To write a value from a register to a location in memory

looks like this in register transfer language:

M[MAR]  R1

• This causes the following to occur

- The contents of the MAR get sent to the memory
address lines
- A Write (= 1) gets sent to the memory unit
- The values in register R1 get sent over the bus to the
data input lines of the memory
- The values get loaded into the specified address in the
memory
 Bus and Memory Transfers
SUMMARY OF R. TRANSFER MICROOPERATIONS

A B Transfer content of reg. B into reg. A

AR DR(AD) Transfer content of AD portion of reg. DR into reg. AR
A  constant Transfer a binary constant into reg. A
ABUS R1, R2 ABUS Transfer content of R1 into bus A and, at the same time,
transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR  M Memory read operation: transfers content of
memory word specified by AR into DR
M  DR Memory write operation: transfers content of
DR into memory word specified by AR
 Arithmetic Microoperations
MICROOPERATIONS

• Computer system microoperations are of four types:

- Register transfer microoperations

- Arithmetic microoperations
- Logic microoperations
- Shift microoperations
 Arithmetic Microoperations
ARITHMETIC MICROOPERATIONS

• The basic arithmetic microoperations are

- Addition
- Subtraction
- Increment
- Decrement
• The additional arithmetic microoperations are
- Add with carry
- Subtract with borrow
- Transfer/Load
- etc. …
Summary of Typical Arithmetic Micro-Operations
R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement
 Logic Microoperations
LOGIC MICROOPERATIONS

• Specify binary operations on the strings of bits in registers

- Logic microoperations are bit-wise operations, i.e., they work on
the individual bits of data
- useful for bit manipulations on binary data
- useful for making logical decisions based on the bit value
• There are, in principle, 16 different logic functions that can be
defined over two binary input variables

A B F0 F1 F2 … F13 F14 F15

0 0 0 0 0 … 1 1 1 Why?
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1

• However, most systems only implement four of these

- AND (), OR (), XOR (), Complement/NOT
• The others can be created from combination of these
 Logic Microoperations

APPLICATIONS OF LOGIC MICROOPERATIONS

• Logic micro operations can be used to manipulate individual
bits or a portions of a word in a register
• Consider the data in a register A. In another register, B, is
bit data that will be used to modify the contents of A
– Selective-set AA+B
– Selective-complement AAB
– Selective-clear A  A • B’
– Mask (Delete) AA•B
– Clear AAB
– Insert A  (A • B) + C
– Compare AAB
– ...
 Logic Microoperations
SELECTIVE SET

• In a selective set operation, the bit pattern in B is

used to set certain bits in A

1 10 0 At
1010 B
1 11 0 At+1 (A  A + B)

• If a bit in B is set to 1, that same position in A gets

set to 1, otherwise that bit in A keeps its previous
value
 Logic Microoperations
SELECTIVE COMPLEMENT

• In a selective complement operation, the bit

pattern in B is used to complement certain bits in A

1100 At
1 01 0 B
0 11 0 At+1 (A  A  B)

• If a bit in B is set to 1, that same position in A gets

complemented from its original value, otherwise it
is unchanged
 Logic Microoperations
SELECTIVE CLEAR

• In a selective clear operation, the bit pattern in B

is used to clear certain bits in A

1100 At
1010 B
0100 At+1 (A  A  B’)

• If a bit in B is set to 1, that same position in A gets

set to 0, otherwise it is unchanged
 Logic Microoperations
MASK OPERATION

• In a mask operation, the bit pattern in B is used to

clear certain bits in A

1100 At
1010 B
1000 At+1 (A  A  B)

• If a bit in B is set to 0, that same position in A gets

set to 0, otherwise it is unchanged
 Logic Microoperations
CLEAR OPERATION

• In a clear operation, if the bits in the same position

in A and B are the same, they are cleared in A,
otherwise they are set in A

1100 At
1010 B
0110 At+1 (A  A  B)
 Logic Microoperations
INSERT OPERATION

• An insert operation is used to introduce a specific bit pattern

into A register, leaving the other bit positions unchanged
• This is done as
- A mask operation to clear the desired bit positions,
followed by
- An OR operation to introduce the new bits into the
desired positions
- Example
• Suppose you wanted to introduce 1010 into the low order
four bits of A:
- 1101 1000 1011 0001 A (Original)
– 1101 1000 1011 1010 A (Desired)

• 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)
 Shift Microoperations
SHIFT MICROOPERATIONS

• There are three types of shifts

- Logical shift
- Circular shift
- Arithmetic shift
• What differentiates them is the information that goes
into the serial input

• A right shift operation

Serial
input

• A left shift operation Serial

input
 Shift Microoperations
LOGICAL SHIFT

• In a logical shift the serial input to the shift is a 0.

• A right logical shift operation:

• A left logical shift operation:

0

• In a Register Transfer Language, the following notation is used

- shl for a logical shift left
– shr for a logical shift right
– Examples:
• R2  shr R2
• R3  shl R3
 Shift Microoperations
CIRCULAR SHIFT

• In a circular shift the serial input is the bit that is shifted out of the
other end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used

- cil for a circular shift left
– cir for a circular shift right
– Examples:
• R2  cir R2
• R3  cil R3
 Shift Microoperations
ARITHMETIC SHIFT

• An arithmetic shift is meant for signed binary numbers (integers)

- An arithmetic left shift multiplies a signed number by two
- An arithmetic right shift divides a signed number by two
• The main distinction of an arithmetic shift is that it must keep the
sign of the number the same as it performs the division

• A right arithmetic shift operation:

sign
bit

• A left arithmetic shift operation:

0
sign
bit
 Shift Microoperations
ARITHMETIC SHIFT

• A left arithmetic shift operation must be checked for the

overflow
0
sign
bit

Before the shift, if the leftmost two

V bits differ, the shift will result in an
overflow

• In a RTL, the following notation is used

- ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
• R2  ashr R2
• R3  ashl R3
 Shift Microoperations

HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS

Serial Select 0 for shift right (down)

input (IR) 1 for shift left (up)

S
MUX H0
0
1
A0

A1 S
H1
0 MUX
A2 1

A3
S
H2
0 MUX
1

S
H3
0 MUX
1

Serial
input (IL)
 Shift Microoperations
ARITHMETIC LOGIC SHIFT UNIT

S3
S2 Ci
S1
S0

Arithmetic Di
Circuit
Select

0 4x1
C i+1 1 MUX Fi
2
3
Logic
Bi Ei
Ai
Circuit
shr
Ai-1
shl
i+1 A

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F=A+ 1 Increment A
0 0 0 1 0 F=A+ B Addition
0 0 0 1 1 F=A+ B + 1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’+ 1 Subtraction
0 0 1 1 0 F=A- 1 Decrement A
0 0 1 1 1 F=A TransferA
0 1 0 0 X F=A B AND
0 1 0 1 X F = A B OR
0 1 1 0 X F=A B XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift left A into F