UNIT 2

BASIC STRUCTURES OF COMPUTERS

Functional units
Q. What are the diff. functional units of basic computer system?
Computer: A computer is a combination of hardware and software resources which
integrate together and provides various functionalities to the user. Hardware are the physical
components of a computer like the processor, memory devices, monitor, keyboard etc. while
software is the set of programs or instructions that are required by the hardware resources to
function properly.
There are a few basic components that aids the working-cycle of a computer i.e. the Input-
Process- Output Cycle and these are called as the functional components of a computer. It
needs certain input, processes that input and produces the desired output. The input unit takes
the input, the central processing unit does the processing of data and the output unit produces
the output. The memory unit holds the data and instructions during the processing.
Digital Computer: A digital computer can be defined as a programmable machine which
reads the binary data passed as instructions, processes this binary data, and displays a
calculated digital output. Therefore, Digital computers are those that work on the digital data.

Details of Functional Components of a Digital Computer

 Input Unit :The input unit consists of input devices that are attached to the computer.
These devices take input and convert it into binary language that the computer
understands. Some of the common input devices are keyboard, mouse, joystick, scanner
etc.
 Central Processing Unit (CPU) : Once the information is entered into the computer by
the input device, the processor processes it. The CPU is called the brain of the computer
because it is the control center of the computer. It first fetches instructions from memory
and then interprets them so as to know what is to be done. If required, data is fetched from
memory or input device. Thereafter CPU executes or performs the required computation
and then either stores the output or displays on the output device. The CPU has three main
components which are responsible for different functions – Arithmetic Logic Unit (ALU),
Control Unit (CU) and Memory registers
 Arithmetic and Logic Unit (ALU) : The ALU, as its name suggests performs
mathematical calculations and takes logical decisions. Arithmetic calculations include
addition, subtraction, multiplication and division. Logical decisions involve comparison of
two data items to see which one is larger or smaller or equal.
 Control Unit : The Control unit coordinates and controls the data flow in and out of CPU
and also controls all the operations of ALU, memory registers and also input/output units.
It is also responsible for carrying out all the instructions stored in the program. It decodes
the fetched instruction, interprets it and sends control signals to input/output devices until
the required operation is done properly by ALU and memory.
 Memory Registers : A register is a temporary unit of memory in the CPU. These are used
to store the data which is directly used by the processor. Registers can be of different
sizes(16 bit, 32 bit, 64 bit and so on) and each register inside the CPU has a specific
function like storing data, storing an instruction, storing address of a location in memory
etc. The user registers can be used by an assembly language programmer for storing
operands, intermediate results etc. Accumulator (ACC) is the main register in the ALU and
contains one of the operands of an operation to be performed in the ALU.
 Memory : Memory attached to the CPU is used for storage of data and instructions and is
called internal memory The internal memory is divided into many storage locations, each
of which can store data or instructions. Each memory location is of the same size and has
an address. With the help of the address, the computer can read any memory location
easily without having to search the entire memory. when a program is executed, it’s data is
copied to the internal memory and is stored in the memory till the end of the execution.
The internal memory is also called the Primary memory or Main memory. This memory is
also called as RAM, i.e. Random Access Memory. The time of access of data is
independent of its location in memory, therefore this memory is also called Random
Access memory (RAM). Read this for different types of RAMs
 Output Unit : The output unit consists of output devices that are attached with the
computer. It converts the binary data coming from CPU to human understandable form.
The common output devices are monitor, printer, plotter etc.

Von-Neumann Model
Von-Neumann proposed his computer architecture design in 1945 which was later known as
Von-Neumann Architecture. It consisted of a Control Unit, Arithmetic, and Logical Memory
Unit (ALU), Registers and Inputs/Outputs.

Von Neumann architecture is based on the stored-program computer concept, where instruction
data and program data are stored in the same memory. This design is still used in most
computers produced today.

A Von Neumann-based computer:

 o Uses a single processor
o Uses one memory for both instructions and data.
o Executes programs following the fetch-decode-execute cycle

Components of Von-Neumann Model:

o Central Processing Unit

o Buses
o Memory Unit

Central Processing Unit

The part of the Computer that performs the bulk of data processing operations is called the
Central Processing Unit and is referred to as the CPU.

The Central Processing Unit can also be defined as an electric circuit responsible for executing
the instructions of a computer program.

The CPU performs a variety of functions dictated by the type of instructions that are
incorporated in the computer.

The major components of CPU are Arithmetic and Logic Unit (ALU), Control Unit (CU) and a
variety of registers.
Arithmetic and Logic Unit (ALU)

The Arithmetic and Logic Unit (ALU) performs the required micro-operations for executing the
instructions. In simple words, ALU allows arithmetic (add, subtract, etc.) and logic (AND, OR,
NOT, etc.) operations to be carried out.

Control Unit

The Control Unit of a computer system controls the operations of components like ALU,
memory and input/output devices.

The Control Unit consists of a program counter that contains the address of the instructions to be
fetched and an instruction register into which instructions are fetched from memory for
execution.

Registers

Registers refer to high-speed storage areas in the CPU. The data processed by the CPU are
fetched from the registers.

Following is the list of registers that plays a crucial role in data processing.

Registers Description

MAR (Memory Address This register holds the memory location of the data that
Register) needs to be accessed.

MDR (Memory Data This register holds the data that is being transferred to
Register) or from memory.

AC (Accumulator) This register holds the intermediate arithmetic and

logic results.

PC (Program Counter) This register contains the address of the next

instruction to be executed.

CIR (Current Instruction This register contains the current instruction during
Register) processing.

Buses

Buses are the means by which information is shared between the registers in a multiple-register
configuration system.

A bus structure consists of a set of common lines, one for each bit of a register, through which
binary information is transferred one at a time. Control signals determine which register is
selected by the bus during each particular register transfer.

Von-Neumann Architecture comprised of three major bus systems for data transfer.
Bus Description

Address Address Bus carries the address of data (but not the data) between the
Bus processor and the memory.

Data Bus Data Bus carries data between the processor, the memory unit and the
input/output devices.

Control Control Bus carries signals/commands from the CPU.

Bus

Memory Unit

A memory unit is a collection of storage cells together with associated circuits needed to transfer
information in and out of the storage. The memory stores binary information in groups of bits
called words. The internal structure of a memory unit is specified by the number of words it
contains and the number of bits in each word.

Two major types of memories are used in computer systems:

1. RAM (Random Access Memory)

2. ROM (Read-Only Memory)

Basic Operational Concepts

o The primary function of a computer system is to execute a program, sequence of
instructions. These instructions are stored in computer memory.
o These instructions are executed to process data which are already loaded in the computer
memory through some input devices.
o After processing the data, the result is either stored in the memory for further reference,
or it is sent to the outside world through some output port.
o To perform the execution of an instruction, in addition to the arithmetic logic unit, and
control unit, the processor contains a number of registers used for temporary storage of
data and some special function registers.
o The special function registers include program counters (PC), instruction registers (IR),
memory address registers (MAR) and memory and memory data registers (MDR).
o The Program counter is one of the most critical registers in CPU.
o The Program counter monitors the execution of instructions. It keeps track on which
instruction is being executed and what the next instruction will be.
 o The instruction register IR is used to hold the instruction that is currently being executed.
o The contents of IR are available to the control unit, which generate the timing signals
that control, the various processing elements involved in executing the instruction.
o The two registers MAR and MDR are used to handle the data transfer between the main
memory and the processor.
o The MAR holds the address of the main memory to or from which data is to be
transferred.
o The MDR contains the data to be written into or read from the addressed word of the
main memory.
o Whenever the processor is asked to communicate with devices, we say that the processor
is servicing the devices. The processor can service these devices in one of the two ways.
o One way is to use the polling routine, and the other way is to use an interrupt.
o Polling enables the processor software to check each of the input and output devices
frequently. During this check, the processor tests to see if any devices need servicing or
not.
o Interrupt method provides an external asynchronous input that informs the processor that
it should complete whatever instruction that is currently being executed and fetch a new
routine that will service the requesting device.

Bus Structures
Bus Organization
A bus organization is a group of conducting wires which carries information, all the peripherals are
connected to microprocessor through the bus. A system bus is nothing just a group of wires to carry
bits.

The MPU (Micro Processing Unit) performs primarily four operations:

 Memory Read: Read data (or instructions) from memory.

 Memory Write: Write data (or instructions) into memory.
 I/O Read: Accepts data from I/P devices.
 I/O Write: Sends data to O/P devices.

The diagram to represent the bus organization of 8085 microprocessor is given below:-

fig:- Bus organization of 8085 microprocessor

Types of Bus in the microprocessor are:-

 Address Bus
 Data Bus
 Control Bus

i. Address Bus:-

The address bus carries information about the location of data in the memory. The addresses bus is
unidirectional because of data flow in one direction, from the microprocessor to memory or from the
microprocessor to input/out devices. Length of Address bus of 8085 microprocessor is 16 bit (That
is, four hexadecimal digits), ranging from 0000H to FFFF H. The microprocessor 8085 can transfer
maximum 16-bit address which means it can address 65,536 different memory location i.e 64KB
memory.

Address Bus is used to perform the first function, identifying a peripheral or a memory location.

ii. Data Bus:-

The data bus allows data to travel between the microprocessor (CPU) and memory (RAM). The
data bus is bidirectional because of data flow in both directions, from the microprocessor to memory
or input/output devices and from memory or input/output devices to microprocessors. Length of
Databus of 8085 microprocessor is 8 bit (that is, two hexadecimal Digits0, ranging from 00H to FF
H.

The data bus is used to perform the second function, transferring binary information.

iii. Control Bus:-

The control bus carries the control signals to control all the associated peripherals, the
microprocessor uses control bus to process data, that is what to do with selected memory location
signals are:-

a. memory card
b.memory write
c. input/output,write.

Bus:

 A group of wires is known as bus Generally a bus consists of different types of wires like
Address bus, Data bus and Control bus
 All the internal and external part of computer system are connected through this bus
 The computer system communicates with this bus
 By using this bus, computer system reads the data from external memory or devices and
write the data to memory or devices.
Need of working bus:

 To form an operational system, parts must be connected in some organised way.

 To achieve a reasonable speed of operation, a computer must be organised so that all its
units can handle one full word of data as a gives time
 When a word of data is transferred between units, all its bits are transferred in parallel,
that is, the bits are transferred simultaneously over different wires.
 Many wires are required to establish the necessary connections.

Single BUS STRUCTURES:

The Bus structure and multiple bus structures are kinds of bus or computing. A bus is
fundamentally a subsystem which transfers data amongst the components of Computer
components either within a computer or between 2 computers. It connects peripheral devices
during this time.

- The multiple Bus Structure have multiple inter connected service integration buses and for a
particular bus the other buses are its foreign buses. A Single bus structure is uncomplicated and
consists of a single server.

-A bus can't span multiple cells. And each cell can have more than one bus.

- Published messages are printed on it. There is not any messaging engine on the Single bus
structure

i) In the single bus structure all the units are connected in the similar type of bus than connecting
different buses as multiple bus structure.

ii) Multiple bus structure's performance is better from the single bus structure.

iii) Single bus structure's price is less than multiple bus structure.

Computer software or can say only software is a common term used to explain the role that
computer programs, process and documentation play in a computer system.

Fig. single bus architecture

Single bus Organisation

  This bus is internal to the CPU and is different from the external bus or buses connecting
the CPU to the memory and I/O devices
 The external memory bus as shown in Fig. is connected to the CPU via a memory data
register MDR and the memory address register MAR
 The number and function of registers R., through R(n-1) vary considerably from one
machine to another.
 They may be used by the programmer as general-purpose registers or some of them may
be used as special-purpose registers, such as index registers or stack pointers.
 Three registers YZ and TEMP are introduced for the first time. These registers are not
available to the programmer, because they are never referenced directly by any
instruction. They are used by CPU for temporary storage during execution of some
instructions.

Advantages of bus structure:

 Versatility :New devices can be added easily, Peripherals can be moved between
computer systems that use the same bus standard.
 Low cost, due to single set of wires is shared in multiple ways.
 Manage complexity by partitioning the design.

Disadvantages of bus structure

 It creates a communication bottleneck, so the bandwidth of that bus can limit the
maximum I/O throughput.
 The maximum bus speed is largely limited by the length of the bus, the number of
devices on the bus, and the need to support a range of devices with Widely varying
latencies and data transfer rates.
Two bus Organisation
 The sequence of operations to add the contents of register R1 to that
of register R, and store the result in register R, are as follows:

 Step Action

(1) RY

(2) R Add. Zin

(3) Zout R

 The signals whose names are given in any step are activated, or set to 1, for
the duration of the clock cycle corresponding to that step. All other signals
are inactive
 Thus, in step 1, the output of register R, and the input of register Y are
enabled, causing the contents of R, to be transferred to Y.

 In step 2. the contents of register R2 are gated onto the bus and hence to
input B of the ALU. The contents of register Y are always available at input
A. The function performed by ALU depends on the signals applied to the
ALU control lines.

 In this case, the Add line is set to 1, causing the output of the ALU to be the
sum of the two numbers at inputs A and B. This sum is loaded into register
Z., because its input is enabled (Zn). In last step. the contents of register Z
are transferred to the destination register R,

 Advantage of two bus structure :

 Each device has its own bus so transfer of data is faster.

 Disadvantage of two bus structure:

 It is costly as compared to single bus structure.

Three Bus Organiation

Three bus structure :

Consider a three-operand instruction of the form OP Rsrel, Rsrc2, Rdst

in which an operation is performed on the contents of two source registers,

and the result is placed into a destination register. Buses Aand B are used to
transfer the source operands, and bus C provides the path to the destination.

The path from the source buses to the destination bus goes through the
ALU, where the required operation is performed.

Thus, assuming that the operation to be performed can be completed

in one pass through the ALU, the structure of fig. allows the execution
phase of an instruction to be performed in one clock cycle. Note that if it is
 merely necessary to copy the contents of one register into another, then the
transfer is also done through the ALU, but no arithmetic or logic operation
is performed.The temporary storage registers Y and Z in figure are not
required Register Y is not needed because both inputs to the ALU are
provided simultaneously via buses A and B.

Register Z is not needed because the output from the ALU is transferred to
the destination register via the third bus, C. In this structure, it is essential to
ensure that the same register can serve as both the source and the destination
in a given instruction.
In computer architecture, there are following types of addressing modes-

1. Implied Addressing Mode-

In this addressing mode,


The definition of the instruction itself specify the operands implicitly.
 It is also called as implicit addressing mode.

Examples-

 The instruction “Complement Accumulator” is an implied mode instruction.

 In a stack organized computer, Zero Address Instructions are implied mode instructions.
 (since operands are always implied to be present on the top of the stack)

2. Stack Addressing Mode-

In this addressing mode,

 The operand is contained at the top of the stack.

Example-

ADD
 This instruction simply pops out two symbols contained at the top of the stack.
 The addition of those two operands is performed.
 The result so obtained after addition is pushed again at the top of the stack.

3. Immediate Addressing Mode-

In this addressing mode,

 The operand is specified in the instruction explicitly.
 Instead of address field, an operand field is present that contains the operand.

Examples-

 ADD 10 will increment the value stored in the accumulator by 10.

 MOV R #20 initializes register R to a constant value 20.

4. Direct Addressing Mode-

In this addressing mode,

 The address field of the instruction contains the effective address of the operand.
 Only one reference to memory is required to fetch the operand.
 It is also called as absolute addressing mode.

Example-
 ADD X will increment the value stored in the accumulator by the value stored at memory
location X.

AC ← AC + [X]

5. Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction specifies the address of memory location that
contains the effective address of the operand.
 Two references to memory are required to fetch the operand.

Example-

 ADD X will increment the value stored in the accumulator by the value stored at memory
location specified by X.
AC ← AC + [[X]]

6. Register Direct Addressing Mode-

In this addressing mode,

 The operand is contained in a register set.
 The address field of the instruction refers to a CPU register that contains the operand.
 No reference to memory is required to fetch the operand.

Example-

 ADD R will increment the value stored in the accumulator by the content of register R.
AC ← AC + [R]

NOTE-

It is interesting to note-
 This addressing mode is similar to direct addressing mode.
 The only difference is address field of the instruction refers to a CPU register instead of
main memory.
7. Register Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction refers to a CPU register that contains the effective
address of the operand.
 Only one reference to memory is required to fetch the operand.
Example-

 ADD R will increment the value stored in the accumulator by the content of memory
location specified in register R.
AC ← AC + [[R]]

NOTE-

It is interesting to note-
 This addressing mode is similar to indirect addressing mode.
 The only difference is address field of the instruction refers to a CPU register.

8. Relative Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of program counter
with the address part of the instruction.

Effective Address
= Content of Program Counter + Address part of the instruction

NOTE-
 Program counter (PC) always contains the address of the next instruction to be
executed.

 After fetching the address of the instruction, the value of program counter immediately
increases.
 The value increases irrespective of whether the fetched instruction has completely
executed or not.

9. Indexed Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of index register with
the address part of the instruction.

Effective Address
= Content of Index Register + Address part of the instruction

10. Base Register Addressing Mode-

In this addressing mode,
 Effective address of the operand is obtained by adding the content of base register with
the address part of the instruction.

Effective Address
= Content of Base Register + Address part of the instruction

11. Auto-Increment Addressing Mode-

 This addressing mode is a special case of Register Indirect Addressing Mode where-
 Effective Address of the Operand
= Content of Register

In this addressing mode,

 After accessing the operand, the content of the register is automatically incremented by
step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 Only one reference to memory is required to fetch the operand.
Example-
Assume operand size = 2 bytes.
here,
 After fetching the operand 6B, the instruction register RAUTO will be automatically
incremented by 2.
 Then, updated value of RAUTO will be 3300 + 2 = 3302.
 At memory address 3302, the next operand will be found.

NOTE-

In auto-increment addressing mode,

 First, the operand value is fetched.
 Then, the instruction register RAUTO value is incremented by step size ‘d’.

12. Auto-Decrement Addressing Mode-

 This addressing mode is again a special case of Register Indirect Addressing Mode
where-

Effective Address of the Operand

= Content of Register – Step Size

In this addressing mode,

 First, the content of the register is decremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 After decrementing, the operand is read.
 Only one reference to memory is required to fetch the operand.

Example-
Assume operand size = 2 bytes.
Here,
 First, the instruction register RAUTO will be decremented by 2.
 Then, updated value of RAUTO will be 3302 – 2 = 3300.
 At memory address 3300, the operand will be found.

NOTE-

In auto-decrement addressing mode,

 First, the instruction register RAUTO value is decremented by step size ‘d’.
 Then, the operand value is fetched.

Also Read- Practice Problems On Addressing Modes

Applications of Addressing Modes-

Addressing Modes Applications

Immediate Addressing Mode  To initialize registers to a constant value

Direct Addressing Mode

and  To access static data
 To implement variables
Register Direct Addressing Mode

 To implement pointers because pointers are

Indirect Addressing Mode memory locations that store the address of
and another variable
 To pass array as a parameter because
Register Indirect Addressing Mode
array name is the base address and pointer
is needed to point the address

Relative Addressing Mode  For program relocation at run time i.e. for
 position independent code
 To change the normal sequence of
execution of instructions
 For branch type instructions since it directly
updates the program counter

 For array implementation or array

Index Addressing Mode addressing
 For records implementation

 For writing relocatable code i.e. for

relocation of program in memory even at
Base Register Addressing Mode run time
 For handling recursive procedures

Auto-increment Addressing Mode

 For implementing loops
and
 For stepping through arrays in a loop
Auto-decrement Addressing Mode  For implementing a stack as push and pop

What is a Subroutine?

A set of instructions that are used repeatedly in a program can be referred to as a Subroutine.
Only one copy of this Instruction is stored in the memory. When a Subroutine is required it
can be called many times during the Execution of a particular program. A call Subroutine
Instruction calls the Subroutine. Care Should be taken while returning a Subroutine as a
Subroutine can be called from a different place from the memory.
The content of the PC must be Saved by the call Subroutine Instruction to make a correct
return to the calling program.

Process of a subroutine in a program

The subroutine linkage method is a way in which computers call and return the Subroutine.
The simplest way of Subroutine linkage is saving the return address in a specific location, such
as a register which can be called a link register called Subroutine.

Advantages of Subroutines

 Code reuse: Subroutines can be reused in multiple parts of a program, which can save
time and reduce the amount of code that needs to be written.
 Modularity: Subroutines help to break complex programs into smaller, more manageable
parts, making them easier to understand, maintain, and modify.
 Encapsulation: Subroutines provide a way to encapsulate functionality, hiding the
implementation details from other parts of the program.

Disadvantages of Subroutines

 Overhead: Calling a subroutine can incur some overhead, such as the time and memory
required to push and pop data on the stack.
 Complexity: Subroutine nesting can make programs more complex and difficult to
understand, particularly if the nesting is deep or the control flow is complicated.
 Side Effects: Subroutines can have unintended side effects, such as modifying global
variables or changing the state of the program, which can make debugging and testing
more difficult.
What is Subroutine Nesting?

Subroutine nesting is a common Programming practice In which one Subroutine calls another
Subroutine.

A Subroutine calling another subroutine

From the above figure, assume that when Subroutine 1 calls Subroutine 2 the return address of
Subroutine 2 should be saved somewhere. So if the link register stores the return address of
Subroutine 1 this will be (destroyed/overwritten) by the return address of Subroutine 2. As the
last Subroutine called is the first one to be returned ( Last in first out format). So stack data
structure is the most efficient way to store the return addresses of the Subroutines .

The Return address of the subroutine is stored in stack memory

What is Stack Memory?

A Stack is a basic data structure that can be implemented anywhere in the memory. It can be
used to store variables that may be required afterwards in the program Execution. In a stack,
the first data put will be the last to get out of a stack. So the last data added will be the first
one to come out of the stack (last in first out).

Stack memory having data A, B & C

So from the diagram above first, A is added then B & C. While removing the first C is
Removed then B & A.

Advantages of subroutine nesting and Stack Memory

 Flexibility: Subroutine nesting allows for the creation of complex programs with many
levels of abstraction, making it easier to organize code and reuse functionality.
 Efficient use of memory: Stack memory is used to allocate and deallocate local variables,
allowing for efficient use of memory resources.
 Error handling: Stack Memory can be used to keep track of the state of the program,
allowing for recovery from errors and exceptions.

Disadvantages of Subroutine Nesting and Stack Memory

 Stack overflow: If too many subroutine calls are nested or if the local variables are too
large, the stack memory can overflow, causing the program to crash.
 Security vulnerabilities: Stack-based buffer overflows can be exploited by attackers to
execute malicious code or crash the program.
 Performance: The use of stack memory can impact program performance, particularly if
the program requires a large amount of memory or if the stack needs to be frequently
accessed.
Parameter passing
What are the Different Types of Filed in Instruction?
A computer performs a task based on the instruction provided. Instruction in computers
comprises groups called fields. These fields contain different information for
computers everything is in 0 and 1 so each field has different significance based on
which a CPU decides what to perform. The most common fields are:
 The operation field specifies the operation to be performed like addition.
 Address field which contains the location of the operand, i.e., register or memory
location.
 Mode field which specifies how operand is to be founded.
Instruction is of variable length depending upon the number of addresses it contains.
Generally, CPU organization is of three types based on the number of address fields:
 Single Accumulator organization
 General register organization
 Stack organization
In the first organization, the operation is done involving a special register called the
accumulator. In the second multiple registers are used for the computation purpose. In
the third organization the work on stack basis operation due to which it does not
contain any address field. Only a single organization doesn’t need to be applied, a
blend of various organizations is mostly what we see generally.
Types of Instructions
Based on the number of addresses, instructions are classified as:
NOTE: We will use the X = (A+B)*(C+D) expression to showcase the procedure.

Zero Address Instructions

These instructions do not specify any operands or addresses. Instead, they operate on
data stored in registers or memory locations implicitly defined by the instruction. For
example, a zero-address instruction might simply add the contents of two registers
together without specifying the register names.

Zero Address Instruction

A stack-based computer does not use the address field in the instruction. To evaluate an
expression first it is converted to reverse Polish Notation i.e. Postfix Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

One Address Instructions

These instructions specify one operand or address, which typically refers to a memory location
or register. The instruction operates on the contents of that operand, and the result may be
stored in the same or a different location. For example, a one-address instruction might load
the contents of a memory location into a register.
This uses an implied ACCUMULATOR register for data manipulation. One operand is in the
accumulator and the other is in the register or memory location. Implied means that the CPU
already knows that one operand is in the accumulator so there is no need to specify it.

One Address Instruction

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC
LOAD A AC = M[A]

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

Two Address Instructions

These instructions specify two operands or addresses, which may be memory locations or
registers. The instruction operates on the contents of both operands, and the result may be
stored in the same or a different location. For example, a two-address instruction might add
the contents of two registers together and store the result in one of the registers.
This is common in commercial computers. Here two addresses can be specified in the
instruction. Unlike earlier in one address instruction, the result was stored in the accumulator,
here the result can be stored at different locations rather than just accumulators, but require
more number of bit to represent the address.

Two Address Instruction

Here destination address can also contain an operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = M[C]

ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1
Three Address Instructions
These instructions specify three operands or addresses, which may be memory locations or
registers. The instruction operates on the contents of all three operands, and the result may be
stored in the same or a different location. For example, a three-address instruction might
multiply the contents of two registers together and add the contents of a third register, storing
the result in a fourth register.
This has three address fields to specify a register or a memory location. Programs created are
much short in size but number of bits per instruction increases. These instructions make the
creation of the program much easier but it does not mean that program will run much faster
because now instructions only contain more information but each micro-operation (changing
the content of the register, loading address in the address bus etc.) will be performed in one
cycle only.

Three Address Instruction

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

Advantages of Zero-Address, One-Address, Two-

Address and Three-Address Instructions
Zero-address instructions
 They are simple and can be executed quickly since they do not require any operand
fetching or addressing. They also take up less memory space.
One-address instructions
 They allow for a wide range of addressing modes, making them more flexible than
zero-address instructions. They also require less memory space than two or three-
address instructions.
Two-address instructions
 They allow for more complex operations and can be more efficient than one-address
instructions since they allow for two operands to be processed in a single
instruction. They also allow for a wide range of addressing modes.
Three-address instructions
 They allow for even more complex operations and can be more efficient than two-
address instructions since they allow for three operands to be processed in a single
instruction. They also allow for a wide range of addressing modes.
Disadvantages of Zero-Address, One-Address, Two-
Address and Three-Address Instructions
Zero-address instructions
 They can be limited in their functionality and do not allow for much flexibility in
terms of addressing modes or operand types.
One-address instructions
 They can be slower to execute since they require operand fetching and addressing.
Two-address instructions
 They require more memory space than one-address instructions and can be slower
to execute since they require operand fetching and addressing.
Three-address instructions
 They require even more memory space than two-address instructions and can be
slower to execute since they require operand fetching and addressing.
Overall, the choice of instruction format depends on the specific requirements of
the computer architecture and the trade-offs between code size, execution time,
and flexibility.

UNIT 3:_BASIC PROCESSING UNIT

Execution of a Complete Instructions:

» Computer Organization and Architecture - Execution of a Complete

Instructions

. Fetch information from memory to CPU

■ Store information to CPU register to memory

Transfer of data between CPU registers.

. Perform arithmetic or logic operation and store the result in CPU registers.

To execute a complete instruction we need to take help of these basic

operations and we need to execute these operation in some particular order.
As for example, consider the instruction: "Add contents of memory location
NUM to the contents of register R1 and store the result in register R1." For
simplicity, assume that the address NUM is given explicitly in the address
field of the instruction That is, in this instruction, direct addressing mode is
used
1. Fetch instruction

2. Fetch first operand (Contents of memory location pointed at by the

address field of the instruction)

3. Perform addition
4. Load the result into R1,

Following sequence of control steps are required to implement the above

operation for the single-bus architecture that we have discussed in earlier
section

instruction execution proceeds as follows

In Step1:

The instruction fetch operation is initiated by loading the contents of the PC

into the MAR and sending a read request to memory.
To perform this task first of all the contents of PC have to be brought to
internal bus and then it is loaded to MAR. To perform this task control
circuit has to generate the PC Signal and MAR signal

After issuing the read signal, CPU has to wait for some time to get the MFC
signal During that time PC is updated by 1 through the use of the ALU. This
is accomplished by setting one of the inputs to the ALU (Register Y) to 0
and the other input is available in bus which is current value of PC

At the same time, the carry-in to the ALU is set to 1 and an add operation is
specified
In Step 2:
The updated value is moved from register Z back into the PC. Step 2 is
initiated immediately after issuing the memory Read request without
waiting for completion of memory function. This is possible because step 2
does not use the memory bus and its execution does not depend on the
memory read operation
In Step 3:

Step3 has been delayed until the MFC is received. Once MFC is received,
the word fetched from the memory is transferred to IR (Instruction
Register), Because it is an instruction. Step 1 through 3 constitute the
instruction fetch phase of the control sequence.
The instruction fetch portion is same for all instructions. Next step inwards,
instruction execution phase takes place

As soon as the IR is loaded with instruction, the instruction decoding

circuits interprets its contents. This enables the control circuitry to choose
the appropriate signals for the remainder of the control sequence, step 4 to
8, which we referred to as the execution phase. To design the control
sequence of execution phase, it is needed to have the knowledge of the
internal structure and instruction format of the PU. Secondly, the length of
instruction phase is different for different instruction.

In this example, we have assumed the following instruction format

Sequencing of control signals
What is Hardwired Control Unit?

A hardwired control is a mechanism of producing control signals using Finite State

Machines (FSM) appropriately. It is designed as a sequential logic circuit. The final
circuit is constructed by physically connecting the components such as gates, flip flops,
and drums. Hence, it is named a hardwired controller.

The figure shows a 2-bit sequence counter, which is used to develop control signals. The
output obtained from these signals is decoded to generate the required signals in
sequential order.

The hardwired control consists of a combinational circuit that outputs desired controls
for decoding and encoding functions. The instruction that is loaded in the IR is decoded
by the instruction decoder. If the IR is an 8-bit register, then the instruction decoder
generates 28 (256) lines.

Inputs to the encoder are given from the instruction step decoder, external inputs, and
condition codes. All these inputs are used and individual control signals are generated.
The end signal is generated after all the instructions get executed. Furthermore, it results
in the resetting of the control step counter, making it ready to generate the control step
for the next instruction.

The major goal of implementing the hardwired control is to minimize the cost of the
circuit and to achieve greater efficiency in the operation speed. Some of the methods that
have come up for designing the hardwired control logic are as follows −

Sequence Counter Method − This is the most convenient method employed to design the
controller of moderate complexity.
Delay Element Method − This method is dependent on the use of clocked delay elements
for generating the sequence of control signals.
State Table Method − This method involves the traditional algorithmic approach to
design the Notes controller using the classical state table method.
 Fig. hardwired control unit
What is Microprogrammed Control Unit?

Computer ArchitectureComputer ScienceNetwork

A control unit whose binary control values are saved as words in memory is called a
microprogrammed control unit.

A controller results in the instructions to be implemented by constructing a definite

collection of signals at each system clock beat. Each of these output signals generates
one micro-operation including register transfer. Thus, the sets of control signals are
generated definite micro-operations that can be saved in the memory.

Each bit that forms the microinstruction is linked to one control signal. When the bit is
set, the control signal is active. When it is cleared the control signal turns inactive. These
microinstructions in a sequence can be saved in the internal ’control’ memory. The
control unit of a microprogram-controlled computer is a computer inside a computer.

The following image shows the block diagram of a Microprogrammed Control

organization.

There are the following steps followed by the microprogrammed control are −

It can execute any instruction. The CPU should divide it down into a set of sequential
operations. This set of operations are called microinstruction. The sequential micro-
operations need the control signals to execute.
 Control signals saved in the ROM are created to execute the instructions on the data
direction. These control signals can control the micro-operations concerned with a
microinstruction that is to be performed at any time step.
The address of the microinstruction is executed next is generated.
The previous 2 steps are copied until all the microinstructions associated with the
instruction in the set are executed.
The address that is supported to the control ROM originates from the micro counter
register. The micro counter received its inputs from a multiplexer that chooses the output
of an address ROM, a current address incrementer, and an address that is saved in the
next address field of the current microinstruction.

Advantages of Microprogrammed Control Unit

There are the following advantages of microprogrammed control are as follows −

It can more systematic design of the control unit.

It is simpler to debug and change.
It can retain the underlying structure of the control function.
It can make the design of the control unit much simpler. Hence, it is inexpensive and less
error-prone.
It can orderly and systematic design process.
It is used to control functions implemented in software and not hardware.
It is more flexible.
It is used to complex function is carried out easily.
Disadvantages of Microprogrammed Control Unit
There are the following disadvantages of microprogrammed control are as follows −
Adaptability is obtained at more cost.
It is slower than a hardwired control unit

In order not to complicate the microprogramming example, only four

instructions are considered. Table 8.1 lists 4 of the16 possible
memory reference instructions.

Table 8.1
 Symbol Opcode Symbolic Description Meaning
Add the content of the
AC AC + M [EA] operand found in the effective
ADD 0000 address (EA) to the content of
AC. The result in AC.
If ( AC < 0) then (PC EA) Branch to the (EA) if the
BRANCH 0001
operand in AC is negative.
Store the content of AC
STORE 0010 M (EA) AC into the memory word
specified by the (EA).
Exchange the data between
EXCHANGE 0011 AC M [EA], M [EA] AC AC and the memory word
specified by the (EA)

Microinstruction Format
Figure 8.5 shows the microinstruction format for the
control memory.

Figure 8.5

The 20 bits of the microinstruction are divided into four main

functional parts as follows:
1. The Microoperation Fields (F1, F2, and
F3)
The Microoperation field is subdivided into three subfields (F1, F2,
and F3) of three bits each. The three bits in each field are encoded
to specify seven distinct microoperations plus one idle
microoperation (i.e. no operation) as listed in Table 8.2. This gives a
total of 21 microoperations. Therefore; No more than three
microoperations can be chosen for a microinstruction, one from each
field.
If for example; fewer than three microoperations are needed for a
given microinstruction, one or more of the fields will use the binary
code 000 (i.e. no operation).

Table 8.2

Microoperation fields
Microoperation Symbol
F1 F2 F3
000 None NOP
001 AC ← AC + DR ADD
010 AC ← 0 CLRAC
011 AC ← AC + 1 INCAC
100 AC ← DR DRTAC
101 AR ← DR(0-10) DRTAR
110 AR ← PC PCTAR
111 M [AR] ← DR WRITE
♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦ ♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦ ♦♦♦♦♦♦♦
000 None NOP
001 AC ← AC - DR SUB
010 AC ← AC ν DR OR
011 AC ← AC ∩ DR AND
100 DR ← M [AR] READ
101 DR ← AC ACTDR
110 DR ← DR + 1 INCDR
111 DR (0-10) ← PC PCTDR
♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦ ♦♦♦♦♦♦♦♦♦♦♦♦♦♦♦ ♦♦♦♦♦♦♦
000 None NOP
001 AC ← AC DR XOR
010 AC ← AC COM
011 AC ← shl AC SHL
100 AC ← shr AC SHR
101 PC ← PC + 1 INCPC
110 PC ← AR ARTPC
111 Rserved
 Example

Suppose that a given microinstruction specify two simultaneous

microoperations from F2 and F3 and none from Fl.

DR ← M [AR] with F2 = 100

And PC ← PC + 1 with F3 = 101

The nine bits of the Microoperation fields will then be 000 100 101.

All transfer-type microoperations symbols use five

letters:
a. The first two letters designate the source register.
b. The third letter is always a T.
c. The last two letters designate the destination register.

Example
a. The microoperation that specifies the transfer PC ← AR has
the symbol ARTPC, which stands for a transfer from AR to PC.

b. The microoperation that specifies the transfer DR ← AC has

the symbol ACTDR, which stands for a transfer from AC to DR.

2. The Condition for Branching Field (CD)

This microinstruction field selects status bit conditions. It consists of
two bits which are encoded to specify four status bit conditions as
listed in Table 8.3.

Table 8.3

CD Condition Symbol Comments

00 Always = 1 U Unconditional Branch
01 DR(15) I Indirect Address Bit
10 AC(15) S Sign Bit of AC
 11 AC = 0 Z Zero value in AC

Notes

a. The first condition is always a 1, so that a reference to CD =

00 will always find the condition to be true. When this condition is
used in conjunction with the BR (branch) field, it provides an
unconditional branch operation.
b. The symbols U, I, S, and Z will be used for the four status bits for
writing microprograms in symbolic form.
3. The Branch Field (BR)
The BR field which consists of two bits specifies the type of branch
to be used (see table 8.4). This field is used in conjunction with the
address field AD to choose the address of the next
microinstruction.

Table 8.4

BR Symbol Function
00 JMP CAR ← AD if condition = 1
CAR ← CAR + 1 if condition = 0
01 CALL CAR ← AD, SBR ← CAR + 1 if condition = 1
CAR ← CAR + 1 if condition = 0
10 RET CAR ← SBR (Return from subroutine)
11 MAP CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0

Table 8.4 shows: -

a. When BR = 00, the control performs a jump (JUMP) operation.

Depending on the value of the CD field. When the status bit
condition specified in the CD field is equal to 1, the next address
in the AD field is transferred to the control address register CAR.
Otherwise, CAR is incremented.

b. When BR = 01, it performs a call to subroutine (CALL)

operation. Depending on the value of the CD field. When the
status bit condition specified in the CD field is equal to 1, the next
address in the AD field is transferred to the control address
register CAR. Otherwise, CAR is incremented.

Note.
The JUMP & CALL operations are identical
except that a CALL microoperation stores the
return address in the subroutine register SBR.

c. When BR = 10, the return from subroutine is accomplished. This

causes the transfer of the return address from SBR to CAR.
 d. When BR = 11, the mapping from the operation code bits of the
instruction to an address for CAR is accomplished. This mapping
is as depicted in figure 8.3. The bits of the operation code are in
DR (11-14) after an instruction is read from memory.

Note.
It is clear from the table 8.4 that the last two conditions in
the BR field are independent of the values in the CD and
AD fields.

4. The Address Field (AD)

The AD field contains a branch address. The address field is seven
bits wide, since the control memory has 128 = 27 words.

Symbolic Microinstructions
The symbols defined in tables 8.2, 8.3, and 8.4 could be used to
specify microinstructions in symbolic form.

The simplest way to formulate an assembly language for a

microprogram is to define symbols for each field of the
microinstruction and to give users the capability for defining their own
symbolic address.

Each symbolic microinstruction is divided into five fields:

1. The Label Field
This field may be left empty or it may specify a symbolic address.
A label is terminated with a colon (:).

2. The Microoperations Field (F1, F2, and F3)

This field consists of one, two, or three symbols, separated by
commas, from those defined in table 8.2. There may be no more
than one symbol from each field.
The NOP symbol is used when the microinstruction has no
microoperations, this will be translated by the assembler to nine
zero's.
3. The Condition Field (CD)
This field has one of the letters U, I, S, or Z.

4. The Branch Field (BR)

This field contains one of the four symbols defined in Table 8.4(i.e.
JMP, CALL, RET, and MAP).

5. The Address Field (AD)

This field specifies a value for the address field of the
microinstruction in one of three possible ways: -

a. With a symbolic address, this must also appear as a label.

b. With the symbol NEXT to designate the next address in

sequence.

c. When the BR field contains a RET or MAP symbol, the AD

field is left empty and is converted to seven zero's by the
assembler.

Note.
The pseudoinstruction ORG is used to define the origin, or
first address, of a microprogram routine. Thus the symbol
ORG 37 informs the assembler to place the next
microinstruction in control memory at decimal address 37,
which is equivalent to the binary address 0100101.
The Fetch Routine
As it was mentioned before, the control memory has 128 words, of
20 bits each.
The first 64 words (addresses 0 to 63) are to be occupied by the
routines for the 16 instructions. The last 64 words may be used for any
other purpose.

The fetch routine needs three microinstructions, which are placed in the
control memory at addresses 64, 65, and 66.

The following register transfer representation of the

fetch routine shows the internal register transfer
operations that each microinstruction implements.

AR← PC

DR ← M [AR], PC ← PC + 1
AR ← DR (0-10), CAR (2-5) ← DR (11-14), CAR (0, 1, 6) ← 0

From the fetch routine above it is clear that:

1. The first microinstruction (located at address 64) transfers the
address of the instruction from PC to AR.

2. The second microinstruction (located at address 65) read the

instruction from the memory and transferred to register DR with
incrimination of the program counter PC. Since no instruction register is
available, the instruction code remains in DR.

3. The third microinstruction (located at address 66) transfer the

address part to the address register AR and then control is transferred
to one of 16 routines by mapping the operation code part of the
instruction from DR into CAR (see figure 8.3).
Using the assembly language conventions defined previously, the
symbolic representation of the fetch routine will be as follows:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
 Using tables 8.2, 8.3, and 8.4, the translation of the symbolic microprogram to
binary produces the following binary microprogram fetch routine.

Binary Address of the Binary Representation of the

Microinstruction in the Microinstruction Word in the
Control Memory Control Memory

F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000

Symbolic Microprogram
Return back to the fetch routine, the execution of the third (MAP)
microinstruction in the fetch routine results in a branch to address
0xxxx00, where xxxx represents the four bits of the operation code.

Example
Suppose that the instruction is STORE instruction whose operation
code is 0010. The MAP microinstruction will transfer to CAR the
address 0 0010 00 (decimal 8), which is the start address for the STORE
routine in control memory.

The first address for the ADD, BRANCH and EXCHANGE routines are 0
0000 00 (decimal 0), 0 0001 00 (decimal 4), and 0 0011 00 (decimal 12)
respectively. The first address for the other 12 routines are at address values
16, 20, 24, ... , 60. This gives four words in control memory for each routine.

In each routine we must provide microinstructions for:

1. Evaluating the effective address.
2. Executing the instruction.
The indirect address mode is associated with all memory-
reference instructions. For purpose of saving in the number of control
memory words, the microinstructions for the indirect address are stored
as a subroutine. This subroutine, symbolized by INDRCT, is located right
after the fetch routine in the control memory.
Table 8.5 shows the symbolic microprogram of the microinstruction routines
that execute the four computer instructions (ADD, BRANCH, STORE, and
EXCHANGE) and the INDRCT and fetch routines.

Table 8.5

Label Microoperations CD BR AD
Symbolic Microprograms
for Computer Instructions
ADD, BRANCH, STORE, EXCHANGE
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH
ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH
ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH
ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH
Symbolic Microprograms
For Subroutines
FETCH & INDRCT
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET
How the transfer and return from the indirect subroutine occurs

Assume that the MAP microinstruction at the end of the fetch routine
caused a branch to address 0, where the ADD routine is stored. The first
microinstruction in the ADD routine calls subroutine INDRCT,
conditioned on status bit I. If I = 1, a branch to INDRCT occurs and the
return address (address 1 in this case) is stored in the subroutine register
SBR.

Remember that an indirect address considers the address part of the

instruction as the address where the effective address is stored rather
than the address of the operand. Therefore, the memory has to be
accessed to get the effective address, which is then transferred to AR.
The return from subroutine (RET) transfers the address from SBR to
CAR, thus returning to the second microinstruction of the ADD routine.

1. The Execution of the ADD Instruction

The execution of the ADD instruction is carried out by the
microinstructions at addresses 1 and 2. The first microinstruction
reads the operand from memory into DR. The second
microinstruction performs an add microoperation with the content of
DR and AC and then jumps back to the beginning of the fetch routine.

2. The Execution of the BRANCH Instruction

The BRANCH instruction should cause a branch to the effective
address if AC < 0. The AC will be less than zero if its sign is negative,
which is detected from status bit S being a 1.
The BRANCH routine in Table 8.5 starts by checking the value of S. If S
is equal to 0, no branch occurs and the next microinstruction causes a
jump back to the fetch routine without altering the content of PC. If S
is equal to 1, the first JMP microinstruction transfers control to
location OVER. The microinstruction at this location calls the
INDRCT subroutine if I = 1. The effective address is then transferred
from AR to PC and the microprogram jumps back to the fetchroutine.

3. The Execution of the STORE Instruction

The STORE routine again uses the INDRCT subroutine if I = 1. The
content of AC is transferred into DR. A memory write operation is
initiated to store the content of DR in a location specified by the
effective address in AR.