DSDV Lab Manual 2023-24
EXPERIMENT-12COUNTERS
(A) ASYNCHRONOUS COUNTER
AIM -To design and test 3-bit binary asynchronous counter using flip-flop IC 7476 for the
Given sequence
COMPONENTS REQUIRED: - IC 7476, Patch Cords & IC Trainer Kit
THEORY: A sequential circuit that gives through a prescribed sequence of states upon the
application of input pluses is called counters. The straight binary sequence counter is the simple
and most straight forward. An n-bit binary counter has n flip-flops and can count in binary from 0
to 2n -1. A counter in which each flip-flop is triggered by the output goes to previous flip-flop.
As all the flip-flops do not change state simultaneously spike occur at the output. To avoid this,
strobe pulse is required. Because of the propagation delay the operating speed of asynchronous
counter is low. Asynchronous counter are easy and simple to construct
ASYNCRONOUS COUNTERS A binary ripple (Asynchronous) counter consists of series
connections of T- flip-flops without any logic gates. Each FF is triggered by the output of its
preceding FF goes from 1 to 0.
Realization of 3-bit binary counters using IC7476
PIN DIAGRAM
Asynchronous UP Counter (MOD-8)
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DSDV Lab Manual 2023-24
TRUTH TABLE
Number of Flip Flop outputs
clock pulses Qc Qb Qa
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
Asynchronous DOWN Counter (MOD-8)
TRUTH TABLE
Number of Flip Flop outputs
clock pulses Qc Qb Qa
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1
Department of ETE, DSCE
DSDV Lab Manual 2023-24
Possible Viva Questions
1. What is an asynchronous counter?
2. How is it different from a synchronous counter?
3. Realize asynchronous counter using T flip flop.
Applications:
Frequency dividers , Delay units, Timers, Real time counters
Remarks :
Signature of Staff Incharge with date:
Department of ETE, DSCE
DSDV Lab Manual 2023-24
(B) SYNCHRONOUS COUNTER
AIM: To design and test 3-bit binary synchronous counter using flip-flop IC 7476 for the
Given sequence
UP COUNTER
Design and Realization of 3 Bit Synchronous Counter Using IC7476
Excitation table
Present Next
state State J K
output output
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
MOD-6 Synchronous UP COUNTER
In MOD-6 counter invalid state is 110
PRESENT STATE NEXT STATE EXCITATION
Qc Qc JC KC JB KB JA KA
Qb Qa Qb Qa
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0 X X 1
Department of ETE, DSCE
DSDV Lab Manual 2023-24
Circuit Diagram
Department of ETE, DSCE
DSDV Lab Manual 2023-24
Synchronous Down Counter
PRESENT STATE NEXT STATE FLIP-FLOPS
Qc Qb Qa Qc Qb Qa Jc Kc Jb Kb Ja Ka
1 0 0 0 1 1 X 1 1 X 1 X
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 0 0 0 0 X 0 X X 1
0 0 0 1 0 0 1 X 0 X 0 X
Simplifications
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DSDV Lab Manual 2023-24
Circuit Diagram
RESULT: The working of Synchronous counters is verified.
Probable Viva Questions:
1. What are synchronous counters?
2. What are the advantages of synchronous counters?
3.What is an excitation table?
4.Write the excitation table for D,T FF.
5.Design mod-5 synchronous counter using TFF
Applications:
Frequency dividers,Delay units, Timers, Real time counters
Remarks :
Signature of Staff Incharge with date:
Department of ETE, DSCE
