Mini Project Report
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY
College of Engineering and Technology
Department of Electronics and Communication Engineering
21ECC211L / Devices and Digital IC Lab
III Semester, 2024- 25(Odd Semester)
Lab code & Title : 21ECC211L & Devices and Digital IC Lab
Year & Semester : 2nd & 3rd
Project Title : Bit Shift-Left Register with Negative-Edge Clock, Clock Enable, Serial In and Serial
Out
Lab Supervisor : Dr. C. Vimala / Dr. K. Jiavana
Team Members Registration No & Name: RA2311053010096 – Harshit Mathur
RA2311053010114 – Ayush Barnwal
RA2311053010117 – Bhavy Tyagi
Reg. No & Name RA2311053010096 RA2311053010114 RA2311053010117
Mark split up Harshit Mathur Ayush Barnwal Bhavy Tyagi
Novelty of the project
(1 mark)
Level of understanding of
the Project (2 marks)
Contribution of the
Project Work (1 mark)
Project Report
(1 Mark)
Total ( 5 Marks)
REPORT VERIFICATION
Date: 10/10/2024 Signature of Lab Supervisor
Mini Project Title Bit Shift-Left Register with Negative-Edge Clock, Clock Enable, Serial In and Serial
Out
OBJECTIVE
To design and implement an 8-bit shift-left register with a negative-edge clock, clock enable,
serial input, and serial output using Verilog HDL. The project aims to demonstrate the
functionality and applications of shift registers in digital circuits.
ABSTRACT
This project involves the design and implementation of an 8-bit shift-left register using Verilog
HDL. The register operates on the negative edge of the clock signal and includes a clock enable
feature. Data is shifted in serially and shifted out serially, making it useful for data storage and
transfer applications. The project includes the design, simulation, and verification of the shift
register, along with a discussion of the results and potential applications.
INTRODUCTION
Shift registers are fundamental components in digital electronics, used for data storage,
transfer, and manipulation. They are widely used in communication systems, data processing,
and digital signal processing. This project focuses on designing an 8-bit shift-left register with
a negative-edge clock, clock enable, serial input, and serial output. The negative-edge clock
ensures that data is shifted on the falling edge of the clock signal, while the clock enable allows
for controlled data shifting.
SOFTWARE&HARDWARE REQUIREMENT/DESCRIPTION
To run the simulation process, the following software tools are required:
Verilog HDL: For writing the hardware description language code.
ModelSim: For simulating the Verilog code and verifying the functionality of the shift
register.
Xilinx ISE: For synthesizing the Verilog code and implementing it on an FPGA, if needed.
CIRCUIT DIAGRAM AND DESCRIPTION
Circuit Diagram: The circuit diagram for the 8-bit shift-left register with a negative-edge
clock, clock enable, serial input, and serial output is based on the provided Verilog code. The
main components include:
Clock ©: The negative-edge triggered clock input.
Clock Enable (CE): The clock enable input that controls whether the shift operation
occurs.
Serial Input (SI): The serial input data that is shifted into the register.
Serial Output (SO): The serial output data that is shifted out from the register.
Description: The shift register is implemented using an 8-bit register (tmp) that stores the data.
The operation of the shift register is controlled by the negative edge of the clock signal (C) and
the clock enable signal (CE). The following steps describe the functionality:
Clock Triggering: The shift operation occurs on the negative edge of the clock signal
(negedge C).
Clock Enable Check: If the clock enable (CE) is high, the shift operation is performed.
Shift Operation: The data in the register (tmp) is shifted left by one position (tmp <=
tmp << 1).
Serial Input: The least significant bit (tmp[0]) is loaded with the serial input (SI).
Serial Output: The most significant bit (tmp[7]) is assigned to the serial output (SO).
CODEBASE
Verilog Code:
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:04:24 10/08/24
// Design Name:
// Module Name: shift_reg
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module shift_reg (C, CE, SI, SO);
input C,SI, CE;
output SO;
reg [7:0] tmp;
always @(negedge C)
begin
if (CE)
begin
tmp <= tmp << 1;
tmp[0] <= SI;
end
end
assign SO = tmp[7];
endmodule
Test Bench:
`timescale 1ns / 1ps
module shift_reg_tb;
// Inputs
reg C;
reg CE;
reg SI;
// Outputs
wire SO;
// Instantiate the shift register module
shift_reg uut (
.C(C),
.CE(CE),
.SI(SI),
.SO(SO)
);
initial begin
// Initialize Inputs
C = 0;
CE = 0;
SI = 0;
// Generate clock signal
forever #5 C = ~C;
end
initial begin
// Apply test vectors
#10 CE = 1; SI = 1;
#10 SI = 0;
#10 SI = 1;
#10 SI = 0;
#10 CE = 0; // Disable clock enable
#20 CE = 1; SI = 1;
#10 SI = 0;
end
endmodule
RESULTS AND DISCUSSION
The shift register was designed and simulated using Verilog HDL. The simulation results show
that the register correctly shifts data on the negative edge of the clock signal when the clock
enable is high. The serial input data is successfully shifted into the register, and the serial
output data is correctly shifted out. The design was also synthesized and implemented on an
FPGA, demonstrating its practical applicability.
CONCLUSION
The project successfully designed and implemented an 8-bit shift-left register with a negative-
edge clock, clock enable, serial input, and serial output. The shift register operates as expected,
demonstrating its usefulness in data storage and transfer applications. The project highlights
the importance of shift registers in digital electronics and their practical applications in various
fields.
REFERENCES
“Verilog code of 8-bit left shift register with posedge clock, async clear, serial in and serial out,” VLSI
Grade. - Verilog code of 8-bit left shift register: - (vlsigrade.com)
“Shift Register - Parallel and Serial Shift Register,” Electronics Tutorials. - Shift Register - Parallel and
Serial Shift Register (electronics-tutorials.ws)
“Verilog examples useful for FPGA & ASIC Synthesis,” ASIC World. - Verilog examples useful for
FPGA & ASIC Synthesis
“8_BIT_SHIFT_LEFT_REGISTER_SISO.VHD,” GitHub. -
VHDL/8_BIT_SHIFT_LEFT_REGISTER_SISO.VHD at main · AkshayAnand2002/VHDL · GitHub
