Name: RITESH KUMAR SINHA (CAN_33679167)
Roll Number: 1KS21EC076
College Name: K S INSTITUTE OF TECHNOLOGY
Department: Electronics and Communication
DATE OF SUBMISSION :13/03/2025
Project: Design an 8-bit shifter which can shift left or right by N-bits,
based on the given inputs using the Verilog HDL.
1. Introduction
A shifter is a combinational or sequential logic circuit that moves binary data left or
right by a specified number of bit positions. In digital circuits, shifting operations
are commonly used in arithmetic operations, logical operations, and data
manipulation.
An 8-bit shifter operates on an 8-bit input and shifts the data left or right by a
specified number of positions (N). The shift operation can be of different types:
1. Logical Shift: Moves bits left or right, filling the vacated positions with
zeros.
2. Arithmetic Shift: Preserves the sign bit for right shifts (used in signed
numbers).
3. Circular (or Rotate) Shift: Moves bits around in a circular manner,
with bits shifted out from one end re-entering at the other end.
An 8-bit shifter is a digital circuit that shifts the bits of an 8-bit binary number either
to the left or right by a specified number of positions. Shifting operations play a
crucial role in computer arithmetic, data processing, and digital signal processing
applications. The primary function of a shifter is to move binary data efficiently,
which is commonly used in multiplication, division, and bitwise operations. By
shifting bits, the value of the binary number can be effectively doubled (left shift) or
halved (right shift), making it an essential component in arithmetic logic units
(ALUs) and other digital systems.
Shifters can be categorized based on their shifting behaviour. Logical shifting moves
bits left or right, filling the vacated positions with zeros. This type of shift is useful
for unsigned binary numbers.
TRUTH TABLE OF 8 BIT SHIFT REGISTER
BLOCK DIAGRAM OF 8 BIT SHIFTER
2. Specification
INPUT:
D (7”0): INPUT DATA
N (2:0): SHIFT AMOUNT
DIR (0) : LEFT SHIFT OF BITS
DIR (1) : RIGHT SHIFT OF THE BITS
OUTPUT:
Q (7:0) : SHIFTED DATA
Design Constraints: The design operates on the Given bits and the no
of the shift amount of the bits in the given direction (0,1) for the shifting
of the 8 bit binary inputs.
Design Architecture
The design consists of the following modules:
8 bit shifter which has the no of the flipflops and the gates are present
are the AND gates and NOR Gates.
1. RTL CODE:
module shifter (
input [7:0] data_in, // 8-bit input data
input [2:0] shift_amount, // 3-bit shift amount (0 to 7)
input dir, // Shift direction: 0 = Left, 1 = Right
output [7:0] data_out // 8-bit shifted output
);
assign data_out = dir ? (data_in >> shift_amount) : (data_in <<
shift_amount); endmodule
2.TESTBENCH CODE
`timescale 1ns / 1ps
module tb_shifter;
reg [7:0] data_in;
reg [2:0] shift_amount;
reg dir;
wire [7:0] data_out;
// Instantiate the 8-bit shifter module
shifter uut (
.data_in(data_in),
.shift_amount(shift_amount),
.dir(dir),
.data_out(data_out) );
initial begin
$dumpfile("dump.vcd"); // Generate waveform file
$dumpvars(0, tb_shifter); // Dump all variables in the testbench
$monitor("Time=%0t | Data=%b | Shift=%d | Dir=%b |
Output=%b",
$time, data_in, shift_amount, dir, data_out);
// Test Case 1: Shift Left by 2
#10 data_in = 8'b00011001; shift_amount = 3'd2; dir = 0;
// Test Case 2: Shift Right by 3 #10 data_in = 8'b11001100;
shift_amount = 3'd3; dir = 1;
// Test Case 3: Shift Left by 5 #10 data_in = 8'b10101010;
shift_amount = 3'd5; dir = 0;
// Test Case 4: Shift Right by 1 #10 data_in = 8'b11110000;
shift_amount = 3'd1; dir = 1;
#10 $finish;
end endmodule
3. Simulation & Verification
Testbench setup:
Input Values are provided for D(0:7)
Shift data are provided for (2:0)
The direction are provided for left =0,And for right =1
The output are stored in 8 bit (0:7)
4. RESULT
5. RESULT AND DISCUSSION
The 8-Shifter was successfully implemented and verified. The
simulation results matched the expected behaviour, confirming the
correctness of the design.
2) Functional Verification of the design using UVM.
Components and Their Working:
1. Testbench (TB)
o The topmost layer that contains all verification components.
2. Test
o Controls the testbench behavior by creating sequences and
configuring the environment.
3. Environment
o It contains the Agent, which includes the Sequencer, Driver, and
Monitor.
o Also contains the Scoreboard, which checks if the DUT's output
matches the expected behavior.
4. Transient Object (Sequence & Sequence Item)
o Sequence: Generates multiple transaction requests.
o Sequence Item: Represents individual transactions that are sent to the
DUT.
5. Agent
o Sequencer: Sends transactions to the Driver.
o Driver: Converts transaction-level operations to signal-level
operations and drives the DUT via the Interface.
o Monitor: Observes DUT signals and sends collected data to the
Scoreboard for verification.
6. Interface
o Provides a connection between the Driver and DUT, carrying signals.
7. DUT (Design Under Test)
o The actual hardware design being verified.
Working Flow:
1. The Test starts and configures the environment.
2. The Sequence generates stimulus (test data).
3. The Sequencer sends these transactions to the Driver.
4. The Driver converts transactions to pin-level signals and applies them to the
DUT via the Interface.
5. The Monitor captures DUT responses and sends them to the Scoreboard.
6. The Scoreboard compares the actual output with expected results.
7. The test completes when all sequences are executed and results are verified.
I . Design
// Code your design here
module shifter_8bit (
input [7:0] data_in, // 8-bit input data
input [2:0] shift_amount, // Shift amount (0 to 7)
input shift_direction, // Shift direction (0: left, 1: right)
output [7:0] data_out // 8-bit shifted output
);
reg [7:0] shifted_data; // Temporary register to hold
shifted data
always @(*) begin
if (shift_direction == 0) begin
// Shift left by shift_amount bits
shifted_data = data_in << shift_amount;
end else begin
// Shift right by shift_amount bits
shifted_data = data_in >> shift_amount;
end
end
assign data_out = shifted_data; // Assign the result to the output
endmodule
I. Testbench
// Code your testbench here
// or browse Examples
// Code your testbench here
// or browse Examples
//`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;
`define TEST_COUNT 200
`include "interface.sv"
`include "sequence_items.sv"
`include "sequencer.sv"
`include "sequence.sv"
`include "driver.sv"
`include "monitor.sv"
`include "scoreboard.sv"
`include "agent.sv"
`include "environment.sv"
`include "test.sv"
// Code your testbench here
// or browse Examples
`timescale 1ns/1ns
`include "uvm_macros.svh"
//`include "shifter_8bit_def.sv"
import uvm_pkg::*;
module top;
bit clk=0;
// bit rst;
shifter_8bit_if top_if(clk);
shifter_8bit dut(
.data_in (top_if.data_in),
.shift_amount (top_if.shift_amount),
.shift_direction (top_if.shift_direction),
.data_out (top_if.data_out )
);
//clock generation
initial forever #0.5 clk=~clk;
initial begin
// rst = 1;
// #2 rst =0;
end
initial begin
uvm_config_db #(virtual shifter_8bit_if) ::
set(null,"*","shifter_8bit_vif",top_if);
`uvm_info("TOP","Configured database for interface...",UVM_LOW)
end
initial begin
run_test("shifter_8bit_test");
end
initial begin
$dumpfile("waveform.vcd");
$dumpvars;
end
endmodule
II. Interface.
interface shifter_8bit_if(input logic clk);
logic [7:0] data_in;
logic [2:0] shift_amount;
logic shift_direction;
logic [7:0] data_out;
endinterface: shifter_8bit_if
III. TEST
class shifter_8bit_test extends uvm_test;
`uvm_component_utils(shifter_8bit_test)
shifter_8bit_env env;
// shifter_8bit_main_seq main_seq;
function new(string name="shifter_8bit_test",uvm_component parent);
super.new(name,parent);
`uvm_info("shifter_8bit_test", "Inside constructor of shifter_8bit_test",
UVM_HIGH)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
env=shifter_8bit_env::type_id::create("env",this);
endfunction: build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
/*
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
phase.raise_objection(this);
// repeat(`TEST_COUNT) begin
// main_seq=shifter_8bit_main_seq::type_id::create("main_seq");class
shifter_8bit_test extends uvm_test;
`uvm_component_utils(shifter_8bit_test)
shifter_8bit_env env;
// shifter_8bit_main_seq main_seq;
function new(string name="shifter_8bit_test",uvm_component parent);
super.new(name,parent);
`uvm_info("shifter_8bit_test", "Inside constructor of shifter_8bit_test",
UVM_HIGH)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
env=shifter_8bit_env::type_id::create("env",this);
endfunction: build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
/*
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
phase.raise_objection(this);
// repeat(`TEST_COUNT) begin
// main_seq=shifter_8bit_main_seq::type_id::create("main_seq");
// main_seq.start(env.agent.seqr);
// end
wait(env.scb.test_cnt==`TEST_COUNT);
phase.drop_objection(this);
endtask
*/
endclass: shifter_8bit_test
class shifter_8bit_mul_test extends shifter_8bit_test;
`uvm_component_utils(shifter_8bit_mul_test)
// shifter_8bit_env env;
shifter_8bit_mul_seq mul_seq;
function new(string name="shifter_8bit_mul_test",uvm_component
parent);
super.new(name,parent);
`uvm_info("shifter_8bit_mul_test", "Inside constructor of
shifter_8bit_mul_test", UVM_HIGH)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
// env=shifter_8bit_env::type_id::create("env",this);
endfunction: build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
phase.raise_objection(this);
repeat(`TEST_COUNT) begin
// forever begin
mul_seq=shifter_8bit_mul_seq::type_id::create("mul_seq");
mul_seq.start(env.agent.seqr);
end
wait(env.scb.test_cnt==`TEST_COUNT);
phase.drop_objection(this);
endtask
endclass: shifter_8bit_mul_test
IV. Environment
IVclass shifter_8bit_env extends uvm_env;
`uvm_component_utils(shifter_8bit_env)
shifter_8bit_agent agent;
shifter_8bit_scoreboard scb;
// shifter_8bit_coverage cov_subscriber; // Declare the coverage subscriber
function new(string name = "shifter_8bit_env", uvm_component parent =
null);
super.new(name, parent);
`uvm_info("shifter_8bit_env", "Inside constructor of shifter_8bit_env",
UVM_HIGH)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
agent = shifter_8bit_agent::type_id::create("agent", this);
scb = shifter_8bit_scoreboard::type_id::create("scb", this);
// cov_subscriber =
shifter_8bit_coverage::type_id::create("cov_subscriber", this); // Instantiate
the coverage subscriber
endfunction : build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
agent.mon.mon_port.connect(scb.scb_port);
// agent.mon.mon_port.connect(cov_subscriber.analysis_export); //
Connect the monitor to the coverage subscriber
endfunction : connect_phase
endclass : shifter_8bit_env
v. Agent
class shifter_8bit_agent extends uvm_agent;
`uvm_component_utils(shifter_8bit_agent)
shifter_8bit_driver drv;
shifter_8bit_monitor mon;
shifter_8bit_sequencer seqr;
function new(string name="shifter_8bit_agent",uvm_component parent);
super.new(name,parent);
`uvm_info("shifter_8bit_agent", "Inside constructor of shifter_8bit_agent",
UVM_HIGH)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
drv=shifter_8bit_driver::type_id::create("drv",this);
mon=shifter_8bit_monitor::type_id::create("mon",this);
seqr=shifter_8bit_sequencer::type_id::create("seqr",this);
endfunction: build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
drv.seq_item_port.connect(seqr.seq_item_export);
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
endtask
endclass: shifter_8bit_agent
VI. Scoreboard
class shifter_8bit_scoreboard extends uvm_scoreboard;
`uvm_component_utils(shifter_8bit_scoreboard)
uvm_analysis_imp #(shifter_8bit_sequence_item, shifter_8bit_scoreboard)
scb_port;
shifter_8bit_sequence_item item[$];
shifter_8bit_sequence_item s_item;
int test_cnt=0;
int test_valid=0;
int test_invalid=0;
function new(string name = "shifter_8bit_scoreboard", uvm_component parent);
super.new(name, parent);
`uvm_info("SCB_CLASS", "Inside Constructor!", UVM_HIGH)
endfunction: new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("SCB_CLASS", "Build Phase!", UVM_HIGH)
scb_port=new("scb_port",this);
endfunction: build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info("SCB_CLASS", "Connect Phase!", UVM_HIGH)
endfunction: connect_phase
function void write (shifter_8bit_sequence_item rx_item);
item.push_front(rx_item);
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
forever begin
this.s_item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("s_item", /* parent = null */, /* contxt =
"\000" */);
wait((item.size() != 0));
s_item=item.pop_front();
// s_item.print();
compare(s_item);
test_cnt++;
end
endtask
function void compare(shifter_8bit_sequence_item item);
logic [31:0] ex_res;
if (item.expected_data_out == item.data_out) begin
`uvm_info(get_name,$sformatf("[%0d/%0d] Test
Passed",test_cnt,`TEST_COUNT),UVM_LOW);
test_analysis(item,ex_res,1);
test_valid++;
end
else begin
`uvm_error(get_name,$sformatf("[%0d/%0d] Test
failed",test_cnt,`TEST_COUNT));
test_analysis(item,ex_res,1);
test_invalid++;
end
endfunction
function void test_analysis(shifter_8bit_sequence_item item, logic [31:0]
ex_res,bit flag);
if(flag) begin
$display("--------------------------------------------------------------------------------");
$display(" data_in= %0h , shift_amount= %0h, shift_direction= %0h, \n
data_out=%0h ,expected_data_out = %0h
,",item.data_in,item.shift_amount,item.shift_direction,item.data_out,item.expected
_data_out);
end
endfunction
/*
randc logic [7:0] data_in; // 8-bit input data
randc logic [2:0] shift_amount; // Shift amount (0 to 7)
randc logic shift_direction; // Shift direction (0: left, 1: right)
logic [7:0] data_out ; // 8-bit shifted output
logic [7:0] expected_data_out ; // 8-bit shifted output
// `uvm_object_utils (shifter_8bit_sequence_item)
*/
function void report_phase(uvm_phase phase);
super.report_phase(phase);
`uvm_info(get_name(),$sformatf("Total tests: %0d",test_cnt),UVM_LOW)
`uvm_info(get_name(),$sformatf("Passed tests: %0d",test_valid),UVM_LOW)
`uvm_info(get_name(),$sformatf("Failed tests:
%0d",(test_invalid/test_cnt)*100),UVM_LOW)
endfunction
endclass
VII. Monitor
class shifter_8bit_monitor extends uvm_monitor;
`uvm_component_utils(shifter_8bit_monitor)
virtual shifter_8bit_if vif;
shifter_8bit_sequence_item item;
uvm_analysis_port #(shifter_8bit_sequence_item) mon_port;
function new(string name="shifter_8bit_monitor",uvm_component parent);
super.new(name,parent);
`uvm_info("shifter_8bit_monitor", "Inside constructor of shifter_8bit_monitor",
UVM_HIGH)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
mon_port=new("mon_port",this);
if(!(uvm_config_db #(virtual
shifter_8bit_if)::get(this,"*","shifter_8bit_vif",vif)))
`uvm_error(get_name(), "Faild to get Virtual IF from database...")
endfunction: build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
forever begin
// item=shifter_8bit_sequence_item::type_id::create("item");
this.item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("item", /* parent = null */, /* contxt =
"\000" */);
//this.s_item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("s_item", /* parent = null */, /* contxt =
"\000" */);
sample(item);
`uvm_info(get_name(),"Item received!!",UVM_HIGH)
mon_port.write(item);
end
endtask
task sample(shifter_8bit_sequence_item item);
// item.rst=vif.rst;
// @(negedge vif.rdy);
//
@(posedge vif.clk);
// #1;
item.data_in = vif.data_in;
item.shift_amount = vif.shift_amount;
item.shift_direction = vif.shift_direction;
item.expected_data_out = (item.shift_direction == 0) ? (item.data_in <<
item.shift_amount) : (item.data_in >> item.shift_amount);
item.data_out = vif.data_out;
// item.A = vif.A;
// item.B = vif.B;
// item.result = vif.result;
// item.exception = vif.exception;
// item.overflow = vif.overflow;
// item.underflow = vif.underflow;
// item.done = vif.done;
// @(posedge vif.clk);
endtask
endclass: shifter_8bit_monitor
VIII. Driver
class shifter_8bit_driver extends uvm_driver #(shifter_8bit_sequence_item);
`uvm_component_utils(shifter_8bit_driver)
virtual shifter_8bit_if vif;
shifter_8bit_sequence_item item;
function new(string name="shifter_8bit_driver",uvm_component parent);
super.new(name,parent);
`uvm_info("shifter_8bit_driver", "Inside constructor of shifter_8bit_driver",
UVM_HIGH)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
if(!(uvm_config_db #(virtual
shifter_8bit_if)::get(this,"*","shifter_8bit_vif",vif)))
`uvm_error(get_name(), "Faild to get Virtual IF from database........")
endfunction: build_phase
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
/* repeat(2) begin
item=shifter_8bit_sequence_item::type_id::create("item");
seq_item_port.get_next_item(item);
init_drive(item);
//item.print();
seq_item_port.item_done();
end
*/
forever begin
// item=shifter_8bit_sequence_item::type_id::create("item");
this.item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("item", /* parent = null */, /* contxt =
"\000" */);
//this.s_item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("s_item", /* parent = null */, /* contxt =
"\000" */);
seq_item_port.get_next_item(item);
drive(item);
//item.print();
seq_item_port.item_done();
end
endtask
task drive(shifter_8bit_sequence_item item);
`uvm_info(get_name(),"Drive...",UVM_HIGH)
//vif.rst=item.rst;
@(posedge vif.clk);
// vif.A<=item.A;
// vif.B<=item.B;
vif.data_in = item.data_in;
vif.shift_amount = item.shift_amount;
vif.shift_direction = item.shift_direction;
`uvm_info("DRIVER", $sformatf("Driving Data: %h, Shift: %h, Direction:
%b", item.data_in, item.shift_amount, item.shift_direction), UVM_MEDIUM)
// Allow combinational logic to settle
// seq_item_port.item_done();
// vif.valid=item.valid;
// vif.AgreaterthanB=item.AgreaterthanB;
// vif.AlessthanB=item.AlessthanB;
// vif.AequaltoB=item.AequaltoB;
endtask
/*
task init_drive(shifter_8bit_sequence_item item);
`uvm_info(get_name(),"Init Drive...",UVM_HIGH)
//vif.rst=item.rst;
@(posedge vif.clk);
vif.a<=item.a;
vif.b<=item.b;
endtask
*/
endclass: shifter_8bit_driver
IX. Sequence items
class shifter_8bit_sequence_item extends uvm_sequence_item;
// rand logic rst;
// randc logic [31:0] A;
// randc logic [31:0] B;
// logic [31:0] result;
// logic exception;
// logic overflow;
// logic underflow;
// logic done;
randc logic [7:0] data_in; // 8-bit input data
randc logic [2:0] shift_amount; // Shift amount (0 to 7)
randc logic shift_direction; // Shift direction (0: left, 1: right)
logic [7:0] data_out ; // 8-bit shifted output
logic [7:0] expected_data_out ; // 8-bit shifted output
// `uvm_object_utils (shifter_8bit_sequence_item)
function new(string name="shifter_8bit_sequence_item");
super.new(name);
endfunction
/*module shifter_8bit (
input [7:0] data_in, // 8-bit input data
input [2:0] shift_amount, // Shift amount (0 to 7)
input shift_direction, // Shift direction (0: left, 1: right)
output [7:0] data_out // 8-bit shifted output
);
reg [7:0] shifted_data; // Temporary register to hold shifted data
*/
//`uvm_object_utils_begin(shifter_8bit_sequence_item)
// `uvm_field_int(A, UVM_ALL_ON)
// `uvm_field_int(B, UVM_ALL_ON)
// `uvm_field_int(result, UVM_ALL_ON)
// `uvm_object_utils_end
Endclass
X. Sequencer
class shifter_8bit_sequencer extends uvm_sequencer
#(shifter_8bit_sequence_item);
`uvm_component_utils(shifter_8bit_sequencer)
function new(string name="shifter_8bit_sequencer",uvm_component parent);
super.new(name,parent);
`uvm_info("shifter_8bit_sequencer", "Inside constructor of
shifter_8bit_sequencer", UVM_HIGH)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
endfunction: build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
endclass: shifter_8bit_sequencer
XI. Sequence
class shifter_8bit_base_sequence extends uvm_sequence;
`uvm_object_utils(shifter_8bit_base_sequence)
shifter_8bit_sequence_item shifter_8bit_item;
function new(string name="shifter_8bit_sequence");
super.new(name);
endfunction
endclass: shifter_8bit_base_sequence
class shifter_8bit_mul_seq extends shifter_8bit_base_sequence;
`uvm_object_utils(shifter_8bit_mul_seq)
shifter_8bit_sequence_item item;
function new(string name="shifter_8bit_mul_seq");
super.new(name);
endfunction
task body();
`uvm_info(get_name(),"Running main sequence...",UVM_HIGH);
// item=shifter_8bit_sequence_item::type_id::create("item");
this.item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("item", /* parent = null */, /* contxt =
"\000" */);
//this.s_item = uvm_object_registry#(shifter_8bit_sequence_item,
"shifter_8bit_sequence_item")::create("s_item", /* parent = null */, /* contxt =
"\000" */)
start_item(item);
item.randomize();
// rst == 1'b0; };
finish_item(item);
end task
end class
Waveform (In Testbench)
initial
begin
$dumpfile("dump.vcd");
$dumpvars();
End
Result :
EDA link : 8bit_shifter(2) - EDA Playground
Generate GDS using OpenROAD tool
In this section, the layout of the RTL code has been
generated using the OpenROAD software tool.
Technology/Platform utilized: sky130hd
Instructions of the config.mk
export
DESIGN_NICKNAM
E = project_2 export
DESIGN_NAME =
shifter_8bit export
PLATFORM
= shy130hd
export VERILOG_FILES = $(sort $(wildcard
$(DESIGN_HOME)/src/$(DESIGN_NICK
NAME)/ shifter_8bit.v)) export SDC_FILE
=
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
#export PLACE_PINS_ARGS = -min_distance 4 -
min_distance_in_tracks export
CORE_UTILIZATION = 0.5
#export CORE_ASPECT_RATIO = 1
#export CORE_MARGIN = 2
export
PLACE_DENSIT
Y = 0.1 export
TNS_END_PER
CENT = 100
#export EQUIVALENCE_CHECK ?= 0
#export REMOVE_CELLS_FOR_EQY = sky130_fd_sc_hd tapvpwrvgnd*
#export FASTROUTE_TCL =
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NIC
KNME)/fastroute.tcl #export
REMOVE_ABC_BUFFERS = 1
Instructions of the constraint.sdc
current_design shifter_8bit
set clk_name v clk
#set clk port_name clk
Set clk_period 2.5
Set clk_io_pct 0.2
# Set clk port [get_port $clk_port_name]
create_clock -name
$clk_name -period $clk_period
set non_clock_inputs [lsearch -inline -all -not [all_inputs]]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name
$non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -
clock $clk_name [all_outputs]
LAYOT OF THE DESIGN
Performance Analysis
Power Measurement:
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
Sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Combinational 1.15e-11 1.20e-12 1.13e-08
1.13e-08 7.3% Clock 0.00e+00
0.00e+00 1.43e-07 1.43e-07 92.7% Macro
0.00e+00 0.00e+00
0.00e+00 0.00e+00 0.0% Pad 0.00e+00
0.00e+00 0.00e+00 0.00e+00 0.0%
Total 1.15e-11 1.20e-12 1.55e-07 1.55e-07
Area Measurement:
Design area 0 u^2 29% utilization.
Timing Information:
Startpoint: shift_amount[2] (input port)
End point:07_/A(internal pin)
Path group: unconstrained
Path Type: max
Delay Time Description
0.00 0.00 ^ input external delay
0.0 0.00 ^ shift_amount[2] (in)
0.00 0.00 ^ _057_/A (sky130_fd_sc_hd
clkbuf_2)
0.00 data arrival time
Generated GDS
Conclusions
In this report, the RTL code of 8-bit shift register has been
designed in verilog. The code is successfully verified with the
UVM with 100% test case pass. The design code is further
processed in the openROAD tool to generate its GDS using
the gf180 platform. It has shown that the generated layout
consumes 155nW power which occupies 4662 sq. um area.
There is no setup and hold violations.
FUTURE SCOPE
High-Performance Computing (HPC)
Low-Power and Energy-Efficient Designs.
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