CHAPTERS

Field Effect Transistors

Objectives

You will be able to: 7 Show how a JFET can be used

1 Explain the operation of n- for voltage amplification and
channel and p-channel junction for switching.
field effect transistors (JFETs). 8 Explain the operation of
Draw typical JFET enhancement-mode and
characteristics. Identify the depletion-enhancement-mode
regions of the characteristics MOSFETs.
and all important current and Draw typical drain and transfer
voltage levels. characteristics for MOSFETs,
For JFETs, define saturation
and discuss the differences
current, pinch-off voltage,
between MOSFETs and JFETs.
forward transfer admittance,
10 Solve problems involving
output admittance, and drain-
source on resistance. MOSFET characteristics and
parameters.
Determine JFET parameter
values from manufacturers’ 11 Explain the operation of
data sheets. VMOSFETs, sketch typical
From the data sheet characteristics, and discuss the
information, draw the advantages of VMOS.
maximum and minimum 12 Sketch circuit symbols for
transfer characteristics for any JFETs, MOSFETs, and VFETs.
given JFET type number. Identify all terminals, current
6 Solve problems involving JFET directions, and voltage
characteristics and parameters. polarities.

INTRODUCTION
A field effect transistor (FET) is a voltage-operated device that can be used in
amplifiers and switching circuits, similar to a bipolar transistor. Unlike a BJT,
a FET requires virtually no input current. This gives it an extremely high
input resistance, which is its most important advantage over a BJT. There are
two major categories of field effect transistors: junction FETs and MOSFETs.
These are further subdivided into p-channel and n-channel devices.
346 Electronic Devices and Circuits

9-1 JUNCTION FIELD EFFECT TRANSISTORS

n-Channel JFET
The operating principle of an n-channel junction field effect transistor (JFET) is
illustrated by the block representation in Fig. 9-1a. A piece of n-type semicon-
ductor material, referred to as the channel, is sandwiched between two smaller
pieces of p-type (the gates). The ends of the channel are designated the drain
(D) and the source (S), and the two pieces of p-type material are connected
together and their terminal is named the gate (G).
With the gate left unconnected and a drain-source voltage (Vp) applied
(positive at the drain, negative at the source), a drain current (Ip) flows, as
shown in Fig. 9-1a. When a gate-source voltage (Vcs) is applied with the gate
negative with respect to the source (Fig. 9-1b), the gate-channel pn-junctions
are reverse biased. The channel is more lightly doped than the gate material,
so the depletion regions penetrate deep into the channel. Because the
depletion regions are regions depleted of charge carriers, they behave as
insulators. The result is that the channel is narrowed, its resistance is
increased, and Ip is reduced. When the negative gate-source bias voltage is
further increased, the depletion regions meet at the centre of the channel
(Fig. 9-1c), and Ip is cut off.

+Vp Drain +p tap

Drain (D) oe current b 55
Depletion £P. letion
WiyPS regions regions
channel meet \ e

Fi Ip De) 2
AL
<I
p-type 74 Vv, GS .
V Gs Voss
cst oj
= *¢
gates (G)
Source (S) fe spy

(a) No gate-source (b) Small negative gate- (c) Large negative gate
bias voltage source bias voltage source bias voltage

Figure 9-1 Ann-channel JFET consists of an n-type channel with p-type gate regions on
each side.

An ac signal applied to the gate causes the reverse gate-source voltage to

increase as the instantaneous level of the signal goes negative, and to
decrease when the signal is positive-going. This causes the gate-channel
depletion regions to widen and decrease successively. When the si gnal goes
negative, the depletions widen, the channel resistance is increased, and the
drain current decreases. As the signal goes positive, the depletion regions
recede, the channel resistance is reduced, and the drain current increases. It is
 Chapter 9 Field Effect Transistors 347

seen that the FET gate-source voltage controls the D

drain current. The gate-channel pn-junctions are
maintained in reverse bias, so the gate current is
normally extremely low, much lower than the base S
current for a BJT. (a) Circuit Symbol for
The name field effect transistor comes from the eshte EE
fact that the depletion regions in the channel are D
produced by the electric field at the reverse- G
biased gate-channel junctions. The term unipolar
device is sometimes applied to a FET, because, un- S
like a bipolar transistor, the current consists of () Alternative circuit symbol
only one type of charge carrier: electrons in the
case of an n-channel device. D
Circuit symbols for an n-channel JFET are G Go
shown in Fig. 9-2. As in the case of all
symbols, the arrowhead S
semiconductor device
(c) Tetrode-connected JFET
points from p-type to n-type. For an n-channel
device, the arrowhead points from the p-type gate Figure 9-2 Circuit sym-
so. . ‘ bols for an n-channel
to the n-type channel. This is the direction of JFET. Like all semicon-
conventional current flow if the junctions become ductor symbols, the
forward biased. Some device manufacturers use arrowheads point from
the symbol in Fig. 9-2a with the gate directly at i to the n-type
opposite the source terminal. Others show the
gate centralized between the drain and source (Fig. 9-2b). This can
sometimes make circuit diagrams confusing unless the drain and source
terminals are clearly identified. The symbol in Fig. 9-2c is used when the
terminals of the two gate regions are provided with separate connecting
leads. In this case, the device is referred to as a tetrode-connected FET.

p-Channel JFET
In a p-channel JFET, shown in block form in Fig. 9-3a, the channel is a p-type
semiconductor, and the gates are n-type. The drain-source voltage (Vp) is
applied negative to the drain and positive to the source, as illustrated, and
the drain current flows (in the conventional direction) from source to drain.
To reverse-bias the gate-channel junctions, the n-type gate regions must be
made positive with respect to the p-type channel. So the bias voltage is
applied positive on the gate terminals and negative on the source.
A positive-going signal at the gate terminal of a p-channel JFET increases
the gate-channel junction reverse bias, causing the depletion regions to
penetrate further into the channel. This increases the channel resistance and
decreases the drain current. Conversely, a negative-going signal narrows
the depletion regions, reduces the channel resistance, and increases the drain
current.
348 Electronic Devices and Circuits
4

Negative
supply ae fr D
voltage Dip
G
G ( |G
S
Die) &
Ves Vos D
Positive ——~ T “~~ Positive G
gate-source = S a gate-source
bias bias
= S
(a) p-channel JFET (b) Circuit symbols for
p-channel JFET

Figure 9-3 A p-channel JFET operates in exactly the same way as an

n-channel device, except that the current directions and voltage polarities
are reversed.

Circuit symbols for a p-channel JFET are shown in Fig. 9-3b. The arrow-
heads again point from the p-type material to the n-type, in this case, from
the p-type channel to the n-type gate.

JFET Fabrication and Packaging

Junction field-effect transistors are normally
manufactured by the diffusion process (see Gate
terminals
Chapter 7). This type of construction is illus-
trated in Fig. 9-4. Starting with a p-type sub-
strate, an n-channel is diffused; then, p-type im-
purities are diffused into the channel. Finally, Source Drain (Gates
metal terminal connections are deposited
through holes in the silicon dioxide surface, as
illustrated.
The n-type region is the FET channel, and
the two p-type regions constitute the gates.
With this symmetrical construction, the drain
and source terminals are interchangeable.
Other fabrication techniques produce device
geometry that is not symmetrical. In these
cases, interchanging the drain and source ter- Top view
minals would radically affect the performance
Figure 9-4 Cross-section and
of the device. top view of n-channel JFET.
Figure 9-5 shows several FET packages With this type of construc-
which are similar to BJT enclosures. Note the tion, the drain and source
are interchangeable.
device terminal identifications in each case.
 Chapter9 Field Effect Transistors 349

DSG 5 5 D cH
Sy cy
|} Bottom view Cc Top view

Bottom view eB
DSG SpG Side view
(a) Resin encapsuled FET (b) Metal can-enclosed FET (c) Surface mount FET
Figure 9-5 Various JFET enclosures.

Section 9-1 Review —

9-1.1 ‘Sketch a block oan ston of an n-channel JFET. Indicate voltages
irection, and explain the device operation.
9-1.2 Repeat Question 9-1.1 for a p-channel JFET. :
9-1.3 Ske ircuit symbols for n-channel and p-channel JFETs. Identify the
: als and briefly explain.

9-2 JFET CHARACTERISTICS

Depletion regions
An n-channel JFET block representation is shown in some detail in Fig. 9-6.
With a drain-source voltage applied as illustrated, Ip flows in the direction
+ tone caged ao

shown, producing voltage drops along the channel. Consider the voltage
drops from the source terminal (S) to points A, B, and C within the channel.
PointA is positive with respect to the source; alternatively, it can be stated that
S is negative with respect to A. Because the gate blocks are connected to 5, the

+Vp

Depletion Depletion
Tegions regions

= a p. G

Va
Figure 9-6 Drain current in an n-channel JFET
causes voltage drops along the channel which
S reverse-bias the gate channel junctions. This pro-
duces different levels of depletion region pene-
iL tration into the channel.
350 Electronic Devices and Circuits

gates are negative with respect to point A by a voltage Va. This causes the de-
pletion regions to penetrate into the channel by an amount proportional to V4.
The voltage drop between point B and the source is Vp, which is less than
Va. Consequently, at point B on the channel the gates are at — Vp with respect
to the channel, and the depletion region penetration is less than at point A.
From point C to the source terminal, the voltage drop (Vc) is less than V3.
Thus, the gate-channel reverse bias (at point C) is Vc volts, and the depletion
region penetration is less than at points A or B. The differing voltage drops
along the channel, and the resulting variation in gate-channel reverse bias,
account for the shape of the depletion region penetration of the channel.

Drain Characteristics with Ve; = 0

Figure 9-7 shows a circuit for determining the drain-current versus drain-
source voltage characteristic for an n-channel JFET with Vos = 0. Vps is
increased in convenient steps from zero, and Ip |
is measured at each Vpg level. This produces a
table of Ip/Vps values for plotting the charac-
teristic shown in Fig. 9-8.
Referring to the characteristic, it is seen that
when Vps = 0, Ip = 0. There is no channel volt- Vesg=0
age drop, and so the voltage between the gate
and all points on the channel is zero, and there Figure 9-7 Circuit for obtain-
is no depletion region penetration. When Vp is ing the Ip/Vps characteristic
‘ db ll t(] th 1V for an n-channel junction
increase . y 2 Sah amioun (less an ),a field effect transistor with
small drain current flows, producing some Ves = 0.

(mA Channel
ohmic , Breakdown
12 4+— region->+~—_ Pinch-off region — region —
|
| | Vos = 0 }
fgg = ! Le

8
ft |
|
Ip 6+ ! |

|| |
44 o
Li

24
||
|
0 -—}-—_+—__+—_}+—__}+—__+—__ ++ (v)
0 2 4 6 8 10 12 14 16 18
Vos f
Vp Breakdown
voltage

Figure 9-8 Ip/Vps characteristic for an n-channel JFET with Vos = 0.

 Chapter9 = Field Effect Transistors 351

voltage drop along the channel. This results in some depletion penetration of
the channel (as explained for Fig. 9-6), but it is so small that it has no signifi-
cant effect on the channel resistance. With further small increases in Vpg, the
drain current increase is approximately linear and the channel behaves as an
almost constant-value resistance (see Fig. 9-8).
The channel continues to behave as a fixed-value resistance until the volt-
age drops along it become large enough to produce considerable depletion
region penetration. At this stage the channel resistance begins to be affected
by the depletion regions. Further increases in Vps now produce smaller Ip
increases, as shown by the curved part of the characteristic. The increased Ip
levels, in turn, cause more depletion region penetration and greater channel
resistance. Eventually, a saturation level of Ip is reached where further Vps
increase seems to have no effect on Ip.
At the point on the characteristic where Ip levels off, the drain current is
referred to as the drain-source saturation current (Ipss) (10 mA in Fig. 9-8). The
shape of the depletion regions in the channel at the Ipss level is such that they
appear to pinch off the channel (see Fig. 9-6). Thus, the drain source voltage at
this point is termed the pinch-off voltage (Vp) (4.5 V in Fig. 9-8.) The region of th.
characteristic where Ip is constant is called the pinch-off region, as illustrated.
The channel mostly behaves like a resistance between the points where Vps = 0
and Vps = Vp;so this part of the characteristic is referred to as the channel ohmic
region.
If Vps is continuously increased (in the pinch-off region), a voltage is
reached at which the (reverse-biased) gate-channel junctions break down
(see Fig. 9-8). When this happens, Ip increases rapidly and the device may be
destroyed. The pinch-off region of the characteristic is the normal operating
region for the FET.

Drain Characteristics with External Bias

A circuit for obtaining the Ip/Vps characteristics for an n--channel JFET when
an external gate-source bias (Vgs) is applied is shown in Fig. 9-9. In this case,
Ves is set to a convenient (negative) level
(such as —1 V). Vps is increased in steps, and
the corresponding level of Ip is noted at each
Vps step. The Ip/Vps characteristic for a Veg of
—1 Vis then plotted, as illustrated in Fig. 9-10.
When a —1 V external gate-source bias volt-
age is applied, the gate-channel junctions are
reverse biased even when Ip = 0. So when Figure 9-9 Circuit for obtain-
Vps = 0, the depletion regions are already ing the Ip/Vps characteristic
penetrating to: some depth into the channel. for an n-channel junction
field effect transistor with
Because of this, a smaller voltage drop along vadoustete-aenmes tins
the channel (smaller than when Ves = 0) will voltages.
352 Electronic Devices and Circuits

increase the depletion regions to the point at which they produce channel
pinch-off. Consequently, when Vcg = —1 V the pinch-off voltage is reached at
a lower Ip level than when Vos = 0. The Ves = —1 V characteristic in Fig. 9-10
has Vp = 3.5 V.

(mA)
Rt 4] 4 - | 7 :
Ipss — 10
Veogss0
GS
| |1 |
'

Saturation dens eer |

Liste | |
current for Ves —-1V 1 | |
Vcgs = -1V it |
| ff ei
Ip | |
—__| fy |
| ) |
|
— | 14 ||
1] | |
0 a | te (V)
0 2 4 6 8 10 12 14 16 18

Vp Vps Breakdown
: voltage for
Pinch-off Veg = -1V
voltage for

Figure 9-10 [,/Vps characteristics for Ves = 0 and Ves = —1 for an n-channel! JFET.

A family of drain characteristics can be obtained by using several levels of

negative gate-source bias voltage (see Fig. 9-11). If a positive Veg is used, a
higher level of Ip can be produced, as shown by the characteristic for
Ves = +0.5 V. However, Vcs is normally kept negative to avoid the
possibility of forward-biasing the gate-channel junctions.
The dashed line from the zero point on the characteristics in Fig. 9-11 is
drawn through the points at which Ip saturates for each level of gate-
source bias voltage. When Vcs=0, Ip saturates at Ipss, and_ the
characteristic shows Vp = 4.5 V. When a —1 V external bias is applied, the
gate-channel junctions still require —4.5 V to achieve pinch-off. This
means that a drop of 3.5 V instead of 4.5 V is now required along the
channel, and the lower voltage drop is achieved with a lower Ip. Similarly,
when Ves = —2 V and —3 V, pinch-off is achieved with 2.5 V and 1.5 V,
respectively, along the channel. The 2.5 V and 1.5 V drops are, of course,
obtained with further reduced Ip levels.
Suppose a —4.5 V gate-source bias is applied to a device with the
characteristics shown in Fig. 9-11. This is a Vgs level equal to the pinch-
off voltage Vp. Without any additional channel voltage drop produced by
Ip, the depletion regions penetrate so deep into the channel that they
 Chapter9 Field Effect Transistors 353

(V)
10 122 #144 «6 #18
V,
1.5 V3.5 iS
25V45V
Figure 9-11 Family of Ip/Vps characteristics for an n-channel JFET
with various levels of Vgs.

meet in the middle, completely cutting Ip off. So, a gate-source bias equal to
the pinch-off voltage reduces Ip to zero. The bias voltage required to do this
is termed the gate cutoff voltage (Vcsiorm), and, as explained, Vesvoty = Ve.
Note in Fig. 9-11 that the drain-source voltage at which breakdown occurs is
reduced as the negative gate-source bias voltage is increased. This is
because — Vcs adds to the reverse bias at the junctions.

Example 9-1
Plot the Ip/ Vps characteristic for a JFET from the following table of values
obtained with Vcs = 0. Determine Ipss and Vp from the characteristics.

Solution
On Fig. 9-12, plot point 1 where Vps = 0 and Ip = 0.

Plot point 2 at Vps = 1 V and Ip = 3 mA,

Vps = 9 V and Ip = 8 mA.
and so on through
Draw the drain characteristic for Vcs = 0 through points 1 to 10.

From the characteristic, Ipsg = 8 mA and Vp = 3.75 V.

 354 Electronic Devices and Circuits

(mA)
12

10

(V)

Figure 9-12 FET characteristics for Ex. 9-1.

Transfer Characteristics
The transfer characteristics for an n-channel JFET are a plot of Ip versus Vs.
The gate-source voltage of an FET controls the level of the drain current; so
the transfer characteristic shows how Ip is controlled by Vcs. As illustrated
in Fig. 9-13a, the transfer characteristic extends from Ip = Ipss at Vcs = 0, to
Ip = 0 at Ves = —Vos(orp-
Figure 9-13b shows a circuit for determining experimentally a table of
quantities for plotting the transfer characteristic of a given FET. The drain-

-5 -4 -3 -2 -1 0
i
Ves(ott)
(a) Transfer characteristic (b) Circuit for determining
the transfer characteristic
Figure 9-13 The transfer characteristics for a FET are a plot of
Ip versus Ves.

source voltage is maintained constant, Vcsis adjusted in convenient steps, and

the corresponding levels of Vs and Ip are recorded.
 Chapter 9 Field Effect Transistors 355

The transfer characteristic for a FET can be derived from the drain
characteristics. A line is drawn vertically on the drain characteristics to
represent a constant Vps level. The corresponding Ip and Vgs values along
this line are noted and then used to plot the transfer characteristic. The
process is demonstrated in Ex. 9-2.

Example 9-2
Derive the transfer characteristic for Vps=8 V from the FET drain
characteristics in Fig. 9-11.

Solution

On Fig. 9-11, draw a vertical line at Vps = 8 V.

From the intersection of the line and the char-
acteristics, read the following quantities:
> 10

On Fig. 9-14, plot point 1 at Vcg=0 and

Ip = 10 mA. Plot point 2 at Ves = —1 V and
Ip = 7 mA, and so on through Ves = —4 V
and Ip = 0.5 mA. Draw the transfer charac-
Ves
teristic through these points.
Figure 9-14 Transfer character-
istics for Ex. 9-2.
p-Channel JFET Characteristics
Figure 9-15 shows a circuit for obtaining the
characteristics of a p-channel JFET. Note the
direction of the arrowhead on the FET symbol,
and the drain current direction. Note also the
supply voltage polarity and the polarity of the
gate-source bias voltage. The drain terminal is
negative with respect to the source, and the gate
terminal is positive with respect to the source.
To obtain a table of quantities wefor plotting a ee Glroult fordeter-
Sf . ining the characteristics of
drain characteristic, Vcs is maintained constant a p-channel JFET.
at the desired (positive) level, — Vps is increased
in steps from zero, and the Ip levels are noted at each step.
Typical p-channel JFET drain characteristics and transfer characteristics are
shown in Fig. 9-16. It is seen that these are similar to the characteristics for an
 356 Electronic Devices and Circuits

Transfer (mA) Drain characteristics

characteristic
4 wet -Veg= =0.5-V- _ |
|
bs = 9

SS
Figure 9-16 Transfer and drain characteristics for a p-channel JFET.

n-channel JFET, except for the voltage polarities. In Fig. 9-16, when Vcs = 0,
Ipss = 15 mA, and progressively more positive levels of Vcs reduce |p toward
cutoff Vesory) = +6 V. Using Ves of —0.5 V produces a higher Ip than when
Vcs = 0. As in the case of the n-channel JFET, forward bias at the gate-channel
junctions should be avoided; consequently, negative Vcs levels are normally
not used with a p-channel JFET.
The transfer characteristic for a p-channel device can be obtained experi-
mentally or can be derived from the drain characteristics, just as for an
n-channel FET.

Practice Problem
9-2.1 The following table of Ip/Vps values for a FET was obtained with a Vcs
of 0. Plot the drain characteristic and determine Ipss and Vp.

10 12

ae } SS

9-3 JFET DATA SHEETS AND PARAMETERS

Maximum Ratings
Typical FET data sheets A-11 and A-12 are shown in Appendix A, and part of
a FET data sheet is reproduced in Fig. 9-17. As with other device data sheets, a
device type number and brief description are usually given at the top. Maxi-
mum ratings follow, and then the electrical characteristics are stated
for
 Chapter9 Field Effect Transistors 367

"Ds(on) Vpsvon)

(a) FET switching circuit (b) The on channel resistance

iS Tyson)

Figure 9-28 Direct-coupled n-channel JFET switching circuit. The output switches from
Vpp to Ip X rpsion) When the input changes from —Vg to zero.

Like a BJT switch, a FET switching circuit has turn-on and turn-off times that are
made up of delay time, rise time, storage time, and fall time. FET switching
times tend to be shorter than BJT times because a FET does not have a forward-
biased junction with a diffusion capacitance (like the BJT base-emitter junction).
FET switching circuits are covered further in Section 10-11.

Practice Problem
9-4.1 AFET amplifier circuit, as in Fig 9-27, has Vpp = 15 V,R, = 4.7 kQO, and
_v; = +30 mV. If Ve is adjusted so that Ip = 1.5 mA, calculate Vp. Also,
calculate the typical voltage gain for the circuit if Qi is a 2N5459 with
Ys = 4500 pS.

9-5 MOSFETs

Enhancement MOSFET
Figure 9-29 shows the construction of a metal oxide semiconductor FET (MOS-
FET), also known as an insulated gate FET. Starting with a high-resistive
p-type substrate, two blocks of heavily-doped Metal
plate
n-type material are diffused into the substr ite,
gource Cake Hiesta
and then the surface is coated with a layer Of
silicon dioxide. Holes are cut through the silicon
O

dioxide to make contact with the n-type blocks.

Metal is deposited through the holes for source p-type substrate
metal
and drain terminals, as illustrated, and a
en Figure 9-29 Metal oxide
plate is deposited on the surface area betwe
drain and source. As will be explained, this semiconductor FET (MOS-
FET) construction.
plate functions as a gate.
nal of the
Consider the situation illustrated in Fig. 9-30a. The drain termi
circuited.
MOSFET is positive with respect to the source, and the gate is open-
368 Electronic Devices and Circuits

p-type substrate p-type substrate

x
Enhanced
n-type channel
(a) Vps applied and gate (b) Effect of positive Ves
open-circuited
Figure 9-30 Effect of +Vps on the MOSFET with the gate terminal
open-circuited and with +Ves applied to the gate.

The two n-type blocks and the p-type substrate form back-to-back pn-junctions
connected by the resistance of the p-type material, as illustrated. The
pn-junction close to the drain terminal is reverse biased, so that only a very
small (reverse-leakage) current flows from D to S.
Now assume that the source terminal is connected to the substrate and
that a positive gate voltage is applied, as shown in Fig. 9-30b. Negative
(minority) charge carriers within the substrate are attracted to the (positive)
plate that constitutes the gate. Since these charge carriers (electrons) cannot
cross the silicon dioxide to the gate, they accumulate close to the surface of
the substrate, as shown. The minority charge carriers constitute an #-type
channel between drain and source, and as the gate-source voltage is made
more positive, more electrons are attracted into the channel, causing the
channel resistance to decrease. A drain current flows along the channel
between the D and S terminals, and because the channel resistance is
controlled by the gate-source voltage (Vgs), the drain current is also
controlled by Vgs. The channel conductivity is said to be enhanced by the
positive gate-source voltage, and so the device is known as an en/iayicesiieiil-
mode MOSFET (EMOSFET or EMOS transistor).
Typical drain and transfer characteristics for an n-channel EMOS device
are shown in Fig. 9-31. Note that on both characteristics the drain current
increases as the positive gate-source bias voltage is increased. Because the
gate of the MOSFET is insulated from the channel, there is no gate-source
leakage current and the device has an extremely high (gate) input resistance:
typically 10° © or greater. Typical forward transfer admittance values for
this type of (low-power) MOSFET range from 1 mS (1 mA/V) to a maximum
of perhaps 6 mS, which is similar to JFET Y;, values.
Two graphic symbols for the n-channel EMOS transistor are shown in
Fig. 9-32. One symbol shows the source and substrate connected internally,
while the other has a separate substrate terminal. The line representing the
 Chapter 9 Field Effect Transistors 369

Transfer
(mA) characteristic
12

10

in
4

0 (V)
0 5 10 15 20
Reet ++ Vps
0123456

Ves
Figure 9-31 Typical drain and transfer characteristics for an
n-channel EMOS transistor.

device channel is broken into three sections to D D

indicate that the channel does not exist until an
appropriate gate voltage is applied. ‘Io show . <
that the device has an insulated gate, the gate S S
symbol does not make direct contact with the Geibistnte
channel. The arrowhead points from the Figure 9:32 Circuit symbols
p-type substrate to the n-type channel. for an n-channel EMOSFET.
A p-channel EMOS transistor is constructed
by starting with an n-type substrate and diffusing p-type drain and source
blocks, as illustrated in Fig. 9-33a. The device characteristics are similar to
those in Fig. 9-31, except that all voltage polarities and current directions are
reversed. The drain-source voltage is negative, and a negative gate-source
voltage is required to create the p-type channel. The arrowheads in the circuit
symbols are also reversed (see Fig. 9-33b).
Source Gate Drain,
O O D

G
é Figure 9-33 Construction and
Poostoy circuit symbol for a p-channel

(a) p-channel EMOSFET (b) Circuit symbol EMOSFED.

Depletion-Enhancement MOSFET
The device cross-section shown in Fig. 9-34a is similar to that for an EMOS
transistor, except that a lightly doped n-type channel is included between the
drain and source blocks. When a positive drain-source voltage (Vps) is
applied, a drain current (Ip) flows even when the gate-source voltage (Vgs) is
zero. If anegative Vs is applied, as shown in Fig. 9-34b, some of the negative
370 Electronic Devices and Circuits

charge carriers are repelled from the gate and driven out of the n-type
channel. This creates a depletion region in the channel, as illustrated, causing
an increase in channel resistance and a decrease in drain current. The effect is
similar to that in an n-channel JFET. Because of the channel depletion
regions, the device can be termed a depletion-mode MOSFET.
Now consider what happens when a positive gate-source voltage is applied.
Additional n-type charge carriers are attracted from the substrate into the
channel, decreasing its resistance and increasing the drain current. So the
depletion-mode MOSFET can also be operated as an enhancement-mode
device. Thus, these devices can be referred to as depletion-enhancement MOSFETs
or DE-MOSFETs; however, the term DMOSFET is normally applied.

Vos Vps
—3]1|+ +
Ves = 0 p|

S G D S oD
Se lp

p-type substrate p-type substrate

| J NG | T™~—SY Ss
n-type channel Depletion region

(a) Ip flows even when Voz = 0 (b) Ip decreases when Vcz is negative,
and increases when Vcg is positive

Figure 9-34 n-Channel depletion-enhancement MOSFET.

(mA)

om 1 een Drain characteristics

|
—-_|—40 +-}— | Ves tH |
f | [Enhancement mode
| 1 Oo ee a ~ ~ ‘VY, el 0 7 | | |
Transfer Ip j = +—
characteristics | ¢ eect ae Herpes { | |
A | _| | | |
| Ves -1V| | |
La 2 Vv
pi
ep
|\Depletion
:
mode >
| | Veg
| Lf 5 ——_—— -
| J [ Vos = —3 Vv |

t t+ (V)
0 5 10 15 20
Vos ee
~4-3-2-101234
Vos
Figure 9-35 Drain and transfer characteristics for an n-channel depletion-enhancement
MOSFET.
 Chapter9 ‘Field Effect Transistors 371

Typical drain and transfer characteristics for a DMOSFET are shown in

Fig. 9-35. The device operates in the depletion mode when Vgs is negative,
and in the enhancement mode when positive
D D
levels of Vcs are used.
The circuit symbols used for DMOSFETs are G G
similar to those already discussed for EMOSFETs,
except that the line representing the channel is : =
made solid to show that a channel is present when Substrate
Vos = 0 (see Fig. 9-36). Figure 9-36 Circuit symbols
for an n-channel depletion-
enhancement MOSFET.
Example 9-7
From the DMOSFET characteristics in Fig. 9-35, determine the forward
transfer admittance at Vcs = 0.

Solution
At Veg = —2V, Ip = 2.2mA

and at Ves = +2V, Ip = 11.8mA

Alp = 11.8 mA — 2.2 mA = 9.6mA

and AVcg = +2 V —- (-2V)
=4V
Al :
Eq. 9-2: i, os O . =, a4V
AVcgs
= 2.4mA/V = 2400 pS

VMOSFET
A disadvantage of the MOSFET types already discussed is that the minimum
channel length depends upon the dimensions of the photographic masks
used in the manufacturing process. Shorter channel lengths can be produced
by changing the geometry of the MOSFET to create a vertical channel
(instead of horizontal). The channel length is then easily determined by the
diffusion process. The shorter channel results in lower resistance, greater
power dissipation, higher frequency response, and larger forward transfer
admittance values than are possible with other MOSFETs.
Figure 9-37a shows a device referred to as a VMOSFET because of its
V-shaped configuration, and because it uses a vertical channel between drain
and source. The V-cut penetrates from the surface of the device through Ws
p, and n~ layers almost to the n* substrate. The n* layers are low-resistive,
and the n~ is a high-resistive region. The silicon dioxide layer covers both the
horizontal surface and the V-cut surface. The gate is a metal film deposited
on the silicon dioxide surface in the V-cut. The drain terminal is at the bottom
of the n* substrate, and the source connection is made to the top n* region
and to the p region.
372 Electronic Devices and Circuits

Metal
Silicon
film
dioxide

Metal Drain

film (a) V-FET construction (b) Enhanced channel connects

the drain and source
Figure 9-37 \VMOSFET construction and operation. The vertical channel gives an
improved frequency response, lower channel resistance, and greater power dissipation
than other FETs.

The VMOSFET operates in the enhancement mode; no channel exists until

a positive gate source voltage is applied. An n-type channel is created as
shown in Fig. 9-37b when Vs is made positive and a current flows vertically
from drain to source.
Some versions of VMOSFETs use a vertical channel but do not use the V-cut.
Motorola currently manufactures devices referred to as TMOS, because the drain
current flow tends to be T-shaped. International rectifier uses the term Hexfet,
because of the hexagonal configuration employed in the device construction.
Typical VMOSFET drain and transfer characteristics are shown in
Fig. 9-38. It can be seen that they are similar to the enhancement-mode device
characteristics in Fig. 9-31, although much higher drain current levels are
usually involved with a VMOSFET than with other MOSFETs. The
characteristics shown are for a device capable of dissipating 40 W.

“) (A)
20 | l = 20 + —
| |
ipf | |__| etfs | / 18 +
| | ; | Veg = +9V
16 ! . 16 +——! =
|

145 4 44+ |
Vos= +8V
iT yP al aha
12 +—}- 12 +
Vee ] |
Ip 10 - | Starting ai | Pio L + Vi L7\

8 5 § = —. —_

spelen | |
tt 6+ | | Ves = +6
6 Hl

4 |__| | 44-5 a

2+— 4
4
2 =
| Vv iS t5V
|

0 eS +-—++ (V) 0 a ee oe
7 42 fs fa 8 0 ‘n 5 =
=a Vescityp Vestnmar Ves Vos

(a) Transfer characteristics (b) Drain characteristics

Figure 9-38 Typical transfer and drain characteristics for a VMOSFET.
 — Chapter 9 Field Effect Transistors 373

The VMOSFET transfer characteristic is seen Parasitic

to be approximately linear over most of its diode
length, and it is curved (non-linear) only at the : i
low current levels. For the typical characteristic
shown, Ip commences at the typical gate thresh- Gc G
old voltage (Vcs(th)typ), and the slope of the linear
portion of the graph is set by the typical gps value he aoa p-channel
(same as Y fs). It should be noted that for a device
with a given type number, Ip might begin at Figure 9-39 Circuit symbols
for VMOSFETs.
Ves(th)min OF VGs(th)ymax,,and that the slope of the
characteristic depends upon the actual gps for
the device. Temperature changes can also have a serious effect on the character-
istics, as shown by the dashed lines.
The graphic symbols used for VMOS devices are the same as for other
enhancement-mode MOSFETs. However, a parasitic pn-junction is present
between the p and n™ layers in a VMOSFET, and this must not be allowed to
become forward biased. So the diode is usually shown on the device symbol
(see Fig. 9-39).
VMOS devices can be described as high-voltage, EMOSFETs. They are
very suitable for high-frequency or fast switching applications. Normally,
they have much larger forward transfer admittance (gps) values and lower
drain-source on resistances than other FETs. Figure 9-40 lists some
performance data for two representative (low-power and high-power)
VMOSFETs. Note that the 80 mS minimum grs for the 2N7002 is substantially
larger than the 4 mS typical for other FET types. The IRF520 has a typical gps
of 2.9 S, which is greater again than that for the 2N7002. FET voltage
amplification is directly proportional to the forward transfer admittance; so
VMOSFET circuits can have much greater voltage gains than circuits using
other FETs.

_ 2N7002,
|| Ypsqmax) | Fogmaxy | Promax) | “a(on) Srs Vosith)
P| 60V | 115ma | 200mw| 750 | 80mS(min) | 1V (min)
S: 2.5 V (max)

“1 Viscmax)': Tomax) | Ppgmax) | Ta(on) 8rs Ves(tn)

|| 100V 8A 4ow | 030 1.5 S (min) 2 V (min)
Rey 2.9S (typ) 4 V (max)

Performance data for low-power and high-power VMOSFETs.

374 Electronic Devices and Circuits

MOSFET specifications normally list gate threshold voltage (Vcsin)) values.

The drain current remains at zero with gate-source voltage levels below
Vos(th) and begins to flow when Vgg is increased above Vegith). S0 Vesith) is
similar to the pinch-off voltage for a JFET. Like the JFET pinch-off voltage,
Vas(th) has maximum and minimum values for each device type number.
For a JFET, Ipss is the drain current when Vcs = 0. The EMOSFET para-
meter identified as Ipgg is still the drain current at zero gate-source voltage.
However, because the device is off when Veg = 0, Ipss is a drain-source leak-
age current with a level measured in microamps. For EMOSFET devices, Ip is
usually specified as Ipon) at Veg = 10 V.
EMOSFETs are often applied in situations where they are biased on to a
low drain current level, and then Ip is increased to a desired higher level by
the application of a signal voltage. The precise levels of the required gate-
source bias and signal voltages can be determined only from the transfer
characteristic for each individual device. However, for a given Ip level
beyond the curved part of the characteristic, a rough approximation for the
required Vgs can be calculated from the maximum Vestn) and the typical grs
values, as follows:
Ip
Ves ~ V esthjmax + ——— (9-5)
SFS(typ)
Example 9-8
Using the information in Fig. 9-40, calculate the approximate gate-source
voltage required to produce a 7 A drain current in an IRF520. Determine the
drain-source on voltage and the device power dissipation at Ip = 7 A.

Solution
Ip 7A
Eq. 9-5: Vos © Ves¢thy(max) + — = EW + pac

=64V

Vision) = Ip X rojon) = 7A X 0.3.0

=2.1V
P= Ip ® View 7A X ELV
=14.7W

Comparison of n-Channel and p-Channel FETs

Recall from Section 1-5 that electrons have greater mobility than holes.
Consequently, hole current velocity is approximately one-third of electron
current velocity. Furthermore, a sample of p-type material has a resistivity
approximately three times that of a similar equally-doped n-type sample.
Thus, given equal doping densities, an n-channel FET will have a lower
 Chapter 9 Field Effect Transistors 375

resistance (lower ra(on)) than a similar p-channel device. In some applications,

n-channel and p-channel MOSFETs are both used in circuits where it is
important to have equal rg(on) Values. In this case, the p-channel devices are
more expensive to manufacture than the n-channel MOSFETs. For these
reasons, n-channel JFETs and MOSFETs tend to be preferred to p-channel
FETs for many applications.

Handling MOSFETs
Figure 9-41 shows the kind of label normally \
found on packages containing MOSFETs. This peevICes
means that the devices can be very easily
destroyed by electrostatic discharge (ESD), that is, :
the discharge of static electricity that accumu- ie
lates on individuals or objects. Usually the very {
thin layer of silicon dioxide at the gate breaks
down when an excessive gate-source voltage is ©
applied. Special precautions are necessary to eine ain es
protect MOSFETs from ESD: enclosed devices can be de-
stroyed by static electricity.
1. Always store MOSFETs in closed conduc-
tive containers. They are usually packaged
with the terminals inserted into conducting i
foam rubber.
2. Use a work station with a grounded anti-static G+
bench-top pad and a grounded anti-static floor L
pad. t
3. Wear anti-static clothing and grounded wrist S
bands. Figure 9-42 MOSFET with
4. Use a soldering iron with a grounded tip. built-in Zener diodes for
5. Avoid touching the device terminals. protection against static
electricity.
Some MOSFETs have built-in protection against static electricity. Back-to-
back series-connected Zener diodes are located between the gate and source
terminals, as illustrated in Fig. 9-42. When the gate-source voltage is high
enough to reverse-bias one of the diodes into breakdown, the other diode is
forward-biased. Thus the gate-source voltage cannot exceed +(Vz + Vp).

! tions, explain the operation of n-channel EMOSFET.

symbols for n-channel and p-channel EMOS and DMOS