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Agilex™ 7 FPGAs and SoCs Device Data Sheet

F-Series and I-Series

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 Contents

Contents

Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series..........................................................................................3
Electrical Characteristics...................................................................................................................................................... 5
Operating Conditions.................................................................................................................................................. 5
Switching Characteristics....................................................................................................................................................29
Core Performance Specifications.................................................................................................................................30
Periphery Performance Specifications.......................................................................................................................... 40
E-Tile Transceiver Performance Specifications...............................................................................................................48
P-Tile Transceiver Performance Specifications............................................................................................................... 52
R-Tile Transceiver Performance Specifications...............................................................................................................57
F-Tile Transceiver Performance Specifications............................................................................................................... 63
HPS Performance Specifications................................................................................................................................. 82
Configuration Specifications.............................................................................................................................................. 116
General Configuration Timing Specifications............................................................................................................... 116
POR Specifications..................................................................................................................................................117
External Configuration Clock Source Requirements......................................................................................................118
JTAG Configuration Timing.......................................................................................................................................118
AS Configuration Timing.......................................................................................................................................... 120
Avalon Streaming (Avalon-ST) Configuration Timing....................................................................................................123
Configuration Bit Stream Sizes................................................................................................................................. 124
I/O Timing......................................................................................................................................................................125
Programmable IOE Delay..................................................................................................................................................125
Glossary.........................................................................................................................................................................126
Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series....................................... 129

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Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing.

Until the data sheet status for a device reaches Final, the specifications are subject to change at any time and at Intel's
discretion.

Table 1. Data Sheet Status for Agilex™ 7 FPGAs and SoCs F-Series
Device Tile Package Status

AGF 012/014 E-Tile and P-Tile R24A Final

AGF 012/014 E-Tile and P-Tile R24B Final

AGF 019/022/023/027 E-Tile and P-Tile R25A Final

AGF 006/008 F-Tile R16A Preliminary

AGF 006/008/012/014/019/022/023/027 F-Tile R24C Preliminary

AGF 019/022/023/027 F-Tile R31C Preliminary

AGF 006/008/012/014 F-Tile R24D Preliminary

Table 2. Data Sheet Status for Agilex™ 7 FPGAs and SoCs I-Series
Device Tile Package Status

AGI 019/023 R-Tile and F-Tile R18A Preliminary

AGI 022/027 R-Tile and F-Tile R29A Preliminary

AGI 022/027 R-Tile and F-Tile R31A Preliminary

AGI 019/022/023/027 F-Tile R31B Preliminary

continued...

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera and Intel warrant performance of its

FPGA and semiconductor products to current specifications in accordance with Altera’s or Intel's standard warranty as applicable, but reserves the right to make
changes to any products and services at any time without notice. Altera and Intel assume no responsibility or liability arising out of the application or use of any ISO
information, product, or service described herein except as expressly agreed to inwriting by Altera or Intel. Altera and Intel customers are advised to obtain the 9001:2015
latest version of device specifications before relying on any published information and before placing orders for products or services. Registered
*Other names and brands may be claimed as the property of others.
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Device Tile Package Status

AGI 035/040 F-Tile R39A Preliminary

AGI 041 R-Tile and F-Tile R29D Preliminary

AGI 041 F-Tile R31B Preliminary

AGI 041 R-Tile and F-Tile R31E Preliminary

The following descriptors designate the status level currently applicable to the relevant variant:
• Advance: These are target specifications based on simulation.
• Preliminary: These specifications are based on simulation, early validation, and/or early characterization data.
• Final: These are production specifications based on silicon validation and/or characterization.

Table 3. Device Grades, Core Speed Grades, and Power Options Supported
For specification status, see the Data Sheet Status table

Device Grade Speed Grade and Power Option Supported

Extended –E1V (fastest)

–E2V

–E3V

–E3E

–E4X

–E4F

Industrial –I1V

–I2V

–I3V

–I3E

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The suffix after the speed grade denotes the power options offered.
• V—standard power (VID)
• E—lower power (VID)
• X—lowest power (VID)
• F—fixed voltage

Related Information
Package and Thermal Resistance website

Electrical Characteristics
The following sections describe the operating conditions and power consumption.

Operating Conditions
The devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of
the devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these
conditions.

Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Table 4. Absolute Maximum Ratings

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Maximum Unit

VCC Core voltage power supply — –0.5 1.14 V

VCCP Periphery circuitry power — –0.5 1.14 V

supply
continued...

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Symbol Description Condition Minimum Maximum Unit

VCCPT Power supply for I/O PLL — –0.5 2.08 V

and I/O pre-driver

VCCRCORE CRAM power supply — –0.5 1.64 V

VCCH Transceiver digital power Devices with E-Tile and P- –0.5 1.21 V
supply Tile

Devices with R-Tile and F- –0.5 1.07 V

Tile

Devices with F-Tile only –0.5 1.07 V

VCCH_SDM SDM block transceiver Devices with E-Tile and P- –0.5 1.21 V
digital power sense Tile

Devices with R-Tile and F- –0.5 1.21 V

Tile

Devices with F-Tile only –0.5 1.07 V

VCCIO_PIO_SDM SDM block I/O bank power — –0.5 2.01 V

sense of bank 3A

VCCIO_SDM SDM block configuration — –0.5 2.08 V

pins power supply

VCCL_SDM SDM block core voltage — –0.5 1.07 V

power supply

VCCFUSEWR_SDM SDM block fuse writing — –0.5 2.4 V

power supply

VCCPLLDIG_SDM SDM block PLL digital — –0.5 1.07 V

power supply

VCCPLL_SDM SDM block PLL analog — –0.5 2.08 V

power supply

VCCBAT Battery back-up power — –0.5 2.08 V

supply (For design security
volatile key register)

VCCADC ADC voltage sensor power — –0.5 2.08 V

supply

VCCIO_PIO I/O bank power supply — –0.5 2.01 V

continued...

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Symbol Description Condition Minimum Maximum Unit

VCCA_PLL I/O clock network power — –0.5 1.64 V

supply

VCCRT_GXE Transceiver power supply E-Tile devices –0.5 1.21 V

VCC_HSSI_GXE E-Tile digital signal power E-Tile devices –0.5 1.21 V

supply

VCCRTPLL_GXE Transceiver PLL power E-Tile devices –0.5 1.21 V

supply

VCCH_GXE Analog power supply E-Tile devices –0.5 1.47 V

VCCCLK_GXE LVPECL REFCLK power E-Tile devices –0.5 3.41 V

supply

VCCRT_GXP Transceiver power supply P-Tile devices –0.5 1.21 V

VCC_HSSI_GXP P-Tile digital signal power P-Tile devices –0.5 1.21 V

supply

VCCFUSE_GXP P-Tile efuse power supply P-Tile devices –0.5 1.21 V

VCCCLK_GXP P-Tile I/O buffer power P-Tile devices –0.5 2.46 V

supply

VCCH_GXP High voltage power for P-Tile devices –0.5 2.46 V

transceiver

VCCEHT_GXR Transceiver analog high R-Tile devices –0.5 2.03 V

voltage power

VCCERT_GXR Transceiver analog power R-Tile devices –0.5 1.33 V

supply

VCCED_GXR Transceiver digital power R-Tile devices –0.5 1.21 V

supply

VCCE_PLL_GXR PLLs power supply R-Tile devices –0.5 1.33 V

VCCE_DTS_GXR DTS power supply R-Tile devices –0.5 1.33 V

VCCCLK_GXR Reference clock power R-Tile devices –0.5 1.34 V

supply

VCCHFUSE_GXR R-Tile efuse power supply R-Tile devices –0.5 1.34 V

VCC_HSSI_GXR Digital signal power supply R-Tile devices –0.5 1.21 V

continued...

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Symbol Description Condition Minimum Maximum Unit

VCC_HSSI_GXF F-Tile digital signal power F-Tile devices –0.5 1.07 V

supply

VCCFUSECORE_GXF F-Tile fuse writing power F-Tile devices –0.5 1.37 V

supply

VCCFUSEWR_GXF F-Tile efuse power supply F-Tile devices –0.5 1.37 V

VCCCLK_GXF Reference clock power F-Tile devices –0.5 2.04 V

supply

VCCERT1_FHT_GXF FHT analog core supply 1 F-Tile devices –0.5 1.33 V

VCCERT2_FHT_GXF FHT analog core supply 2 F-Tile devices –0.5 1.33 V

VCCEHT_FHT_GXF FHT high voltage power F-Tile devices –0.5 1.99 V

supply for analog circuit

VCCERT_FGT_GXF FGT analog core supply F-Tile devices –0.5 1.34 V

VCCH_FGT_GXF FGT analog I/O power F-Tile devices –0.5 2.04 V

supply

VCCERT_GXF_COMBINE Combined analog core F-Tile devices –0.5 1.33 V

supply

VCCL_HPS HPS core voltage and — –0.5 1.21 V

periphery circuitry power
supply

VCCPLLDIG_HPS HPS PLL digital power — –0.5 1.21 V

supply

VCCPLL_HPS HPS PLL analog power — –0.5 2.08 V

supply

VCCIO_HPS HPS I/O buffers power — –0.5 2.08 V

supply

VI DC input voltage VCCIO_PIO = 1.2 V –0.3 1.56 V

VCCIO_PIO = 1.5 V 0 1.7 V

VCCIO_SDM, VCCIO_HPS = 1.8 –0.3 2.19 V

V

IOUT (1) (2) DC output current per pin VCCIO_PIO = 1.2 V, 1.5 V (3) –15 15 mA

continued...

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Symbol Description Condition Minimum Maximum Unit

VCCIO_SDM, VCCIO_HPS = 1.8 –20 20 mA

V (4)

TJ Absolute junction — –55 125 °C

temperature

TSTG Storage temperature — –55 150 °C

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following tables and undershoot to –1.1 V when
using VCCIO_HPS/ VCCIO_SDM of 1.8 V and –0.3 V when using VCCIO_PIO of 1.2 V for input currents less than 100 mA and periods
shorter than 20 ns.

No overshooting beyond 1.7 V and undershooting below 0 V is allowed when using VCCIO_PIO = 1.5 V.

The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) × 100) over
the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

(1) Total current per I/O bank must not exceed 100 mA.
(2) Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os.
(3) The maximum current allowed through any GPIO bank pin when the device is not turned on or during power-up/power-down
conditions is 10 mA. Pin voltage during these conditions should not exceed 1.2 V or the VCCIO_PIO supply rail of the bank where the
I/O pin resides in, whichever is the lower voltage.
(4) The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down
conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HPS or VCCIO_SDM supply rail of the bank where the
I/O pin resides in.

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Table 5. Maximum Allowed Overshoot During Transitions (for 1.2 V I/O in GPIO Bank)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) AC input voltage VCCIO_PIO + 0.30 100 %

VCCIO_PIO + 0.35 37 %

VCCIO_PIO + 0.40 9 %

VCCIO_PIO + 0.45 3 %

VCCIO_PIO + 0.50 1 %

> VCCIO_PIO + 0.50 No overshoot allowed %

Table 6. Maximum Allowed Overshoot During Transitions (for 1.8 V I/O in HPS and SDM I/O Banks)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ Unit

= 100°C

Vi (AC) AC input voltage VCCIO_SDM + 0.30, VCCIO_HPS + 100 %

0.30

VCCIO_SDM + 0.35, VCCIO_HPS + 60 %

0.35

VCCIO_SDM + 0.40, VCCIO_HPS + 30 %

0.40

VCCIO_SDM + 0.45, VCCIO_HPS + 20 %

0.45

VCCIO_SDM + 0.50, VCCIO_HPS + 10 %

0.50

VCCIO_SDM + 0.55, VCCIO_HPS + 6 %

0.55

>VCCIO_SDM + 0.55, >VCCIO_HPS No overshoot allowed %

+ 0.55

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For example, when using 1.2 V I/O standard with 1.26 V VCCIO_PIO, a signal that overshoots to 1.71 V can only be at 1.71 V
for ~3% over the lifetime of the device. For an overshoot of 1.56 V, the percentage of high time for the overshoot can be as
high as 100% over the lifetime of the device.

Figure 1. Overshoot Duration Example (for 1.2 V GPIO Bank at VCCIO_PIO = 1.26 V)

1.76 V

1.56 V

1.2 V

DT
T

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters.

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Recommended Operating Conditions

Table 7. Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum(5) Typical Maximum(5) Unit

VCC Core voltage power SmartVID(6) : –1V, – (Typical) – 3% 0.70 – 0.90(7) (Typical) + 3% V
supply 2V, –3V, –3E, –4X

Fixed voltage: –4F 0.776 0.8 0.824 V

VCCP Periphery circuitry SmartVID(6): –1V, – (Typical) – 3% 0.70 – 0.90(7) (Typical) + 3% V

power supply 2V, –3V, –3E, –4X

Fixed voltage: –4F 0.776 0.8 0.824 V

VCCPT Power supply for I/O — 1.71 1.8 1.89 V

PLL and I/O pre-driver

VCCRCORE CRAM power supply — 1.14 1.2 1.26 V

VCCH Advanced interface Devices with E-Tile 0.87 0.9 0.93 V

bus (AIB) power and P-Tile
supply
Devices with R-Tile 0.776 0.8 0.824 V
and F-Tile

Devices with F-Tile 0.776 0.8 0.824 V

only

VCCH_SDM SDM block transceiver Devices with E-Tile 0.87 0.9 0.93 V
digital power sense and P-Tile
continued...

(5) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(6) The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus voltage
regulator and SmartVID devices are connected via PMBus.
(7) The typical value is based on the SmartVID programmed value.

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Symbol Description Condition Minimum(5) Typical Maximum(5) Unit

Devices with R-Tile 0.87 0.9 0.93 V

and F-Tile

Devices with F-Tile 0.776 0.8 0.824 V

only

VCCIO_PIO_SDM (8) SDM block I/O bank 1.5 V 1.455 1.5 1.545 V
power sense of Bank
3A 1.2 V 1.14 1.2 1.26 V

VCCIO_SDM SDM block — 1.71 1.8 1.89 V

configuration pins
power supply

VCCL_SDM SDM block core — 0.776 0.8 0.824 V

voltage power supply

VCCFUSEWR_SDM SDM block fuse writing — 1.75 1.8 1.85 V

power supply

VCCPLLDIG_SDM SDM block PLL digital — 0.776 0.8 0.824 V

power supply

VCCPLL_SDM SDM block PLL analog — 1.71 1.8 1.89 V

power supply

VCCBAT (9) Battery back-up power — 1 — 1.8 V

supply (For design
security volatile key
register)
continued...

(5) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(8) Must be powered up with the same voltage level as VCCIO_PIO_3A. Must be supplied at 1.2 V when using Avalon®-ST ×16/×32
configuration schemes.
(9) Power up VCCBAT with a non-volatile battery power source when using the device security AES BBRAM key. When not using the AES
BBRAM key, tie this pin to ground.

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Symbol Description Condition Minimum(5) Typical Maximum(5) Unit

IBAT (10) Battery back-up power VCCBAT = 1.2 V — — 200 nA

supply (For design
security volatile key
register)

VCCADC ADC voltage sensor — 1.71 1.8 1.89 V

power supply

VCCIO_PIO I/O bank power supply 1.5 V 1.455 1.5 1.545 V

1.2 V 1.14 1.2 1.26 V

VCCA_PLL I/O clock network — 1.14 1.2 1.26 V

power supply

VI (11) DC input voltage VCCIO_PIO = 1.2 V –0.3 — VCCIO_PIO + 0.3 V

VCCIO_PIO = 1.5 V 0 — 1.7 V

VCCIO_SDM = 1.8 V –0.3 — VCCIO_SDM + 0.3 V

VCCIO_HPS = 1.8 V –0.3 — VCCIO_HPS + 0.3 V

VO Output voltage VCCIO_PIO = 1.2 V, 1.5 0 — VCCIO_PIO V

V

VCCIO_SDM = 1.8 V 0 — VCCIO_SDM V

VCCIO_HPS = 1.8 V 0 — VCCIO_HPS V

TJ Operating junction Extended 0 — 100 °C

temperature
Industrial –40(12) — 100 °C

tRAMP (13) (14) Power supply ramp Standard POR 200 μs — 100 ms —
time

(5) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(10) At 25 °C. This supply current specification does not apply to –E4F speed grade and power option device.
(11) This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the
maximum value.

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E-Tile Transceiver Power Supply Recommended Operating Conditions

Table 8. E-Tile Transceiver Power Supply Recommended Operating Conditions

For specification status, see the Data Sheet Status table

Symbol Description Typical DC Level Recommended DC Recommended VR Recommended AC Maximum (DC Unit
(V) Setpoint (% of Ripple (% of Transient (% of Setpoint + Ripple
Vnominal) Vnominal) Vnominal) + AC Transient)
(% of Vnominal)

VCCRT_GXE (15) Transceiver power 0.9 ± 0.5% ± 2.5% ± 3% V

supply

VCC_HSSI_GXE E-tile digital signal 0.9 ± 0.5% ± 2.5% ± 3% V

power supply

VCCRTPLL_GXE (15) Transceiver PLL 0.9 ± 0.5% ± 2.5% ± 3% V

power supply

VCCH_GXE Analog power 1.1 ± 0.5% ± 0.5% ± 2% ± 3% V

supply

VCCCLK_GXE LVPECL REFCLK 2.5 ± 0.5% ± 0.5% ± 3.5% ± 5% V

power supply

Related Information
AN 910: Intel Agilex 7 Power Distribution Network Design Guidelines
Provides the PCB design guidelines.

(12) E-Tile supports an operating temperature range of –40°C to 100°C. However, the E-Tile transceivers may experience a higher error
rate from –40°C to –20°C because of the calibration procedure when starting at a low temperature. Therefore, the recommended
operating temperature range for E-Tile protocol-compliant transceiver links is –20°C to 100°C. The maximum temperature ramp rate
is 2°C per minute.
(13) tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
(14) To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating
conditions.
(15) The difference between VCCRT/VCCRTPLL and VCCH should be no less than 200 mV.

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P-Tile Transceiver Power Supply Recommended Operating Conditions

Table 9. P-Tile Transceiver Power Supply Recommended Operating Conditions

The specifications below should be met at the board vias directly connected to the package power balls. Place the VR sense point in the FPGA pinfield (in the
package shadow), as close as possible to the corresponding package power balls. For these rails, measure the output voltage at this remote sense location.

For specification status, see the Data Sheet Status table

Symbol Description Typical DC Level Recommended DC Recommended VR Recommended AC Maximum (DC Unit
(V) Setpoint (% of Ripple (% of Transient (% of Setpoint + Ripple
Vnominal) Vnominal) Vnominal) + AC Transient)
(% of Vnominal)

VCCRT_GXP Transceiver power 0.9 ± 0.5% ± 2.5% ± 3% V

supply

VCC_HSSI_GXP P-tile digital signal 0.9 ± 0.5% ± 2.5% ± 3% V

power supply

VCCFUSE_GXP P-tile efuse power 0.9 ± 0.5% ± 2.5% ± 3% V

supply

VCCCLK_GXP (16) P-tile I/O buffer 1.8 ± 0.5% ± 0.5% ± 2% ± 3% V

power supply

VCCH_GXP (16) High voltage power 1.8 ± 0.5% ± 0.5% ± 2% ± 3% V

for transceiver

Related Information
AN 910: Intel Agilex 7 Power Distribution Network Design Guidelines
Provides the PCB design guidelines.

(16) Follow the more stringent tolerance range for the voltage rails connecting multiple power supplies.

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R-Tile Transceiver Power Supply Recommended Operating Conditions

Table 10. R-Tile Transceiver Power Supply Recommended Operating Conditions

For specification status, see the Data Sheet Status table

Symbol Description Typical DC Level Recommended DC Recommended VR Recommended AC Maximum (DC Unit
(V) Setpoint (% of Ripple (% of Transient (% of Setpoint + Ripple
Vnominal) Vnominal) Vnominal) + AC Transient)
(% of Vnominal)

VCCH_GXR[L,R] (17) Transceiver analog 1.8 ±0.5% ±2% ±2.5% V

high voltage power

VCCRT_GXR[L,R] Transceiver analog 1 ±0.5% ±2% ±2.5% V

power supply

VCCED_GXR[L,R] Transceiver digital 0.9 ±0.8% ±2.5% ±3.3% V

power supply

VCCE_PLL_GXR[L,R] PLLs power supply 1 ±0.5% ±1.5% ±2% V

VCCE_DTS_GXR[L,R] DTS power supply 1 ±0.5% ±1.5% ±2% V

VCCCLK_GXR[L,R] (17) Reference clock 1 ±0.5% ±2.5% ±3% V

power supply

VCCHFUSE_GXR R-tile efuse power 1 ±0.5% ±2.5% ±3% V

supply

VCC_HSSI_GXR Digital signal power 0.9 ±0.8% ±2.5% ±3.3% V

supply

Related Information
AN 910: Intel Agilex 7 Power Distribution Network Design Guidelines
Provides the PCB design guidelines.

(17) Follow the more stringent tolerance range for the voltage rails connecting multiple power supplies.

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F-Tile Transceiver Power Supply Recommended Operating Conditions

Table 11. F-Tile Transceiver Power Supply Recommended Operating Conditions

To prevent F-Tile performance degradation, devices with F-Tile must not remain in a powered-up and unconfigured state for a cumulative time exceeding 12
months.

For specification status, see the Data Sheet Status table

Symbol Description Typical DC Level Recommended DC Recommended VR Recommended AC Maximum (DC Unit
(V) Setpoint (% of Ripple (% of Transient (% of Setpoint + Ripple
Vnominal) Vnominal) Vnominal) + AC Transient)
(% of Vnominal)

VCC_HSSI_GXF F-Tile digital signal 0.8 ±0.5% ±0.5% ±2.5% ±3% V

power supply

VCCFUSECORE_GXF F-Tile fuse writing 1 ±0.5% ±4.5% ±5% V

power supply

VCCFUSEWR_GXF F-Tile efuse power 1 ±0.5% ±4.5% ±5% V

supply

VCCCLK_GXF Reference clock 1.8 ±0.5% ±0.5% ±2% ±3% V

power supply

VCCERT1_FHT_GXF (18) FHT analog core 1 ±0.5% ±0.5% ±1.5% ±2.5% V

supply 1

VCCERT2_FHT_GXF (19) FHT analog core 1 ±0.5% ±0.5% ±1.5% ±2.5% V

supply 2

VCCEHT_FHT_GXF (20) FHT high voltage 1.5 ±0.5% ±0.5% +1%/–1.5% +2%/–2.5% V
power supply for
analog circuit
continued...

(18) HF noise requires AC 10 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤5 mVpp.
(19) HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤5 mVpp.
(20) HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤7 mVpp.

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Symbol Description Typical DC Level Recommended DC Recommended VR Recommended AC Maximum (DC Unit
(V) Setpoint (% of Ripple (% of Transient (% of Setpoint + Ripple
Vnominal) Vnominal) Vnominal) + AC Transient)
(% of Vnominal)

VCCERT_FGT_GXF (21) FGT analog core 1 ±0.5% ±0.5% ±1.5% ±3% V

supply alone

FGT analog core 1 ±0.5% ±0.5% ±1.5% ±2.5% V

supply when
combined with
VCCERT1_FHT_GX and
VCCERT2_FHT_GXF 1 V
supply

VCCH_FGT_GXF (21) FGT analog I/O 1.8 ±0.5% ≤5 mV ±1.5% ±3% V

power supply

Related Information
AN 910: Intel Agilex 7 Power Distribution Network Design Guidelines
Provides the PCB design guidelines.

HPS Power Supply Recommended Operating Conditions

Table 12. HPS Power Supply Recommended Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with ARM-based hard processor system (HPS). Power
supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected
from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Typical Maximum Unit

VCCL_HPS HPS core voltage and Performance boost, (Typical) – 3% 0.95 (Typical) + 3% V
periphery circuitry fixed voltage: –1V
power supply
SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
3V, –3E (22)
continued...

(21) HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple: ≤5mVpp.

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Symbol Description Condition Minimum Typical Maximum Unit

Fixed voltage: –4F, – 0.776 0.8 0.824 V

4X

VCCPLLDIG_HPS HPS PLL digital power Performance boost, (Typical) – 3% 0.95 (Typical) + 3% V
supply (can be fixed voltage: –1V
connected to VCCL_HPS)
SmartVID: –1V, –2V, – (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
3V, –3E (22)

Fixed voltage: –4F, – 0.776 0.8 0.824 V

4X

VCCPLL_HPS HPS PLL analog power 1.8 V 1.71 1.8 1.89 V

supply

VCCIO_HPS HPS I/O buffers power 1.8 V 1.71 1.8 1.89 V

supply

Related Information
• Recommended Operating Conditions on page 12
Provides the steady-state voltage values for the FPGA portion of the device.
• HPS Clock Performance on page 82

DC Characteristics

Supply Current and Power Consumption

Intel® offers two ways to estimate power for your design—the Intel FPGA Power and Thermal Calculator (PTC) and the Intel
Quartus® Prime Power Analyzer feature.

Use the PTC before you start your design to estimate the supply current for your design. The PTC provides a magnitude
estimate of the device power because these currents vary greatly with the usage of the resources.

The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you
complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

(22) The use of Power Management Bus (PMBus) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus voltage
regulator and SmartVID devices are connected via PMBus.

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I/O Pin Leakage Current

Table 13. I/O Pin Leakage Current (for GPIO Bank)

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Max Unit

II Input pin VI = 0 V to VCCIO_PIO (MAX) –360 360 µA

IOZ Tri-stated I/O pin VO = 0 V to VCCIO_PIO (MAX) –360 360 µA

Table 14. I/O Pin Leakage Current (for HPS and SDM I/O Banks)
For specification status, see the Data Sheet Status table

Symbol Description Condition Min Max Unit

II Input or tri-stated I/O pin VI, VO = 0 V 0.015 6 µA

VI, VO = VCCIO_HPS (MAX), 0.01 1 µA

VCCIO_SDM (MAX)

Bus Hold Specifications

The bus-hold trip points are based on calculated input voltages from the JEDEC* standard.

Table 15. Bus Hold Parameters (for GPIO Bank)

For specification status, see the Data Sheet Status table

Parameter Symbol Condition VCCIO_PIO (V) Unit

1.2

Min Max

Bus-hold, low, sustaining ISUSL VIN > VIL (max) 50 — µA

current

Bus-hold, high, sustaining ISUSH VIN < VIH (min) –50 — µA

current
continued...

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Parameter Symbol Condition VCCIO_PIO (V) Unit

1.2

Min Max

Bus-hold, low, overdrive IODL 0 V < VIN < VCCIO_PIO — 1,400 µA

current

Bus-hold, high, overdrive IODH 0 V < VIN < VCCIO_PIO — –1,400 µA

current

Bus-hold trip point VTRIP — 0.33 × VCCIO_PIO 0.67 × VCCIO_PIO V

OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to
the calibration block.

Table 16. OCT Calibration Accuracy Specifications (for GPIO Bank)

Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.

These specifications require RZQ reference accuracy of 240 Ω ±1%.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Calibration Accuracy Unit

34-Ω and 40-Ω RS Internal series termination with VCCIO_PIO = 1.2 ±20 %
calibration (34-Ω and 40-Ω
setting)

50-Ω and 60-Ω RT Internal parallel termination with SSTL-12 and HSTL-12 I/O –10 to +60 %
calibration (50-Ω and 60-Ω standards
setting)
POD12 I/O standard ±15 %

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OCT Without Calibration Resistance Tolerance Specifications

Table 17. OCT Without Calibration Resistance Tolerance Specifications (for GPIO Bank)

This table lists the GPIO OCT without calibration resistance tolerance to PVT changes.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Calibration Accuracy Unit

34-Ω and 40-Ω RS Internal series termination VCCIO_PIO = 1.2 –30 to +60 %
without calibration (34-Ω and
40-Ω setting)

100-Ω RD Internal differential termination VCCIO_PIO = 1.5 ±40 %

(100-Ω setting)
VCCIO_PIO = 1.2 ±40 %

Pin Capacitance

Table 18. Pin Capacitance (for GPIO Bank)

For specification status, see the Data Sheet Status table

Symbol Description Maximum Unit

CIO Input/output capacitance of I/O pins 2.6(23) pF

Internal Weak Pull-Up Resistor

All I/O pins in GPIO bank have an option to enable weak pull-up when using 1.2 V LVCMOS I/O standard. For SDM and HPS,
the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.

Table 19. Internal Weak Pull-Up Resistor Values (for GPIO Bank)
For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Min Typ Max Unit

RPU Value of the I/O pin VCCIO_PIO = 1.2 ±5% 0.5 2.5 15 kΩ
pull-up resistor before
and during
configuration, as well

(23) This value refers to die-level pin capacitance without the device package.

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Symbol Description Condition (V) Min Typ Max Unit

as user mode if you

have enabled the
programmable pull-up
resistor option.

Table 20. Internal Weak Pull-Up and Weak Pull-Down Resistor Values (for HPS and SDM I/O Banks)
For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Min Typ Max Unit

20 kΩ RPU, 20 kΩ RPD Value of the I/O pin VCCIO_SDM = 1.8 ±5%, 15 20 25 kΩ

pull-up and pull-down VCCIO_HPS = 1.8 ±5%
resistor during user
mode if you have
enabled the
programmable pull-up
or pull-down resistor
option.

50 kΩ RPU, 50 kΩ RPD Value of the I/O pin VCCIO_SDM = 1.8 ±5%, 37.5 50 62.5 kΩ
pull-up and pull-down VCCIO_HPS = 1.8 ±5%
resistor during user
mode if you have
enabled the
programmable pull-up
or pull-down resistor
option.

80 kΩ RPU, 80 kΩ RPD Value of the I/O pin VCCIO_SDM = 1.8 ±5%, 60 80 100 kΩ
pull-up and pull-down VCCIO_HPS = 1.8 ±5%
resistor during user
mode if you have
enabled the
programmable pull-up
or pull-down resistor
option.

Related Information
Agilex 7 Device Family Pin Connection Guidelines: F-Series and I-Series
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.

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Hysteresis Specifications for Schmitt Trigger Input

Table 21. Hysteresis Specifications for Schmitt Trigger Input (for HPS I/O Bank)

The devices support Schmitt trigger input on HPS I/O bank. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity,
especially for signal with slow edge rate.

For specification status, see the Data Sheet Status table

Symbol Description Condition Min Typ Max Unit

VHYS Hysteresis for Schmitt VCCIO_HPS = 1.8 V 180 250 350 mV

trigger input

I/O Standard Specifications

Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH
and IOL) for various I/O standards supported.

For minimum voltage values, use the minimum VCCIO_PIO values. For maximum voltage values, use the maximum VCCIO_PIO
values.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Related Information
Recommended Operating Conditions on page 12

Single-Ended I/O Standards Specifications

Table 22. Single-Ended I/O Standards Specifications (for GPIO Bank)

For specification status, see the Data Sheet Status table

I/O Standard VCCIO_PIO (V) VIL (V) VIH (V) VOL (V)(24) VOH (V)(24)

Min Typ Max Min Max Min Max Max Min

1.2 V LVCMOS 1.14 1.2 1.26 –0.3 0.35 × 0.65 × VCCIO_PIO + 0.3 0.25 × 0.75 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO

(24) Applicable to test condition of IOH and IOL at 2 mA.

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Table 23. Single-Ended I/O Standards Specifications (for HPS and SDM I/O Banks)
For specification status, see the Data Sheet Status table

I/O VCCIO_HPS, VCCIO_SDM (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL IOH
Standard (mA)(25) (mA)(25)

Min Typ Max Min Max Min Max Max Min Max Min

1.8 V 1.71 1.8 1.89 –0.3 0.35 × 0.65 × VCCIO_HPS + 0.4 VCCIO_HPS – 8 –8
LVCMOS VCCIO_HPS, VCCIO_HPS, 0.3, 0.4,
0.35 × 0.65 × VCCIO_SDM + VCCIO_SDM –
VCCIO_SDM VCCIO_SDM 0.3 0.4

Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications

Table 24. Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications (for GPIO Bank)
For specification status, see the Data Sheet Status table

I/O Standard VCCIO_PIO (V) VREF (V) VTT (V)

Min Typ Max Min Typ Max Min Typ Max

SSTL-12 1.14 1.2 1.26 0.49 × 0.5 × VCCIO_PIO 0.51 × 0.475 × 0.5 × VCCIO_PIO 0.525 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO

HSTL-12 1.14 1.2 1.26 0.47 × 0.5 × VCCIO_PIO 0.53 × 0.475 × 0.5 × VCCIO_PIO 0.525 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO

HSUL-12 1.14 1.2 1.26 0.49 × 0.5 × VCCIO_PIO 0.51 × — — —

VCCIO_PIO VCCIO_PIO

POD12 1.14 1.2 1.26 — Internally — — VCCIO_PIO —

calibrated

(25) To meet the IOH and IOL specifications, you must set the current strength settings accordingly. For example, to meet the 1.8 V
LVCMOS specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet
the IOH and IOL specifications in the data sheet.

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Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications

Table 25. Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications (for GPIO Bank)
For specification status, see the Data Sheet Status table

I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V)

Max Min Max Min

SSTL-12 VREF – 0.075 VREF + 0.075 VREF – 0.100 VREF + 0.100

HSTL-12 VREF – 0.080 VREF + 0.080 VREF – 0.150 VREF + 0.150

HSUL-12 VREF – 0.100 VREF + 0.100 VREF – 0.135 VREF + 0.135

POD12(26) VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070

Note: For output voltage swing calculation example, refer to the related information.

Related Information
1.2 V I/O Interface Voltage Level Compatibility section, Intel Agilex 7 General-Purpose I/O User Guide: F-Series and I-Series
Provides output voltage swing calculation examples.

(26) This specification is defined over internal Vref range from 0.6 × VCCIO_PIO to 0.92 × VCCIO_PIO.

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Differential SSTL, HSTL, and HSUL I/O Standards Specifications

Table 26. Differential SSTL, HSTL, and HSUL I/O Standards Specifications (for GPIO Bank)
For specification status, see the Data Sheet Status table

I/O VCCIO_PIO (V) VILdiff(DC) VIHdiff(DC) VILdiff(AC) VIHdiff(AC) VIX(AC) (V) VOX(AC) (V)
Standard (V) (V) (V) (V)

Min Typ Max Max Min Max Min Min Typ Max Min Typ Max

SSTL-12 1.14 1.2 1.26 –0.15 0.15 –0.2 0.2 0.5 × 0.5 × 0.5 × 0.5 × 0.5 × 0.5 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO
– 0.12 + 0.12 – 0.12 + 0.12

HSTL-12 1.14 1.2 1.26 –0.16 0.16 –0.3 0.3 0.5 × 0.5 × 0.5 × 0.5 × 0.5 × 0.5 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO
– 0.12 + 0.12 – 0.12 + 0.12

HSUL-12 1.14 1.2 1.26 –0.2 0.2 –0.27 0.27 0.5 × 0.5 × 0.5 × 0.5 × 0.5 × 0.5 ×
VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO VCCIO_PIO
– 0.12 + 0.12 – 0.12 + 0.12

Related Information
1.2 V I/O Interface Voltage Level Compatibility section, Intel Agilex 7 General-Purpose I/O User Guide: F-Series and I-Series
Provides output voltage swing calculation examples.

Differential POD I/O Standards Specifications

Table 27. Differential POD I/O Standards Specifications (for GPIO Bank)
For specification status, see the Data Sheet Status table

I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (%)(27)

Min Typ Max Max Min Max Min Max

POD12 1.14 1.2 1.26 –0.11 0.11 –0.14 0.14 25

Related Information
1.2 V I/O Interface Voltage Level Compatibility section, Intel Agilex 7 General-Purpose I/O User Guide: F-Series and I-Series
Provides output voltage swing calculation examples.

(27) Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.

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Differential I/O Standards Specifications

Table 28. Differential I/O Standards Specifications (for GPIO Bank)

For specification status, see the Data Sheet Status table

I/O VCCIO_PIO (V) VID (mV) VICM(DC) (V) VOD (V)(28) (29) VOCM (V)(28)
Standard
Min Typ Max Min Max Min Conditio Max Min Typ Max Min Typ Max
n

True 1.455 1.5 1.545 200 600 0.3 Data rate <0.9 0.247 — 0.454 0.99 1.1 1.21
Differenti ≤700
al 100 600 0.9 Mbps 1.4
Signaling
(Transmi 100 600 0.9 Data rate 1.4
tter & >700
Receiver) Mbps
(30)

True 1.14 1.2 1.26 200 600 0.3 Data rate <0.9 — — — — — —
Differenti ≤700
al 100 600 0.9 Mbps 1.1
Signaling
(Receiver 100 600 0.9 Data rate 1.1
only)(30) >700
Mbps

Switching Characteristics
This section provides the performance characteristics of core and periphery blocks.

(28) RL range: 90 ≤ RL ≤ 110 Ω.

(29) The specification is only applicable to default VOD and pre-emphasis setting.
(30) The True Differential Signaling input buffer is supported on 1.2 V and 1.5 V VCCIO_PIO bank. The maximum input voltage driven into
the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.

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Core Performance Specifications

Clock Tree Specifications

Table 29. Clock Tree Performance

For specification status, see the Data Sheet Status table

Parameter Performance Unit

–1V, –2V –3V, –3E, –4F, –4X

Programmable clock routing 1,000 780 MHz

I/O PLL Specifications

Table 30. I/O PLL Specifications

For specification status, see the Data Sheet Status table

Symbol Parameter Condition Min Typ Max Unit

fIN Input clock frequency –1V 10 — 1,100(31) MHz

–2V 10 — 900(31) MHz

–3V, –3E 10 — 750(31) MHz

–4F, –4X 10 — 650(31) MHz

fINPFD Input clock frequency — 10 — 325 MHz

to the PFD

fVCO I/O PLL VCO operating –1V 600 — 1,600 MHz

range
–2V 600 — 1,434 MHz

–3V, –3E 600 — 1,250 MHz

–4F, –4X 600 — 1,067 MHz

continued...

(31) This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard
and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

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Symbol Parameter Condition Min Typ Max Unit

fCLBW I/O PLL closed-loop I/O bank I/O PLL 0.5 — 10 MHz
bandwidth
Fabric-feeding I/O PLL 1 — 10 MHz

tEINDUTY Input clock or external — 40 — 60 %

feedback clock input
duty cycle

fOUT Output frequency for –1V — — 1,100 MHz

internal clock (C
counter) –2V — — 900 MHz

–3V, –3E — — 750 MHz

–4F, –4X — — 650 MHz

fOUT_EXT Output frequency for –1V — — 800 MHz

external clock output
–2V — — 717 MHz

–3V, –3E — — 625 MHz

–4F, –4X — — 500 MHz

tOUTDUTY Duty cycle for fOUT_EXT < 300 MHz 45 50 55 %

dedicated external
fOUT_EXT ≥ 300 MHz 40/45 (32) 50 55 (32)/60 %
clock output (when set
to 50%)

tFCOMP (33) External feedback — — — 5 ns

clock compensation
time

fDYCONFIGCLK Dynamic configuration — — — 100 MHz

clock for mgmt_clk

tLOCK Time required to lock — — — 1 ms

from end-of-device
configuration or
deassertion of areset
continued...

(32)
To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to
the related information for the detail design guidelines.
(33) Not applicable for fabric-feeding I/O PLL.

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Symbol Parameter Condition Min Typ Max Unit

tDLOCK Time required to lock — — — 1 ms

dynamically (after
switchover or
reconfiguring any non-
post-scale counters/
delays)

tPLL_PSERR Accuracy of PLL phase — — — ±50 ps

shift

tARESET Minimum pulse width — 10 — — ns

on the areset signal

tINCCJ Input clock cycle-to- fREF < 100 MHz (34) — — 750 ps (p-p)
cyle jitter
fREF ≥ 100 MHz (34) — — 0.15 UI (p-p)

tREFPJ Reference phase jitter Carrier frequency: 100 — — 1.42 ps

(rms)(35) MHz with integrated
bandwidth of 10 kHz
to 50 MHz

tREFPN Reference phase 10 Hz — — –90 dBc/Hz

noise(36) (35)
100 Hz — — –100 dBc/Hz

1 kHz — — –110 dBc/Hz

10 kHz — — –120 dBc/Hz

100 kHz — — –130 dBc/Hz

1 MHz — — –138 dBc/Hz

10 MHz — — –142 dBc/Hz

continued...

(34) fREF is fIN/N, specification applies when N = 1.

(35) Requirement for Advanced Interface Bus (AIB), High Bandwidth Memory (HBM) Interface, Mobile Industry Processor Interface (MIPI),
DDR4 protocol, and LVDS applications only.
(36) The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 100
MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK
phase noise at 100 MHz + (20 × log10 (f/100)).

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Symbol Parameter Condition Min Typ Max Unit

100 MHz — — –144 dBc/Hz

tOUTPJ_DC (33) (37) Period jitter for fOUT < 100 MHz (34) — — 17.5 mUI (p-p)
dedicated clock output
fOUT ≥ 100 MHz (34) — — 175 ps (p-p)

tOUTCCJ_DC (33) (37) Cycle-to-cycle jitter fOUT < 100 MHz (34) — — 17.5 mUI (p-p)
for dedicated clock
fOUT ≥ 100 MHz (34) — — 175 ps (p-p)
output

tOUTPJ_IO (38) (37) Period jitter for clock fOUT < 100 MHz (34) — — 60 mUI (p-p)
output on the regular
fOUT ≥ 100 MHz (34) — — 600 ps (p-p)
I/O

tOUTCCJ_IO (38) (37) Cycle-to-cycle jitter fOUT < 100 MHz (34) — — 60 mUI (p-p)
for clock output on the
fOUT ≥ 100 MHz (34) — — 600 ps (p-p)
regular I/O

tCASC_OUTPJ_DC (33) Period jitter for fOUT < 100 MHz (34) — — 17.5 mUI (p-p)
dedicated clock output
fOUT ≥ 100 MHz (34) — — 175 ps (p-p)
in cascaded PLLs

Related Information
• Memory Output Clock Jitter Specifications on page 48
Provides more information about the external memory interface clock output jitter specifications.
• Agilex 7 Clocking and PLL User Guide: F-Series and I-Series
Provides the recommended spread-spectrum clock profile and design guidelines to achieve 5% duty cycle using the
LVDS SERDES Intel FPGA IP.

(37) This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend
on the spread-spectrum clock profile used. Refer to the related information for the recommended spread-spectrum clock profile.
(38) External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory
Output Clock Jitter Specifications table.

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DSP Block Specifications

Table 31. DSP Block Performance Specifications

For specification status, see the Data Sheet Status table

Mode Performance Unit

–1V –2V –3V, –3E –4F, –4X

Fixed-point 18 × 19 900 771 676 600 MHz

multiplication mode

Fixed-point 27 × 27 900 771 676 600 MHz

multiplication mode(39)

Fixed-point 18 × 19 900 771 676 600 MHz

multiplier adder mode(39)

Fixed-point 18 × 19 900 771 676 600 MHz

multiplier adder summed
with 36-bit input mode(39)

Fixed-point four 9 × 9 900 771 676 600 MHz

multiplier adder mode(39)

Fixed-point 18 × 19 900 771 676 600 MHz

systolic mode

Fixed-point 18 × 19 900 771 676 600 MHz

complex multiplication
mode

FP32 floating-point 750 579 507 475 MHz

multiplication mode

FP32 floating-point adder 750 579 507 475 MHz

or subtract mode
continued...

(39) When Chainout is enabled but systolic registers are not used, the performance specifications for the following speed grades are as
follows:
• –1V: 675 MHz
• –2V: 578 MHz
• –3V and –3E: 507 MHz
• –4F and –4X: 450 MHz

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Mode Performance Unit

–1V –2V –3V, –3E –4F, –4X

FP32 floating-point 750 579 507 475 MHz

multiplier adder or
subtract mode

FP32 floating-point 750 579 507 475 MHz

multiplier accumulate
mode

Addition or subtraction of 750 579 507 475 MHz

two FP16 floating-point
multiplication mode

Sum/sub of two FP16 750 579 507 475 MHz

multiplications with FP32
(addition/subtraction)

Sum/sub of two FP16 750 579 507 475 MHz

multiplications with
accumulation (addition/
subtraction)

FP32 floating-point 750 579 507 475 MHz

complex multiplication

FP32 floating-point vector 750 579 507 475 MHz

dot product

FP16 floating-point 750 579 507 475 MHz

complex multiplication

FP16 floating-point vector 750 579 507 475 MHz

dot product

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from
an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block
clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

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Table 32. Memory Block Performance Specifications

For specification status, see the Data Sheet Status table

Memory Mode Performance Unit

–1V –2V –3V, –3E –4F, –4X

MLAB Single-port RAM/ROM 1,000 782 667 600 MHz

Simple dual-port RAM

Simple dual-port RAM 630 510 460 330 MHz

with read-during-write
option

M20K Block(40) Single-port RAM/ROM 1,000 (HS) 782 (HS) 667 (HS) 600 (HS) MHz
Simple dual-port RAM 850 (LP) 664 (LP) 567 (LP) 510 (LP)

Simple dual-port RAM, 1,000 (HS) 782 (HS) 667 (HS) 600 (HS) MHz
coherent read enabled 850 (LP) 664 (LP) 567 (LP) 510 (LP)

Single-port RAM with 800 (HS) 640 (HS) 560 (HS) 480 (HS) MHz
the read-during-write 680 (LP) 540 (LP) 476 (LP) 410 (LP)
option set to Old Data
Simple dual-port RAM
with the read-during-
write option set to Old
Data

Simple dual-port RAM 600 (HS) 480 (HS) 420 (HS) 360 (HS) MHz
with ECC enabled, 512 500 (LP) 400 (LP) 357 (LP) 300 (LP)
× 32

Simple dual-port RAM 1,000 (HS) 782 (HS) 667 (HS) 600 (HS) MHz
with ECC, optional 850 (LP) 664 (LP) 567 (LP) 510 (LP)
pipeline registers
enabled, 512 × 32

Dual-port ROM 600 (HS) 500 (HS) 420 (HS) 360 (HS) MHz
True dual-port RAM

Simple quad-port RAM 600 (HS) 500 (HS) 420 (HS) 360 (HS) MHz

eSRAM Simple dual-port 750 640 500 500 MHz

(40) For M20K block, timing/power optimization feature is available. The available options are High Speed (HS) and Low Power (LP). For
details on this timing/power optimization feature, refer to the related information.

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Related Information
Agilex 7 Embedded Memory User Guide
Provides details on M20K block timing/power optimization feature.

Local Temperature Sensor Specifications

Table 33. Local Temperature Sensor Specifications

For specification status, see the Data Sheet Status table

Description Temperature Range Accuracy Sampling Rate(41) Conversion Time

Local Temperature Sensor –40 to 125°C(42) ±5°C 1 KSPS < 1 ms

Remote Temperature Diode Specifications

Note the following for the remote temperature diode specifications:

• The temperature diode characteristics in this table target for three-currents temperature sensing chip implementation.
The characteristics can also apply to two-currents temperature sensing chip implementation.
• Absolute accuracy is dependent on third-party external diode ADC and integration specifics.

Table 34. Remote Temperature Diode Specifications (Core Fabric TSD)

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Ibias, diode source current 10 — 170 μA

Vbias, voltage across diode 0.43 — 0.75 V

Series resistance — — <3 Ω

Diode ideality factor — 1.006(43) — —

(41) The read out is subject to the SDM mailbox activity status.
(42) Temperature range refers to junction temperature.
(43) When using lower injection current (two-currents) implementation, the ideality factor is 1.009.

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Table 35. Remote Temperature Diode Specifications (E-Tile TSD)

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Ibias, diode source current 10 — 170 μA

Vbias, voltage across diode 0.56 — 0.82 V

Series resistance — — <2 Ω

Diode ideality factor — 1.005 — —

Table 36. Remote Temperature Diode Specifications (P-Tile TSD)

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Ibias, diode source current 10 — 170 μA

Vbias, voltage across diode 0.56 — 0.87 V

Series resistance — — <10 Ω

Diode ideality factor — 1.0108(44) — —

Table 37. Remote Temperature Diode Specifications (R-Tile TSD)

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Ibias, diode source current 20 — 170 μA

Vbias, voltage across diode 0.5 — 0.78 V

Series resistance — — <10 Ω

Diode ideality factor — 1.000(45) — —

(44) When using lower injection current (two-currents) implementation, the ideality factor is 1.03.
(45) When using lower injection current (two-currents) implementation, the ideality factor is 1.008.

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Table 38. Remote Temperature Diode Specifications (F-Tile TSD)

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Ibias, diode source current 20 — 170 μA

Vbias, voltage across diode 0.5 — 0.78 V

Series resistance — — <10 Ω

Diode ideality factor — 1.002(46) — —

Voltage Sensor Specifications

Table 39. Voltage Sensor Specifications

For specification status, see the Data Sheet Status table

Parameter Minimum Typical Maximum Unit

Resolution — 7 — Bit

Sampling rate(47) — — 1 KSPS

Input capacitance — — 40 pF

Voltage sensor accuracy, Vin range: 0 V to 1.1 V(48) — — ±3.5 %

Unipolar Input Mode Input signal range for — — 1.35 V

Vsigp

Common mode voltage on — — 0.25 V

Vsign

Input signal range for — — 1.1 V

Vsigp – Vsign

(46) When using lower injection current (two-currents) implementation, the ideality factor is 1.016.
(47) The read out is subject to the SDM mailbox activity status.
(48) For 1.8 V channel 3, 4, 5, and 9, the accuracy is ±4.5%.

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Periphery Performance Specifications

This section describes the periphery performance, LVDS SERDES, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and
perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable
frequency in your system.

LVDS SERDES Specifications

Table 40. LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 3 to 10.

DDR registers support SERDES factor J = 1 to 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table

Paramet Symbol Conditio –1 Speed Grade –2 Speed Grade –3 Speed Grade –4 Speed Grade Unit
er n
Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Clock fHSCLK_in Clock 10 — 800 10 — 700 10 — 625 10 — 625 MHz

frequen (input boost
cy clock factor W
frequen = 1 to
cy) True 40(49)
Differen
tial I/O
Standar
ds

fHSCLK_in Clock 10 — 625 10 — 625 10 — 525 10 — 525 MHz

(input boost
clock factor W
frequen = 1 to
cy) 40(49)
Single-
Ended
continued...

(49) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

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Paramet Symbol Conditio –1 Speed Grade –2 Speed Grade –3 Speed Grade –4 Speed Grade Unit
er n
Min Typ Max Min Typ Max Min Typ Max Min Typ Max

I/O
Standar
ds

fHSCLK_O — — — 800(50) — — 700(50) — — 625(50) — — 625(50) MHz

UT
(output
clock
frequen
cy)

Transmit True SERDES 150 — 1,600 150 — 1,434 150 — 1,250 150 — 1,000 Mbps
ter Differen factor J
tial I/O = 4 to
Standar 10(52)
ds - (53) (54)

fHSDR
(data SERDES 150 — 1,200 150 — 1,076 150 — 938 150 — 600 Mbps
rate)(51) factor J
= 3(52)
(53) (54)

continued...

(50) This is achieved by using the PHY clock network.

(51) Requires package skew compensation with PCB trace length.
(52) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain
which is design dependent and requires timing analysis.
(53) The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
(54) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource that you
use. The I/O differential buffer and serializer do not have a minimum toggle rate.

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Paramet Symbol Conditio –1 Speed Grade –2 Speed Grade –3 Speed Grade –4 Speed Grade Unit
er n
Min Typ Max Min Typ Max Min Typ Max Min Typ Max

SERDES 150 — 840(55) 150 — (55) 150 — (55) 150 — (55) Mbps
factor J
= 2,
uses
DDR
register
s

SERDES 150 — 420(55) 150 — (55) 150 — (55) 150 — (55) Mbps
factor J
= 1,
uses
DDR
register
s

tx Jitter - Total ≤1,600 Mbps: 160 ≤1,434 Mbps: 200 ≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ps
True jitter for ≤1,434 Mbps: 200 ≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320
Differen data
≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340
tial I/O rate,
Standar 600 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340
ds Mbps – ≤800 Mbps: 320 600 Mbps: 340
1.6 600 Mbps: 340
Gbps

Total — — 0.21 — — 0.21 — — 0.21 — — 0.21 UI

jitter for
data
rate, <
600
Mbps

tDUTY TX 45 50 55 45 50 55 45 50 55 45 50 55 %
(56) output
clock
duty
cycle for
continued...

(55) The maximum ideal data rate is the SERDES factor (J) × the PLL maximum output frequency (fOUT) provided you can close the design
timing and the signal integrity meets the interface requirements.
(56) Not applicable for DIVCLK = 1.

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Paramet Symbol Conditio –1 Speed Grade –2 Speed Grade –3 Speed Grade –4 Speed Grade Unit
er n
Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Differen
tial I/O
Standar
ds

tRISE & True — — 160 — — 180 — — 200 — — 220 ps

tFALL (53) Differen
(57) tial I/O
Standar
ds

TCCS (51) True — — 330 — — 330 — — 330 — — 330 ps

(56) Differen
tial I/O
Standar
ds

Receiver True SERDES 150 — 1,600 150 — 1,434 150 — 1,250 150 — 1,000 Mbps
Differen factor J
tial I/O = 4 to
Standar 10(52)
ds - (53) (54)

fHSDRDPA
(data SERDES 150 — 1,200 150 — 1,076 150 — 938 150 — 600 Mbps
rate) factor J
= 3(52)
(53) (54)

fHSDR SERDES (54) — (58) (54) — (58) (54) — (58) (54) — (58) Mbps
(data factor J
rate) = 3 to
(without 10
DPA)(51)
SERDES (54) — (55) (54) — (55) (54) — (55) (54) — (55) Mbps
factor J
= 2,
uses
continued...

(57) This applies to default pre-emphasis and VOD settings only.

(58) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider
the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

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Paramet Symbol Conditio –1 Speed Grade –2 Speed Grade –3 Speed Grade –4 Speed Grade Unit
er n
Min Typ Max Min Typ Max Min Typ Max Min Typ Max

DDR
register
s

SERDES (54) — (55) (54) — (55) (54) — (55) (54) — (55) Mbps
factor J
= 1,
uses
DDR
register
s

DPA DPA run — — — 10,000 — — 10,000 — — 10,000 — — 10,000 UI

(FIFO length
mode)

DPA DPA run SGMII/ — — 5 — — 5 — — 5 — — 5 UI

(soft length GbE
CDR protocol
mode)
All other — — 50 data — — 50 data — — 50 data — — 50 data —
protocol transitio transitio transitio transitio
s n per n per n per n per
208 UI 208 UI 208 UI 208 UI

Soft Soft- — –300 — 300 –300 — 300 –300 — 300 –300 — 300 ppm
CDR CDR
mode ppm
toleranc
e

Non Samplin — — — 330 — — 330 — — 330 — — 330 ps

DPA g
mode Window

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DPA Lock Time Specifications

Table 41. DPA Lock Time Specifications

The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1- to-0 transition.

For specification status, see the Data Sheet Status table

Standard Training Pattern Number of Data Transitions in Number of Repetitions per Maximum Data Transition
One Repetition of the Training 256 Data Transitions(59)
Pattern

SPI-4 00000000001111111111 2 128 768

Parallel Rapid I/O 00001111 2 128 768

10010000 4 64 768

Miscellaneous 10101010 8 32 768

01010101 8 32 768

(59) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

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LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications

Figure 2. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps

25

8.5

Jitter Amplitude(UI)
0.22

0.1

F1 F2 F3 F4
Jitter Frequency (Hz)

Table 42. LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps
For specification status, see the Data Sheet Status table

Parameter Jitter Frequency (Hz) Sinusoidal Jitter (UI)

F1 10,000 25

F2 17,565 25

F3 1,493,000 0.22

F4 50,000,000 0.22

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Figure 3. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps
Sinusoidal Jitter Amplitude

20db/dec

0.1 UI
P-P
Frequency
baud/1667 20 MHz

Memory Standards Supported

Table 43. Memory Standards Supported

This table lists the overall capability of External Memory Interface supported. For specific details, refer to the External Memory Interface Spec Estimator.

For specification status, see the Data Sheet Status table

Memory Standard Controller Type Maximum Frequency (MHz)

DDR4 SDRAM Hard memory controller 1,600

QDR IV SRAM Soft memory controller 1,066

DDR4 SDRAM HPS hard memory controller 1,600

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Related Information
External Memory Interface Spec Estimator
Provides the specific details of the memory standards supported.

DLL Range Specifications

Table 44. DLL Frequency Range Specifications

For specification status, see the Data Sheet Status table

Parameter Performance (for All Speed Grades) Unit

DLL operating frequency range 600 – 1,600 MHz

DLL reference clock input Minimum 600 MHz

Memory Output Clock Jitter Specifications

The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential
signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel
recommends using PHY clock networks for better jitter performance.

The memory clock output jitter is within the JEDEC specifications when the phase jitter (integration bandwidth 10 kHz to 50
MHz) of the input clock is not more than 20 ps peak-to-peak, or 1.42 ps RMS at 1e-12 BER and 1.22 ps at 1e-16 BER.

E-Tile Transceiver Performance Specifications

This section provides E-tile transceiver specifications and timing.

E-Tile Transceiver Performance

Table 45. E-Tile Transmitter and Receiver Data Rate Performance Specifications
For specification status, see the Data Sheet Status table

Symbol/Description Condition Transceiver Speed Grade Unit

–1 –2 –3

Supported data rate(60) NRZ 28.9 28.3 17.4 Gbps

PAM4 57.8(61) 56 32 Gbps

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E-Tile Transceiver Reference Clock Specifications

Table 46. E-Tile Reference Clock LVPECL DC Electrical Characteristics

For specification status, see the Data Sheet Status table

Symbol Refclk Parameter Min Typ Max Unit

VTT Termination voltage (2.5 V 0.4 0.5 0.6 V

compliant)

Termination voltage (3.3 V 1.04 1.3 1.56 V

compliant)

RTT Termination resistor 40 50 60 Ω

VDIFF Differential voltage 0.4 0.8 1.2 V

VCM Input common mode VDIFF/2 — VCCCLK_GXE – VDIFF/2 V

voltage (2.5 V compliant,
no internal termination
resistor)

Input common mode VCCCLK_GXE – 1.6 VCCCLK_GXE – 1.3 VCCCLK_GXE – 1.0 V

voltage (2.5 V compliant,
internal termination
resistor)

Input common mode VDIFF/2 — VCCCLK_GXE – VDIFF/2 V

voltage (3.3 V compliant,
no internal termination
resistor)

Input common mode 1.4 2 2.6 V

voltage (3.3 V compliant,
internal termination
resistor)

(60) The supported data rate is for chip-to-chip and backplane links.
(61) Two channels are combined to support up to 57.8 Gbps.

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Table 47. E-Tile Reference Clock Electrical and Jitter Requirements

For specification status, see the Data Sheet Status table

Parameter Condition Min Typ Max Unit

Frequency — 125 156.25 700 MHz

Frequency tolerance — –100 — 100 ppm

Clock duty cycle — 45 50 55 %

Rise/Fall times 20% to 80% 40 — 300 ps

Phase jitter 12 kHz to 20 MHz — 0.375 0.5 ps rms

Phase noise(62) 10 kHz — — –130 dBc/Hz

100 kHz — — –138 dBc/Hz

500 kHz — — –138 dBc/Hz

3 MHz — — –140 dBc/Hz

10 MHz — — –144 dBc/Hz

20 MHz — — –146 dBc/Hz

E-Tile Transmitter Specifications

Table 48. E-Tile Transmitter Specifications

For specification status, see the Data Sheet Status table

Symbol/Description Condition Min Typ Max Unit

Transmitter differential No precursor/postcursor — 0.965 — V

output voltage peak-to- de-emphasis
peak

Transmitter common mode — VCCRT_GXE/2 V

voltage

(62) The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 156.25
MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK
phase noise at 156.25 MHz + 20*log10(f/156.25).

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E-Tile Receiver Specifications

Table 49. E-Tile Receiver Specifications

For specification status, see the Data Sheet Status table

Symbol/Description Condition Min Typ Max Unit

Absolute VMAX for a NRZ — VCCH_GXE + 0.3 — V

receiver pin
PAM4 — VCCH_GXE — V

Maximum peak-to-peak — 1.2 V

differential input voltage
VID (diff p-p) before/after
device configuration

VCM (Internal AC NRZ GND — VCCH_GXE V

coupled)(63)
PAM4 GND + 0.3 — VCCH_GXE – 0.3 V

Receiver run length(64) — — — 100(65) symbols

DC input impedance — 40 — 60 Ω

DC differential input — 80 100 120 Ω

impedance

Powered down DC input Receiver pin impedance 100k — — Ω

impedance when the receiver
termination is powered
down

Differential termination From DC to 100 MHz 80 100 120 Ω

PPM tolerance Allowed frequency — — 750 ppm

mismatch between
REFCLK and RX data

(63) This value uses internal AC coupling. External coupling capacitors are required beyond the range mentioned in this table.
(64) No additional transition density requirements apply.
(65) The incoming data must be statistically DC-balanced.

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P-Tile Transceiver Performance Specifications

This section provides P-tile transceiver specifications and timing.

P-Tile Transceiver Performance

Table 50. P-Tile Transmitter and Receiver Data Rate Performance

For specification status, see the Data Sheet Status table

Symbol/Description Condition Gen 1 Gen 2 Gen 3 Gen 4 Unit

Supported data rate PCIe* 2.5 5 8 16 Gbps

Table 51. P-Tile PLLA Performance

For specification status, see the Data Sheet Status table

Symbol/Description Condition Transceiver Speed Grade Unit

Min Typ Max

VCO frequency — — 5 — GHz

PLL bandwidth (BWTX- PCIe 2.5 GT/s 1.5 — 22 MHz

PKG_PLL1)(66)
PCIe 5.0 GT/s 8 — 16 MHz

PLL bandwidth (BWTX- PCIe 5.0 GT/s 5 — 16 MHz

PKG_PLL2)(66)

PLL peaking (PKGTX-PLL1) PCIe 2.5 GT/s — — 3 dB

PCIe 5.0 GT/s — — 3 dB

PLL peaking (PKGTX- PCIe 5.0 GT/s 1 — — dB

PLL2)(66)

(66) The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value
in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at
the point where its transfer function crosses the –3 dB point.

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Table 52. P-Tile PLLB Performance

For specification status, see the Data Sheet Status table

Symbol/Description Condition Transceiver Speed Grade Unit

Min Typ Max

VCO frequency — — 8 — GHz

PLL bandwidth (BWTX- PCIe 8.0 GT/s 2 — 4 MHz

PKG_PLL1)(67)
PCIe 16.0 GT/s 2 — 4 MHz

PLL bandwidth (BWTX- PCIe 8.0 GT/s 2 — 5 MHz

PKG_PLL2)(67)
PCIe 16.0 GT/s 2 — 5 MHz

PLL peaking (PKGTX- PCIe 8.0 GT/s — — 2 dB

PLL1)(67)
PCIe 16.0 GT/s — — 2 dB

PLL peaking (PKGTX- PCIe 8.0 GT/s — — 1 dB

PLL2)(67)
PCIe 16.0 GT/s — — 1 dB

P-Tile Transceiver Reference Clock Specifications

Table 53. P-Tile Reference Clock Specifications

For specification status, see the Data Sheet Status table

Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

Supported I/O standards — HCSL —

Input reference clock — 99.97 100 100.03 MHz

frequency(68)
continued...

(67) The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value
in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at
the point where its transfer function crosses the –3 dB point.

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Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

Rising edge rate(69) PCIe 0.6 — 4 V/ns

Falling edge rate(69) PCIe 0.6 — 4 V/ns

Duty cycle PCIe 40 — 60 %

Spread-spectrum — 30 — 33 kHz
modulating clock
frequency

Spread-spectrum — –0.5 — 0 %
downspread

Absolute VMAX — — — 1.15 V

Absolute VMIN — — — –0.3 V

Peak-to-peak differential — 300 — 1,500 mV

input voltage

VICM (DC coupled) HCSL I/O standard for 250 — 550 mV

PCIe reference clock

Cycle to cycle jitter PCIe — — 150 ps

(TCCJITTER)(70)

TSSC-MAX-PERIOD-SLEW Max SSC df/dt — — 1,250 ppm/μs

Related Information
• PCI Express Base Specification Revision 3.0
• PCI Express Base Specification Revision 4.0

(68) This number is with spread spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications
in Section 8.6.3 Data Rate Independent Refclk Parameters in the PCI Express* Base Specification Revision 4.0.
(69) Measured from –150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential
zero crossing.
(70) For common reference clock architecture, follow the jitter limit specified in the PCI Express* Card Electromechanical Specification for
2.5 GT/s, Section 4.3.7 Refclk Specifications for 5.0 GT/s and Section 4.3.8 Refclk Specifications for 8.0 GT/s in the PCI Express Base
Specification Revision 3.0, and Section 8.6 Refclk Specifications for 16.0 GT/s in the PCI Express Base Specification Revision 4.0.

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P-Tile Transmitter Specifications

Table 54. P-Tile Transmitter Specifications

For specification status, see the Data Sheet Status table

Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

Supported I/O standards PCIe High Speed Differential I/O —

Differential on-chip PCIe 80 — 120 Ω

termination resistors

Differential peak-to-peak PCIe 2.5 GT/s 800 — 1,100 mV

voltage for full swing
PCIe 5.0 GT/s 800 — 1,100 mV

PCIe 8.0 GT/s 800 — 1,100 mV

PCIe 16.0 GT/s 800 — 1,100 mV

Differential peak-to-peak PCIe 8.0 GT/s and 16.0 250 — — mV

voltage during EIEOS GT/s

Lane-to-lane output skew PCIe 2.5 GT/s — — 2.5 ns

PCIe 5.0 GT/s — — 2 ns

PCIe 8.0 GT/s — — 1.5 ns

PCIe 16.0 GT/s — — 1.25 ns

P-Tile Receiver Specifications

Table 55. P-Tile Receiver Specifications

For specification status, see the Data Sheet Status table

Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

Supported I/O standards PCIe High Speed Differential I/O —

Peak-to-peak differential PCIe 2.5 GT/s(71) 175(72) — 1,200 mV

input voltage VID (diff p-p)
PCIe 5.0 GT/s(71) 100(72) — 1,200 mV
continued...

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Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

PCIe 8.0 GT/s 25(72) — —(73) mV

PCIe 16.0 GT/s 15(72) — —(73) mV

Differential on-chip — 80 — 120 Ω

termination resistors

RESREF(74) — 167.3 169 170.7 Ω

RREF — 2.772 2.8 2.828 kΩ

Related Information
PCI Express Base Specification Revision 4.0

(71) Voltage shown for PCIe 2.5 GT/s and 5.0 GT/s are at the package pins (TP2).
(72) For PCIe at 2.5 GT/s and 5 GT/s, the VID is measured at TP2, which is the accessible test point at the device under test. For PCIe 8.0
GT/s and 16.0 GT/s, the VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx
package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
(73) The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe Express Base
Specification Rev. 4.0 for the generator (TX) launch voltage value.
(74) Connecting RESREF at 169 Ω calibrates PCIe channel on-chip termination to 85 Ω.

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R-Tile Transceiver Performance Specifications

R-Tile Transceiver Performance

Table 56. R-Tile Transmitter and Receiver Data Rate Performance

For specification status, see the Data Sheet Status table

Symbol/Description Condition Transceiver Speed Grade Unit

–1 –2

Supported data rate PCIe 2.5, 5, 8, 16, 32 2.5, 5, 8, 16, 32 Gbps

CXL 8, 16, 32 — Gbps

Table 57. R-Tile Slow PLL Performance

For specification status, see the Data Sheet Status table

Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

VCO frequency PCIe — 10 — GHz

CXL — — — GHz

PLL bandwidth (BWTX- PCIe 2.5 GT/s 1.5 — 22 MHz

PKG_PLL1)(75)
PCIe 5.0 GT/s 8 — 16 MHz

PLL bandwidth BWTX- PCIe 2.5 GT/s — — — MHz

PKG_PLL2)(75)
PCIe 5.0 GT/s 5 — 16 MHz

PLL peaking (PKGTX- PCIe 2.5 GT/s — — 3 dB

PLL1)(75)
PCIe 5.0 GT/s — — 3 dB

PLL peaking (PKGTX- PCIe 2.5 GT/s — — — dB

PLL2)(75)
PCIe 5.0 GT/s 1 — — dB

(75) The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value
in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at
the point where its transfer function crosses the –3 dB point.

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Table 58. R-Tile Fast PLL Performance

For specification status, see the Data Sheet Status table

Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

VCO frequency PCIe — 16 — GHz

CXL — 16 — GHz

PLL bandwidth (BWTX- PCIe 8.0 GT/s 0.5 — 4 MHz

PKG_PLL1)(76)
PCIe 16.0 GT/s 0.5 — 4 MHz

PCIe 32.0 GT/s 0.5 — 1.8 MHz

CXL 8.0 GT/s 0.5 — 4 MHz

CXL 16.0 GT/s 0.5 — 4 MHz

CXL 32.0 GT/s 0.5 — 1.8 MHz

PLL bandwidth (BWTX- PCIe 8.0 GT/s 0.5 — 5 MHz

PKG_PLL2)(76)
PCIe 16.0 GT/s 0.5 — 5 MHz

PCIe 32.0 GT/s — — — —

CXL 8.0 GT/s 0.5 — 5 MHz

CXL 16.0 GT/s 0.5 — 5 MHz

CXL 32.0 GT/s — — — —

PLL peaking (PKGTX- PCIe 8.0 GT/s — — 2 dB

PLL1)(76)
PCIe 16.0 GT/s — — 2 dB

PCIe 32.0 GT/s — — 2 dB

CXL 8.0 GT/s — — 2 dB

CXL 16.0 GT/s — — 2 dB

continued...

(76) The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value
in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at
the point where its transfer function crosses the –3 dB point.

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Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

CXL 32.0 GT/s — — 2 dB

PLL peaking (PKGTX- PCIe 8.0 GT/s — — 1 dB

PLL2)(76)
PCIe 16.0 GT/s — — 1 dB

PCIe 32.0 GT/s — — — —

CXL 8.0 GT/s — — 1 dB

CXL 16.0 GT/s — — 1 dB

CXL 32.0 GT/s — — — —

R-Tile Transceiver Reference Clock Specifications

Table 59. R-Tile Reference Clock Specifications

For specification status, see the Data Sheet Status table

Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

Supported I/O standards PCIe HCSL —

CXL HCSL —

Refclk frequency for PCIe 99.99 100 100.01 MHz

devices that support 32.0
GT/s(77) CXL 99.99 100 100.01 MHz

Rising edge rate(78) PCIe 0.6 — 4 V/ns

CXL 0.6 — 4 V/ns

continued...

(77) This number is with spread-spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications
in Section 8.6 Refclk Specifications of PCI Express Base Specification Revision 5.0 Version 1.0.
(78) Measured from –150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential
zero crossing.

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Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

Falling edge rate(78) PCIe 0.6 — 4 V/ns

CXL 0.6 — 4 V/ns

Duty cycle PCIe 40 — 60 %

CXL 40 — 60 %

Absolute VMAX PCIe — — 1.15 V

CXL — — 1.15 V

Absolute VMIN PCIe — — –0.3 V

CXL — — –0.3 V

Peak-to-peak differential PCIe 300 — 1,450 mV

input voltage
CXL 300 — 1,450 mV

Vcross PCIe 250 — 550 mV

CXL 250 — 550 mV

Cycle-to-cycle jitter PCIe — — 150 ps

(TCCJITTER)(79)
CXL — — 150 ps

Spread-spectrum PCIe 30 — 33 kHz

modulating clock
frequency CXL 30 — 33 kHz

SSC deviation for devices PCIe –0.3 — 0 %

that support 32.0 GT/s
and SRIS when operating CXL –0.3 — 0 %
in SRIS mode at all speeds

TSSC-MAX-PERIOD-SLEW Max SSC df/dt for PCIe — — 1,250 ppm/µs

Max SSC df/dt for CXL — — 1,250 ppm/µs

(79) For common reference clock architecture, you must meet the jitter limit specified in Section 8.6 Refclk Specifications of PCI Express
Base Specification Revision 5.0 Version 1.0.

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Related Information
PCI Express Base Specification Revision 5.0

R-Tile Transmitter Specifications

Table 60. R-Tile Transmitter Specifications

For specification status, see the Data Sheet Status table

Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

Supported I/O standards PCIe High-Speed Differential I/O —

CXL High-Speed Differential I/O —

Differential on-chip PCIe (80) 80 100 120 Ω

termination resistors
CXL(80) 80 100 120 Ω

Differential peak-to-peak PCIe 2.5 GT/s 800 — 1,200 mV

voltage for full swing
PCIe 5.0 GT/s 800 — 1,200 mV

PCIe 8.0 GT/s 800 — 1,300 mV

PCIe 16.0 GT/s 800 — 1,300 mV

PCIe 32.0 GT/s 800 — 1,300 mV

CXL 8.0 GT/s 800 — 1,300 mV

CXL 16.0 GT/s 800 — 1,300 mV

CXL 32.0 GT/s 800 — 1,300 mV

Differential peak-to-peak PCIe 8.0 GT/s, 16.0 GT/s, 250 — — mV

voltage during EIEOS and 32.0 GT/s

CXL 8.0 GT/s, 16.0 GT/s, 250 — — mV

and 32.0 GT/s

Lane-to-lane output skew PCIe 2.5 GT/s — — 2.5 ns

continued...

(80) 100ohms (Typical) aligned to Base spec.

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Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

PCIe 5.0 GT/s — — 2 ns

PCIe 8.0 GT/s — — 1.5 ns

PCIe 16.0 GT/s — — 1.25 ns

PCIe 32.0 GT/s — — 1.25 ns

CXL 8.0 GT/s — — 1.5 ns

CXL 16.0 GT/s — — 1.25 ns

CXL 32.0 GT/s — — 1.25 ns

R-Tile Receiver Specifications

Table 61. R-Tile Receiver Specifications

For specification status, see the Data Sheet Status table

Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

Supported I/O standards PCIe High-Speed Differential I/O —

CXL High-Speed Differential I/O —

Peak-to-peak differential PCIe 2.5 GT/s(81) 175 — 1,200 mVPP

input voltage VID (diff p-p)
PCIe 5.0 GT/s(81) 100 — 1,200 mVPP

PCIe 8.0 GT/s(81) 25 — 1,200 mVPP

PCIe 16.0 GT/s(81) 15 — 800 mVPP

PCIe 32.0 GT/s(81) 15 — 800 mVPP

continued...

(81) For PCIe at 2.5 GT/s and 5 GT/s, VID is measured at TP2, which is the accessible test point at the device under test. For PCIe and CXL
8.0 GT/s, 16.0 GT/s and 32.0 GT/s, VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the
behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can
be defined.

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Symbol/Description Condition All Transceiver Speed Grades Unit

Min Typ Max

CXL 8.0 GT/s(81) 25 — 1,200 mVPP

CXL 16.0 GT/s(81) 15 — 800 mVPP

CXL 32.0 GT/s(81) 15 — 800 mVPP

Differential on-chip PCIe (82) 80 85 120 Ω

termination resistors
CXL(82) 80 85 120 Ω

RCOMP PCIe (83) 148.5 150 151.5 Ω

CXL(83) 148.5 150 151.5 Ω

F-Tile Transceiver Performance Specifications

F-Tile Transceiver Performance

Table 62. F-Tile FHT Transmitter and Receiver Data Rate Performance
For specification status, see the Data Sheet Status table

Symbol/Description Condition Transceiver Speed Grade Unit

–1 –2 –3

Supported data rate NRZ 24–29, 48–58 24–29 24–29 Gbps

PAM4 48–58, 96–116 48–58 48–58 Gbps

(82) 85ohms (Typical) aligned to Base spec.

(83) Connecting RCOMP at 150 Ω calibrates PCIe and CXL channel on-chip termination to 85 Ω (aligned to Base spec).

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Table 63. F-Tile FGT Transmitter and Receiver Data Rate Performance
For specification status, see the Data Sheet Status table

Symbol/Description Condition Transceiver Speed Grade Unit

–1 –2 –3

Supported data rate NRZ 1–32.45 1–32 1–17.4 Gbps

PAM4 20–58.125 20–58.125 20–32 Gbps

F-Tile Transceiver Reference Clock Specifications

Table 64. F-Tile FHT Reference Clock Requirements

For specification status, see the Data Sheet Status table

Parameter Description Condition Min Typical Max Unit

Frequency Reference clock — 100 156.25 200 MHz

frequency

Frequency accuracy Frequency accuracy of — — — ±100 ppm

the reference clock,
including temperature
variability, aging, and
initial variation

Single sideband phase Measured SSB phase 10 kHz — — –130 dB

noise noise must be smaller
than phase noise 100 kHz — — –138 dB
mask(84)
500 kHz — — –138 dB

3 MHz — — –140 dB

10 MHz — — –144 dB
continued...

(84) Add an offset of 20 × log10(Fclk/156.25 MHz) dB to mask values, where Fclk is reference clock frequency.

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Parameter Description Condition Min Typical Max Unit

20 MHz — — –146 dB

1 GHz — — –146 (85) dB

Integrated RMS jitter Integrated over 10 — — — 522 fs

kHz – 20 MHz, include
spurious

Table 65. F-Tile FHT Reference Clocks Input Specifications

LVDS is recommended with on-board 100 nF AC-coupling capacitor.

For specification status, see the Data Sheet Status table

Parameter Description Condition Min Typical Max Unit

TREF-DUTY Duty cycle — 45 50 55 %

TREF-RISE/FALL Rising and falling edge 20% – 80% 40 — 300 ps

rate

TREF-SINGLEEND-SKEW Skew between — — — 5 ps

REFCLKP and
REFCLKN

ZREF-SINGLEEND-DC Reference clock input — 40 50 60 Ω

impedance –
terminated mode

VREFIN-SE-PP Input reference clock — 200 — 510 mV

single-ended peak-to-
peak voltage
continued...

(85) The phase noise mask requirement between 20 MHz and 1 GHz excludes any harmonics power of the fundamental clock.

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Parameter Description Condition Min Typical Max Unit

VREFIN-CM-AC Input reference clock — Set on-chip (no user access) —

common-mode
voltage when AC-
coupled on board

VREFIN-IL-DC Input reference clock — 0.1 — — V

input low voltage
when DC-coupled on
board

VREFIN-IH-DC Input reference clock — — — 0.9 V

input high voltage
when DC-coupled on
board

Table 66. F-Tile FGT Reference Clock Input Specifications

For specification status, see the Data Sheet Status table

Parameter Description Condition Min Typical Max Unit

Supported I/O — Dedicated reference CML, HCSL

standards clock pin

FREF Reference clock — 100(86) — 380 MHz

operating frequency

TREF-DUTY Duty cycle — 45 50 55 %

TREF-RISE/FALL Rising and falling edge 20% – 80% — — 0.15 × Tref_period ps

rate

TREF-SINGLEEND-SKEW Skew between — — — 50 ps

REFCLKP and
REFCLKN
continued...

(86) This value is 100 MHz for down SSC (Spread Spectrum Clocking) clocking. This value can also be 25 MHz for HDMI rate of less than 1
Gbps.

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Parameter Description Condition Min Typical Max Unit

ZREF-DIFF-DC (87) Reference clock — 80 100 120 Ω

differential input
impedance –
terminated mode

VREFIN-DIFF (88) Input reference clock — 0.6 1.2 1.7 V

differential peak-to-
peak voltage

VREFIN-IL-DC Input reference clock — 0 — — V

input low voltage
when DC-coupled on
board

VREFIN-IH-DC Input reference clock — — — 1 V

input high voltage
when DC-coupled on
board

VREFIN-CM-AC Input reference clock — Set on-chip (no user access) V

common-mode
voltage when AC-
coupled on board

VREFIN-CM-DC Input reference clock — 0.2 — 0.8 V

common-mode
voltage when DC-
coupled on board

PNREF-SSB (156.25 Reference clock 10 kHz — — –130 dBc/Hz

MHz) measured single
sideband phase noise 100 kHz — — –138 dBc/Hz
mask including spurs
must be smaller than 500 kHz — — –138 dBc/Hz
phase noise mask(89)
3 MHz — — –140 dBc/Hz
continued...

(87) These termination resistors are part of the reference clock input buffer on-chip, and are always present and no external termination
or DC biasing is needed if AC-coupled on board. If DC-coupled on board, external biasing is not required unless a signaling standard
other than differential 100 Ω termination is required.
(88) LVDS is recommended with on-board AC-coupling and subject to 0.6 V ≤ VREFIN-DIFF ≤ 1.7 V.
(89) Add an offset of 20 × log10(Fclk/156.25 MHz) dB to mask values, where Fclk is reference clock frequency.

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Parameter Description Condition Min Typical Max Unit

10 MHz — — –144 dBc/Hz

20 MHz — — –146 dBc/Hz

1 GHz — — –146 dBc/Hz

VREFIN-RJ-RMS RMS jitter integrated — — — 522 fs

from 10 kHz – 20 MHz
including spurs

VREFIN-PPM-ERROR Reference clock — –350 + SSC — +350 + SSC ppm

frequency error

Figure 4. Simplified F-Tile FGT Reference Clock Input Buffer

Board FGT Reference Clock Receiver

Bumps
REF+

50 Ω
AC Coupled
ZREF-DIFF-DC Network

50 Ω

REF-

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Table 67. F-Tile FGT Reference Clock Output Driver Specifications

For specification status, see the Data Sheet Status table

Parameter Description Condition Min Typical Max Unit

FREF_OUT Reference clock — 25 — 800 MHz

operating frequency

TREF-DUTY_OUT Duty cycle — 45 50 55 %

TREF-RISE_OUT/FALL_OUT Rising and falling edge 20% – 80% — — 0.15 × Tref_period ps

rate

TREF-SINGLEEND-SKEW Skew between — — — 50 ps

REFCLKP and
REFCLKN

ZREF-DIFF-DC_OUT Reference clock — 80 100 120 Ω

differential output
impedance –
terminated mode

VREFIN-DIFF-AC_OUT Output reference clock — 0.9 1 1.1 V

differential peak to
peak voltage when
AC-coupled on board

VREFIN-CM-OUT (90) Output reference clock — 0.45 0.5 0.55 V

common-mode

(90)
If your far-end differential termination is comprised of two 50 Ω terminations to GND, the common-mode voltage is nominally 250 mV.
If your far-end differential termination is comprised of a single 100 Ω differential termination between the P and N signals, the
common-mode voltage is nominally 500 mV.

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F-Tile Transmitter Specifications

Table 68. F-Tile FHT Transmitter Electrical Specifications

For specification status, see the Data Sheet Status table

Parameter Symbol Description Min Typical Max Unit

Output eye VTX-DIFF-PKPK Transmit amplitude 800 — 1,200 mVdiff-pkpk

specifications (low frequency)

VTX-DEEMP_STEP Transmit tap 0.5 — 5 %

resolution for c(0),
c(1), and c(–1)

Transmit tap 0.5 — 2.5 %

resolution for c(–2)

TTX-SLEW Rise/fall time 8 — — ps

Transmitter output VTX-CM OUT Transmitter output 820 850 880 mV

voltage common-mode
voltage

Transmitter DC ZTX-DIFF-DC Transmitter output 80 100 120 Ω

impedance differential DC
impedance 100 W
mode while configured

ZTX-CM-DC Transmitter output 20 25 30 Ω

common-mode DC
impedance

Transmitter return loss ZRL-DIFF-DC Transmitter differential — — 14.5 dB

DC return loss

ZRL-DIFF-NYQ Transmitter differential — — 8 dB

return loss at Nyquist
frequency (FBAUD/2)

ZRL-CMN Transmitter common- — — 6 dB

mode return loss
below 10 GHz

Electrical idle VTX-IDLE Idle output voltage — — 50 mVpkpk

continued...

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Parameter Symbol Description Min Typical Max Unit

VCM-DELTA-SQUELCH Maximum common- — — 100 mV

mode step entering/
exiting squelch mode

TTX-IDLE-LATENCY Latency entering/ — — 28 ms

exiting idle (cold boot)

Power state cycle (re- — — 5 µs

establish CM)

Table 69. F-Tile FGT Transmitter Electrical Specifications

For specification status, see the Data Sheet Status table

Parameter Symbol Description Min Typical Max Unit

Output eye VTX-DIFF-PKPK Back-porch transmit 300 — 1,050 mV

specifications amplitude

VTX-DEEMP_STEP Transmit tap — — 2 %

resolution

DTX-N+2-DEEMP N+2 precursor tap de- 0 — 2.5 dB

emphasis

DTX-N+1-DEEMP N+1 precursor tap de- 0 — 4.5 dB

emphasis

DTX-N-1-DEEMP N-1 postcursor tap de- 0 — 6.5 dB

emphasis

TTX-SLEW Rise/fall time at 20%– 10 — 20 ps

80%

TTX-DJ Transmit deterministic — — 0.15 UIpkpk

jitter at 25 Gbps

TTX-RJ Transmit total peak- — — 0.15 UIpkpk

peak random jitter
(assumes 14σTXRJ-
RMS)(91)
continued...

(91) Assume a 1st order high-pass jitter measurement filter with a cutoff of Fbaud/Fgpll = Ngpll.

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Parameter Symbol Description Min Typical Max Unit

TTX-TJ Transmit total peak- — — 0.28 UIpkpk

peak jitter (TTX-TJ =
TTX-DDJ + TTX-PJ + TTX-
(91)
RJ)

Transmitter output VTX-CM OUT Transmitter output 0.45 0.5 0.55 V

voltage common-mode
voltage

Transmitter DC ZTX-DIFF-DC Transmitter output 80 90 120 Ω

impedance differential DC
impedance 90 Ω mode
while configured(92)

ZTX-CM-DC Transmitter output 20 25 30 Ω

common-mode DC
impedance

Transmitter return loss ZRL-DIFF-DC Transmitter differential — — 12 dB

DC return loss

ZRL-DIFF-NYQ Transmitter differential — — 6 dB

return loss at Nyquist
frequency (FBAUD/2)

ZRL-CMN Transmitter common- — — 6 dB

mode return loss
below 10 GHz

Electrical idle VTX-IDLE Idle output voltage — — 20 mV

VCM-DELTA-SQUELCH Maximum common- — — 100 mV

mode step entering/
exiting squelch mode

TTX-IDLE-LATENCY Latency entering/ — — 8 µs

exiting idle (cold
boot), power state
cycle (re-establish
CM)
continued...

(92) TX pins are driven to 0 V before mode configuration.

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Parameter Symbol Description Min Typical Max Unit

Receiver detect VTX-RCV-DETECT Voltage change — — 600 mV

allowed during
receiver detection

Lane-to-lane output — Lane count ≤ 8 — — 2 UI + 200 ps ps

skew
— Lane count = 16 — — 2 UI + 300 ps ps

F-Tile Receiver Specifications

Table 70. F-Tile FHT Receiver Electrical Specifications

For specification status, see the Data Sheet Status table

Parameter Symbol Description Min Typical Max Unit

Receiver input eye VRX-DIFF-PKPK Receiver input Closed eye — 1,200 mVdiff-pkpk
specifications differential peak-to-
peak voltage(93)

VRX-CM-DC Receiver input DC 100 — 900 mV

common-mode
voltage(94) (93)
continued...

(93) To support Hot Swap with FHT PMA’s, ensure the following:
For AC Coupled connections:
• RX inputs have external AC coupling caps of at least 100nF.
• The single-ended voltages applied to the RX_p and RX_n pins should not exceed ±300mV (for a total of 600mV p-p).
• The total differential voltage (combination of RX_p/RX_n) should not exceed 1,200mV.
• The FHT RX Analog Parameter selection for External AC cap must be EXTERNAL_AC_CAP_ENABLE.
For DC Coupled connections:
• The maximum amount of time that the unpowered FHT RX PMA can be DC coupled to a link partner who is transmitting is 40
minutes. If you cannot meet this requirement, contact Altera Customer Support.
• The single-ended voltages applied to the RX_p and RX_n pins should not exceed ±300mV (for a total of 600mV p-p).
• The total differential voltage (combination of RX_p/RX_n) should not exceed 1,200mV.
• The FHT RX Analog Parameter selection for External AC cap must be EXTERNAL_AC_CAP_DISABLE.
(94) Referenced to RX GND. This specification is also supported before mode configuration.

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Parameter Symbol Description Min Typical Max Unit

VRX-MAX Receiver input — — 1,200 mV

maximum voltage(93)

VRX-MIN Receiver input –200 — — mV

minimum voltage

TRX-DDJ Receive input signal — — 1 UIpkpk

data dependent jitter
(inter-symbol
interference)

TRX-RJ Receive input random — — 0.15 UIpkpk

jitter

TRX-PJ Receive input periodic — — 0.05 UIpkpk

jitter (at high
frequency)

TRX-TJ Receive input total — — 1 UIpkpk

jitter (DDJ + RJ + PJ)

Equalizer FPPM-OFFSET Tolerable data –200 — 200 ppm

specifications frequency offset

Receiver return loss ZRL-DIFF-DC Receiver differential — — 10 dB

DC return loss

ZRL-DIFF-NYQ Receiver differential — — 6 dB

return loss at Nyquist
frequency (FBAUD/2)

ZRL-CM Receiver common- — — 6 dB

mode return loss
below 10 GHz

Receiver DC RDIFF-DC DC differential receive 80 100 120 Ω

impedance impedance

RCM-DC DC common-mode 20 25 30 Ω
receive impedance

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Table 71. F-Tile FGT Receiver Electrical Specifications

For specification status, see the Data Sheet Status table

Parameter Symbol Description Min Typical Max Unit

Receiver input eye VRX-DIFF-PKPK Receiver input Closed eye — 1,200 mV

specifications differential peak-to-
peak voltage(95)

VRX-MAX Receiver input — — 1 V

maximum voltage(96)

VRX-MIN Receiver input –0.3 — — V

minimum voltage(96)

VRX-CM-DC Receiver input DC 0 — 700 mV

common-mode
voltage(97)

TRX-RJ Receive input random — — 0.15 UIpkpk

jitter

TRX-PJ Receive input periodic — — 0.05 UIpkpk

jitter (at high
frequency)

Insertion loss IINS-LOSS-56Gb/s Insertion loss at 56 — — 30 dB

specifications Gbps PAM42/BER
<10–4

IINS-LOSS-53Gb/s Insertion loss at 53 5(98) — — dB

Gbps PAM42/BER
<10–4
continued...

(95) This is supported when the receiver is powered and configured, powered and unconfigured, or unpowered.
(96) VRX_MAX and VRX_MIN are before and after configuration.
(97) The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or
unpowered. This specification is also supported before mode configuration. If squelch detect is used, receiver DC input common-mode
voltage should be within 200 mV to 300 mV. Otherwise, use AC coupling capacitors on board.
(98) The minimum insertion loss specification assumes a PAM4 transmitter with 800 mVppd. For transmitters with output amplitude
adjustment capabilities and can reduce output amplitude to below 800 mVppd, this minimum insertion loss can be further relaxed.

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Parameter Symbol Description Min Typical Max Unit

IINS-LOSS-30Gb/s Insertion loss at 32 — — 30 dB

Gbps NRZ(99) /BER
<10–12

IINS-LOSS-25Gb/s Insertion loss at — — 30 dB

25.78125 Gbps
NRZ(99)/ BER <10–12

Receiver return loss ZRL-DIFF-DC Receiver differential — — 12 dB

DC return loss

ZRL-DIFF-NYQ Receiver differential — — 6 dB

return loss at Nyquist
frequency (FBAUD/2)

ZRL-CM Receiver common- — — 6 dB

mode return loss
below 10 GHz

Receiver DC RDIFF-DC DC differential receive 65 85 102 Ω

impedance impedance
80 100 120 Ω

RCM-DC DC common-mode 20 25 30 Ω
receive impedance

Receiver signal VIDLE-THRESH Receiver signal detect 75 120 175 mVdiff-pkpk

detection(100) input voltage
threshold

F-Tile Electrical Compliance

Table 72. F-Tile FHT Supported Electrical Compliance List

For specification status, see the Data Sheet Status table

Specification/Clause Protocol Encoding Lane Rate (Gbps)

IEEE 802.3-2022 400GAUI-4 PAM4 106.25

continued...

(99) COM compliant package and channel.

(100) Receiver signal detection values in this table are applicable to PCIe and similar standards, such as SATA, where a clock pattern like
PCIe EIEOS 500 MHz clock pattern is used.

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Specification/Clause Protocol Encoding Lane Rate (Gbps)

IEEE 802.3ck-2022 200GAUI-2 PAM4 106.25

200GAUI-4 PAM4 53.125

IEEE 802.3-2022 100GAUI-1 PAM4 106.25

100GAUI-2 PAM4 53.125

100GAUI-4 NRZ 25.78125

50GAUI-1 PAM4 53.125

50GAUI-2 NRZ 25.78125

IEEE 802.3-2022 25GAUI-1 NRZ 25.78125

IEEE 802.3ck-2022 163/162 400GBASE-KR4/CR4 PAM4 106.25

200GBASE-KR2/CR2 PAM4 106.25

100GBASE-KR/CR PAM4 106.25

CEI 4.0/5.0 OIF-CEI-112G VSR/MR/LR PAM4 96 – 116

OIF-CEI-56G VSR/MR PAM4 48 – 58

OIF-CEI-28G VSR/SR/MR NRZ 24 – 29

OIF-25G NRZ 24 – 29

Table 73. F-Tile FGT Supported Electrical Compliance List

For specification status, see the Data Sheet Status table

Specification/Clause Protocol(101) Encoding Lane Rate (Gbps)

IEEE 802.3-2022 400GAUI-8 PAM4 53.125

400GAUI-16 NRZ 26.5625

200GAUI-4 PAM4 53.125

200GAUI-8 NRZ 26.5625

continued...

(101) For protocols which require FGT PAM4 usage, in order to ensure BER compliance please contact Altera Customer Support and
reference case 14023487435.

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Specification/Clause Protocol(101) Encoding Lane Rate (Gbps)

IEEE 802.3-2022 100GAUI-2 PAM4 53.125

100GAUI-4 NRZ 25.78125

50GAUI-1 PAM4 53.125

50GAUI-2 NRZ 26.5625

IEEE 802.3-2022 25GAUI-1 NRZ 25.78125

IEEE 802.3-2022 200GBASE-KR4/CR4 PAM4 53.125

100GBASE-KR2/CR2 PAM4 53.125

50GBASE-KR/CR PAM4 53.125

IEEE 802.3-2022 100GBASE-KR4 NRZ 25.78125

100GBASE-CR4 NRZ 25.78125

IEEE 802.3-2022 40GBASE-KR4 NRZ 10.3125

40GBASE-CR4 NRZ 10.3125

IEEE 802.3-2022 10GBASE-KR/CR NRZ 10.3125

IEEE 802.3-2022 10GBASE-KX4 NRZ 10.3125

IEEE 802.3-2022 25GBASE-KR/CR NRZ 25.78125

CEI 4.0/5.0 CEI-56G VSR/MR/LR PAM4 36 – 58

CEI-28G VSR/SR/MR NRZ 19.9 – 28.1

IOF-CEI-25G LR NRZ 19.9 – 28.1

CEI-11G SR/MR/LR NRZ 9.95 – 11.2

CEI-6G SR/LR NRZ 4.976 – 6.375

G.709 OTU0 NRZ 1.327451

G.sup56
OTU1 NRZ 2.666057
G.sup43
continued...

(101) For protocols which require FGT PAM4 usage, in order to ensure BER compliance please contact Altera Customer Support and
reference case 14023487435.

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Specification/Clause Protocol(101) Encoding Lane Rate (Gbps)

G.sup58 OTU1e NRZ 11.049107

OTU2/2e NRZ 10.709225/11.095728

OTU2f NRZ 11.317642

OTU2r NRZ 12.639086

OTU3 NRZ 4x10.754603

OTU4(OTL4.4) NRZ 4x27.952493

OTU4(OTL4.10) NRZ 10x11.180997

G.709.1 100G FlexO-SR (FOIC1.4) NRZ 4x27.952369

100G FlexO-SR (FOIC1.2) PAM4 2x55.904737

100G FlexO-SR (FOIC2.4) PAM4 4x55.904737

100G FlexO-SR (FOIC4.8) PAM4 8x55.904737

G.709, G.709.4 OTU25u NRZ 25.781651

OTU25 NRZ 27.952.493

OTU50u (OTU50u.2-RS) NRZ 2x26.562.914

OTU50u (OTU50u.1-RS) PAM4 53.125827

OTU50 (OTU50.2-RS) NRZ 2x27.952493

OTU50 PAM4 55.904987

PCIE BASE 4.0 PCIE NRZ 2.5, 5, 8, 16

SMPTE 259M SDI NRZ 0.27

SMPTE 292M NRZ 1.485/1.483516484

SMPTE 372M NRZ 2.97/2.967032967

SMPTE ST 2081 NRZ 5.94/5.934065934

continued...

(101) For protocols which require FGT PAM4 usage, in order to ensure BER compliance please contact Altera Customer Support and
reference case 14023487435.

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Specification/Clause Protocol(101) Encoding Lane Rate (Gbps)

SMPTE ST 2082 NRZ 11.88/11.868131868

CPRI V7.0 CPRI NRZ 1.2288

NRZ 2.4576

NRZ 3.072

NRZ 4.9152

NRZ 6.144

NRZ 8.11008

NRZ 9.8304

NRZ 10.1376

NRZ 12.16512

NRZ 24.33024

JESD204B JESD204B NRZ up to 19.2

JESD204C JESD204C NRZ up to 32.45

DP 2.0 DisplayPort 2.0 NRZ 1.62

NRZ 2.7

NRZ 5.4

NRZ 8.1

NRZ 10

NRZ 13.5

NRZ 20

FC-PI-2 Fiber Channel NRZ 1.0625

NRZ 2.125
continued...

(101) For protocols which require FGT PAM4 usage, in order to ensure BER compliance please contact Altera Customer Support and
reference case 14023487435.

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Specification/Clause Protocol(101) Encoding Lane Rate (Gbps)

FC-PI-5 NRZ 4.25

NRZ 8.5

10GFC NRZ 10.52

FC-PI-5 NRZ 14.025

FC-PI-6 NRZ 28.05

FC-PI-7 PAM4 57.8

Serial ATA revision 3.0 Sata Gen 1, 2, 3 NRZ 1, 3, 6

T10/BSR INCITS 519 SAS 1, 2, 3, 4 NRZ 3, 6, 12, 22.5

IEEE 802.3-2022 10G-EPON NRZ 10

IEEE 802.3-2022 1G-EPON NRZ 1

G.984 GPON NRZ 1.25, 2.5, 10.3

CEI-6G-SR Interlaken NRZ 6.25

CEI-11G-SR NRZ 10.3125

CEI-11G-SR+ NRZ 12.5

OIF-28G MR (OIF-CEI3.0) NRZ 25.78125

OIF-CEI 56G PAM4-MR PAM4 53.125

— SerialLite IV NRZ 32

HDMI1.0-1.2a HDMI NRZ 1.65 × 3 = 4.95

HDMI1.3-1.4b NRZ 3.4 × 3 = 10.2

HDMI2.0-2.0b NRZ 6 × 3 = 18

HDMI2.1 NRZ 12 × 4 = 48

SFF8431 SFP+ NRZ 9.8304 – 12.5

continued...

(101) For protocols which require FGT PAM4 usage, in order to ensure BER compliance please contact Altera Customer Support and
reference case 14023487435.

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Specification/Clause Protocol(101) Encoding Lane Rate (Gbps)

ITU-T G.8261 and G.8262 SyncE NRZ/PAM4 10, 25, 50

InfiniBand™ Architecture Specification InfiniBand NRZ 5, 10, 14.062, 25.78125

RapidIO™ Interconnect Specification SRIO NRZ 1.25, 2.5, 3.125, 6.25, 10.3125

HPS Performance Specifications

This section provides hard processor system (HPS) specifications and timing.

HPS Clock Performance

Table 74. Maximum HPS Clock Frequencies

For specification status, see the Data Sheet Status table

Performance VCCL_HPS (V) MPU Frequency L3 Frequency MPFE Frequency Rate DDR Clock (MHz) DDR (Mb/s per
(MHz) (MHz) (MHz) pin)
(l3_main_free_clk
)

–1 speed grade Fixed: 0.95 1,500 400 400 Quarter 1,600 3,200

667 Half 1,333 2,666

SmartVID 1,350 400 400 Quarter 1,600 3,200

667 Half 1,333 2,666

–2 speed grade SmartVID 1,200 400 334 Quarter 1,333 2,666

600 Half 1,200 2,400

–3 speed grade SmartVID 1,000 400 300 Quarter 1,200 2,400

534 Half 1,067 2,133

–4 speed grade Fixed: 0.8 1,000 400 267 Quarter 1,067 2,133

467 Half 933 1,866

(101) For protocols which require FGT PAM4 usage, in order to ensure BER compliance please contact Altera Customer Support and
reference case 14023487435.

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Related Information
External Memory Interface Spec Estimator
Provides the specific details of the maximum allowed SDRAM operating frequency.

HPS Internal Oscillator Frequency

Table 75. HPS Internal Oscillator Frequency

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Internal oscillator frequency 150 300 400 MHz

HPS PLL Specifications

Table 76. HPS PLL Input Requirements

The main HPS PLL receives its clock signals from the HPS_OSC_CLK pin. Refer to the related information for details about assigning this pin.

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit

Clock input range 25 — 125 MHz

Clock input accuracy — — 50 ppm

Clock input duty cycle 45 50 55 %

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Table 77. HPS PLL Performance

For specification status, see the Data Sheet Status table

Description Min Max Unit

Main PLL VCO output — 3,000 MHz

Peripheral PLL VCO output — 3,000 MHz

h2f_user0_clk(102) — 500 MHz

h2f_user1_clk(102) — 500 MHz

Related Information
Agilex 7 Device Family Pin Connection Guidelines: F-Series and I-Series
Provides more information about the HPS_OSC_CLK pin assignment.

HPS Cold Reset

Table 78. HPS Cold Reset

For specification status, see the Data Sheet Status table

Symbol Description Min Max Unit

tRST0 Minimum time for 3 — ms

HPS_COLD_nRESET
asserted(103)

(102) The HPS PLL provides this clock to the FPGA fabric.
(103)
HPS_COLD_nRESET may be ignored if HPS is not running or if the device is being configured.

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HPS SPI Timing Characteristics

Table 79. SPI Master Timing Requirements

You can adjust the input delay timing by programming the rx_sample_dly register.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tspi_ref_clk The period of the SPI 2.5 — — ns

internal reference clock,
sourced from
l4_main_clk

Tclk SPIM_CLK clock period 16.67 — — ns

Tdutycycle SPIM_CLK duty cycle 45 50 55 %

Tck_jitter SPIM_CLK output jitter — — 2 %

Tdio Master-out slave-in –3 — 2 ns

(MOSI) output skew

Tdssfrst (104) SPI_SS_N asserted to first (1.5 × Tclk) – 2 — — ns

SPIM_CLK edge

Tdsslst (104) Last SPIM_CLK edge to Tclk – 2 — — ns

SPI_SS_N deasserted

Tsu (105) SPIM_MISO setup time — — ns

5.0 – (rx_sample_dly ×
with respect to SPIM_CLK Tspi_ref_clk)(106)
capture edge

Th (105) Input hold in respect to — — ns

1.3 + (rx_sample_dly ×
SPIM_CLK capture edge Tspi_ref_clk)

(104) SPI_SS_N behavior differs depending on Motorola SPI, TI SSP, or Microwire operational mode.
(105) The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge
depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising
edge.
(106)
Valid values of rx_sample_dly range from 1 to 64 (units are in Tspi_ref_clk steps).

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Figure 5. SPI Master Output Timing Diagram

scph* = 0
Tdssfrst
SPI_SS Tdio (max) Tdsslst
Tdio (min)
SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MOSI OUT0 OUT1 OUTn

SPI_MISO

scph* = 1
Tdssfrst
SPI_SS Tdio (max) Tdsslst
Tdio (min)
SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MOSI OUT0 OUT1 OUTn

SPI_MISO

*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register

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Figure 6. SPI Master Input Timing Diagram

scph* = 0

SPI_SS

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MOSI
Tsu Th
SPI_MISO IN0 IN1 INn

scph* = 1

SPI_SS

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MOSI
Tsu Th
SPI_MISO IN0 IN1 INn

*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register

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Table 80. SPI Slave Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tspi_ref_clk The period of the SPI 2.5 — — ns

internal reference clock,
sourced from
l4_main_clk

Tclk SPIM_CLK clock period 30 — — ns

Tdutycycle SPIM_CLK duty cycle 45 50 55 %

Td Master-in slave-out (2 × Tspi_ref_clk) + 3 — (3 × Tspi_ref_clk) + 11 ns

(MISO) output skew

Tsu Master-out slave-in 4 — — ns

(MOSI) setup time

Th Master-out slave-in 9 — — ns
(MOSI) hold time

Tsuss SPI_SS_N asserted to first Tspi_ref_clk + 4.2 — — ns

SPIM_CLK edge

Thss Last SPIM_CLK edge to Tspi_ref_clk + 4.2 — — ns

SPI_SS_N deasserted

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Figure 7. SPI Slave Output Timing Diagram

scph* = 0

SPI_SS Td (max)
Td (min)
SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MISO OUT0 OUT1 OUTn

SPI_MOSI

scph* = 1

SPI_SS Td (max)
Td (min)
SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MISO OUT0 OUT1 OUTn

SPI_MOSI

*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register

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Figure 8. SPI Slave Input Timing Diagram

scph* = 0
Tsuss
SPI_SS Thss

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MISO
Th
Ts
SPI_MOSI
IN0 IN1 INn

scph* = 1
Tsuss
SPI_SS Thss

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

SPI_MISO
Ts Th
SPI_MOSI IN0 IN1 INn

*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register

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HPS SD/MMC Timing Characteristics

Table 81. HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements

These timings apply to SD, MMC, and embedded MMC (eMMC) cards operating at 1.8 V.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tsdmmc_cclk SDMMC_CCLK clock period 2,500 — — ns

(Identification mode)

SDMMC_CCLK clock period 40 — — ns

(SDR12)

SDMMC_CCLK clock period 20 — — ns

(SDR25)

Tdutycycle SDMMC_CCLK duty cycle 45 50 55 %

Tsdmmc_cclk_jitter SDMMC_CCLK output jitter — — 2 %

Tsdmmc_clk Internal reference clock 5 — — ns

before division by 4

Td SDMMC_CMD/ –0.5 + Tsdmmc_clk × — 2.5 + (Tsdmmc_clk × ns

SDMMC_DATA[7:0] output drvsel/2 drvsel/2)
delay(107)

Tsu SDMMC_CMD/ 6 – (Tsdmmc_clk × — — ns

SDMMC_DATA[7:0] input smplsel/2)
setup(108)

Th SDMMC_CMD/ 0.5 + (Tsdmmc_clk × — — ns

SDMMC_DATA[7:0] input smplsel/2)
hold(108)

None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at
1.8 V at power on.

(107)
When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz
for example, the output delay time is 7.5 to 10.5 ns.
(108)
When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (sdmmc_clk) is 200
MHz for example, the setup time is 1 ns and the hold time is 5.5 ns.

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Note: SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC
interface.

Figure 9. SD/MMC Timing Diagram

SDMMC_CCLK
Td

SDMMC_CMD and SDMMC_DATA (Out) Command/Data Out

TSU
Th
SDMMC_CMD and SDMMC_DATA (In)
Command/Data In

HPS USB UPLI Timing Characteristics

Table 82. HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements
For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tusb_clk USB_CLK clock period — 16.667 — ns

Td Clock to USB_STP/ 2 — 7 ns
USB_DATA[7:0] output
delay

Tsu Setup time for USB_DIR/ 4 — — ns

USB_NXT/USB_DATA[7:0]

Th Hold time for USB_DIR/ 1 — — ns

USB_NXT/USB_DATA[7:0]

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Figure 10. USB ULPI Timing Diagram

USB_CLK
Td
USB_STP

USB_DATA[7:0] To PHY From PHY

TSU Th
USB_DIR and USB_NXT

Note: The USB interface supports single data rate (SDR) timing only.

Note: If you need to adjust the timings of certain signals, you can use the HPS registers Pin_Mux.io0_delay through
Pin_Mux.io47_delay to allow software to set the delay chains in each of the dedicated I/Os. For example, to add output
and input delay to the USB_DATA3 signal (HPS_IOA_8), program Pin_Mux.io7_delay.output_val_en = 1, and
Pin_Mux.io7_delay.output_val = 15 to add approximately 1.6 ns output delay from the HPS, and program
Pin_Mux.io7_delay.input_val_en = 3, and Pin_Mux.io7_delay.input_val = 30 to add approximately 2.9 ns input delay into the
HPS. See HPS Programmable I/O Timing Characteristics for more information.

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 83. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements
For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tclk (1000Base-T) TX_CLK clock period — 8 — ns

Tclk (100Base-T) TX_CLK clock period — 40 — ns

Tclk (10Base-T) TX_CLK clock period — 400 — ns

continued...

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Symbol Description Min Typ Max Unit

Tdutycycle (1000Base-T) TX_CLK duty cycle 45 50 55 %

Tdutycycle (10/100Base-T) TX_CLK duty cycle 40 50 60 %

Td (109) (110) TXD/TX_CTL to TX_CLK –0.5 — 0.5 ns

output skew

Figure 11. RGMII TX Timing Diagram

TX_CLK
TX_D[3:0] D0 D1

Td

TX_CTL

Table 84. RGMII RX Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tclk (1000Base-T) RX_CLK clock period — 8 — ns

Tclk (100Base-T) RX_CLK clock period — 40 — ns

Tclk (10Base-T) RX_CLK clock period — 400 — ns

Tdutycycle (1000Base-T) RX_CLK duty cycle 45 50 55 %

Tdutycycle (10/100Base-T) RX_CLK duty cycle 40 50 60 %

Tsu RX_D/RX_CTL to RX_CLK 1 — — ns

setup time

Th (111) RX_CLK to RX_D/RX_CTL 1 — — ns

hold time

(109) Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
(110) If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ns with the HPS I/O
programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.

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Figure 12. RGMII RX Timing Diagram

RX_CLK

TSU Th

RX_D[3:0] D0 D1

RX_CTL

Table 85. Reduced Media Independent Interface (RMII) Clock Timing Requirements
For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tclk REF_CLK clock period, — 20 — ns

sourced by HPS TX_CLK

REF_CLK clock period, — 20 — ns

sourced by external clock
source

Tdutycycle_int Clock duty cycle, REF_CLK 35 50 65 %

sourced by TX_CLK

Tdutycycle_ext Clock duty cycle, REF_CLK 35 50 65 %

sourced by external clock
source

Table 86. RMII TX Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Td TX_CLK to TXD/TX_CTL 2 — 10 ns
output data delay

(111) If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK
by 1.5-2 ns, using the HPS I/O programmable delay.

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Figure 13. RMII TX Timing Diagram

Reference Clock (RX_CLK) (1)

TX_D[1:0] D0 D1

Td

TX_CTL
Note:
1. For RMII mode, RX_CLK is always used as the reference clock. Refer to the related information for example system-level topologies.

Table 87. RMII RX Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tsu RX_D/RX_CTL setup time 2 — — ns

Th RX_D/RX_CTL hold time 1 — — ns

Figure 14. RMII RX Timing Diagram

Reference Clock (RX_CLK) (1)

TSU Th

RX_D[1:0] D0 D1

RX_CTL
Note:
1. For RMII mode, RX_CLK is always used as the reference clock. Refer to the related information for example system-level topologies.

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Table 88. Management Data Input/Output (MDIO) Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tclk MDC clock period 400 — — ns

Td MDC to MDIO output data 10 — 300 ns

delay

Tsu Setup time for MDIO data 10 — — ns

Th Hold time for MDIO data 0 — — ns

Figure 15. MDIO Timing Diagram

MDC
Td
MDIO_OUT Dout0 Dout1

TSU Th

MDIO_IN Din0

Related Information
HPS-to-PHY Interface Diagrams section, Intel Agilex 7 Hard Processor System Technical Reference Manual
Provides the example system-level topologies.

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HPS I2C Timing Characteristics

Table 89. HPS I2C Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Standard Mode Fast Mode Unit

Min Max Min Max

Tclk Serial clock (SCL) 10 — 2.5 — μs

clock period

Tclk_jitter I2C clock output jitter — 2 — 2 %

THIGH (112) SCL high period 4(113) — 0.6(114) — μs

TLOW (115) SCL low period 4.7(116) — 1.3(117) — μs

TSU;DAT Setup time for serial 0.25 — 0.1 — μs

data line (SDA) data
to SCL

THD;DAT (118) Hold time for SCL to 0 3.15 0 0.6 μs

SDA data

TVD;DAT and TVD;ACK SCL to SDA output — 3.45(120) — 0.9(121) μs

(119) data delay
continued...

(112)
You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
(113)
The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the related information for the SCL_High_time equation.
(114)
The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the related information for the SCL_High_time equation.
(115)
You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
(116)
The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the related information for the SCL_Low_time equation.
(117)
The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the related information for the SCL_Low_time equation.
(118) THD;DAT is affected by the rise and fall time.
(119)
TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).

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Symbol Description Standard Mode Fast Mode Unit

Min Max Min Max

TSU;STA Setup time for a 4.7 — 0.6 — μs

repeated start
condition

THD;STA Hold time for a 4 — 0.6 — μs

repeated start
condition

TSU;STO Setup time for a stop 4 — 0.6 — μs

condition

TBUF SDA high pulse 4.7 — 1.3 — μs

duration between
STOP and START

Tscl:r (122) SCL rise time — 1,000 20 300 ns

Tscl:f (122) SCL fall time — 300 6.54 300 ns

Tsda:r (122) SDA rise time — 1,000 20 300 ns

Tsda:f (122) SDA fall time — 300 6.54 300 ns

(120)
Use maximum SDA_HOLD = 240 to be within the specification.
(121)
Use maximum SDA_HOLD = 60 to be within the specification.
(122) Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value,
and total capacitance on the transmission line.

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Figure 16. I2C Timing Diagram

tf tr tSU;DAT

70%
SDA 30%

tHIGH
tVD;DAT
tf tHD;DAT tr

SCL 70%
30%
tHD;STA Tclk tLOW

tBUF

SDA 70%
30%

tSU;STA tHD;STA tVD;ACK tSU;STO

SCL 70%
30%

Related Information
Clock Synchronization section, Agilex 7 Hard Processor System Technical Reference Manual
Provides the SCL high and low time equations.

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HPS NAND Timing Characteristics

Table 90. HPS NAND ONFI 1.0 Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Max Unit

TWP (123) Write enable pulse width 10 — ns

TWH (123) Write enable hold time 7 — ns

TRP (123) Read enable pulse width 10 — ns

TREH (123) Read enable hold time 7 — ns

TCLS (123) Command latch enable to write 10 — ns

enable setup time

TCLH (123) Command latch enable to write 5 — ns

enable hold time

TCS (123) Chip enable to write enable 15 — ns

setup time

TCH (123) Chip enable to write enable hold 5 — ns

time

TALS (123) Address latch enable to write 10 — ns

enable setup time

TALH (123) Address latch enable to write 5 — ns

enable hold time

TDS (123) Data to write enable setup time 7 — ns

TDH (123) Data to write enable hold time 5 — ns

TWB (123) Write enable high to R/B low — 200 ns

TCEA Chip enable to data access time — 100 ns

continued...

(123) This timing is software programmable. Refer to the related information for more information about software-programmable timing in
the NAND flash controller.

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Symbol Description Min Max Unit

TREA Read enable to data access time — 40 ns

TRHZ Read enable to data high — 200 ns

impedance

TRR Ready to read enable low 20 — ns

Figure 17. NAND Command Latch Timing Diagram

CLE tCLS tCLH

tCS tCH
CE

tWP

WE
tALS tALH
ALE
tDS tDH

IO0-7 Command

R/B tWB

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Figure 18. NAND Address Latch Timing Diagram

tCLS
CLE

tCS
CE

tWP
WE
tWH

tALS tALH
ALE
tDS tDH

IO0-7 Address

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Figure 19. NAND Data Output Cycle Timing Diagram

tCLH
CLE

tCH
CE

tWP tWP tWP

WE tWH

tALS
ALE
tDS tDH tDS tDH tDS tDH

IOx DOUT 0 DOUT 1 DOUT n

Figure 20. NAND Data Input Cycle Timing Diagram

tCEA
CE
tRP tRP tRP
RE tREH
tRR

R/B
tREA tRHZ tREA tRHZ tREA tRHZ

IOx DIN 0 DIN 1 DIN n

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Figure 21. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle

CE

tRP
RE tREH
tRR

tREA tREA
R/B
tRHZ

IOx DIN 0 DIN 1 DIN n

tCEA

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Figure 22. NAND Read Status Timing Diagram

CLE tCLS tCLH

tCS tCH tCEA

CE

tWP
WE

tRHZ
RE
tDS tDH

IO0-7 70h Status

tREA

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Figure 23. NAND Read Status Enhanced Timing Diagram

CLE tCLS tCLH

tCS tCH tCEA
CE
tWP

WE tWP
tALH tALS tALH
tWH
ALE

RE
tDS tDH tREA tRHZ

IO0-7 78h R1 R2 R3 Status

Related Information
NAND Flash Controller section, Agilex 7 Hard Processor System Technical Reference Manual
Provides more information about software-programmable timing in the NAND flash controller.

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HPS Trace Timing Characteristics

Table 91. Trace Timing Requirements

To increase the trace bandwidth, Intel recommends routing the trace interface to the FPGA in the HPS Platform Designer component. The FPGA trace interface
offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.

Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed
possible. Refer to your trace module data sheet for termination recommendations.

Most trace modules implement programmable clock and data skew, to improve trace data timing margins. Alternatively, you can change the clock-to-data timing
relationship with the HPS programmable I/O delay.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

Tclk Trace clock period 6.667 — — ns

Tclk_jitter Trace clock output jitter — — 2 %

Tdutycycle Trace clock maximum duty 45 50 55 %

cycle

Td Tclk to D0–D15 output data –0.5 — 1.3 ns

delay

Figure 24. Trace Timing Diagram

Clock (DDR)

Trace Data (DDR)

Td

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HPS GPIO Interface

The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock
frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable
GPIO pulse width is 62.5 µs (at 32 kHz).

If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal
is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If
the external signal is more than two clock cycles, the external signal is not filtered.

HPS JTAG Timing Characteristics

Table 92. HPS JTAG Timing Requirements

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit

tJCP TCK clock period 41.66 — — ns

tJCH TCK clock high time 20 — — ns

tJCL TCK clock low time 20 — — ns

tJPSU (TDI) TDI JTAG port setup time 5 — — ns

tJPSU (TMS) TMS JTAG port setup time 5 — — ns

tJPH JTAG port hold time 0.5 — — ns

tJPCO JTAG port clock to output 0 — 8 ns

tJPZX JTAG port high impedance — — 10 ns

to valid output

tJPXZ JTAG port valid output to — — 10 ns

high impedance

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Figure 25. HPS JTAG Timing Diagram

TMS

TDI
tJCP
tJCH tJCL tJPSU tJPH

TCK
tJPZX tJPCO tJPXZ
TDO

HPS Programmable I/O Timing Characteristics

Table 93. HPS Programmable I/O Delay (Output Path)

For specification status, see the Data Sheet Status table

Name output_val_en output_val Description Min Typ Max Unit

ZERO_CHAIN_DEL 0 0 Intrinsic I/O delay. — 0 — ps

AY Bypasses the delay
chain

CHAIN_DELAY 1 0 Intrinsic I/O delay — 0 — ps

+ Minimum + 0 ×
Chain Delay

ONE_CHAIN_DELA 1 1 Intrinsic I/O delay — 422 — ps

Y + Minimum + 1 ×
Chain Delay

TWO_CHAIN_DELA 1 2 Intrinsic I/O delay — 518 — ps

Y + Minimum + 2 ×
Chain Delay

THREE_CHAIN_DEL 1 3 Intrinsic I/O delay — 607 — ps

AY + Minimum + 3 ×
Chain Delay

FOUR_CHAIN_DEL 1 4 Intrinsic I/O delay — 705 — ps

AY + Minimum + 4 ×
Chain Delay
continued...

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Name output_val_en output_val Description Min Typ Max Unit

FIVE_CHAIN_DELA 1 5 Intrinsic I/O delay — 786 — ps

Y + Minimum + 5 ×
Chain Delay

SIX_CHAIN_DELAY 1 6 Intrinsic I/O delay — 874 — ps

+ Minimum + 6 ×
Chain Delay

SEVEN_CHAIN_DEL 1 7 Intrinsic I/O delay — 955 — ps

AY + Minimum + 7 ×
Chain Delay

EIGHT_CHAIN_DEL 1 8 Intrinsic I/O delay — 1,042 — ps

AY + Minimum + 8 ×
Chain Delay

NINE_CHAIN_DELA 1 9 Intrinsic I/O delay — 1,126 — ps

Y + Minimum + 9 ×
Chain Delay

TEN_CHAIN_DELAY 1 10 Intrinsic I/O delay — 1,214 — ps

+ Minimum + 10 ×
Chain Delay

ELEVEN_CHAIN_DE 1 11 Intrinsic I/O delay — 1,296 — ps

LAY + Minimum + 11 ×
Chain Delay

TWELVE_CHAIN_D 1 12 Intrinsic I/O delay — 1,382 — ps

ELAY + Minimum + 12 ×
Chain Delay

THIRTEEN_CHAIN_ 1 13 Intrinsic I/O delay — 1,462 — ps

DELAY + Minimum + 13 ×
Chain Delay

FOURTEEN_CHAIN 1 14 Intrinsic I/O delay — 1,552 — ps

_DELAY + Minimum + 14 ×
Chain Delay

FIFTEEN_CHAIN_D 1 15 Intrinsic I/O delay — 1,626 — ps

ELAY + Minimum + 15 ×
Chain Delay

— 1 [16:30] INVALID — — — —

— 2 — INVALID — — — —
continued...

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Name output_val_en output_val Description Min Typ Max Unit

— 3 [0:15] INVALID — — — —

SIXTEEN_CHAIN_D 3 16 Intrinsic I/O delay — 1,798 — ps

ELAY + Minimum + 16 ×
Chain Delay

SEVENTEEN_CHAIN 3 17 Intrinsic I/O delay — 1,885 — ps

_DELAY + Minimum + 17 ×
Chain Delay

EIGHTEEN_CHAIN_ 3 18 Intrinsic I/O delay — 1,967 — ps

DELAY + Minimum + 18 ×
Chain Delay

NINETEEN_CHAIN_ 3 19 Intrinsic I/O delay — 2,054 — ps

DELAY + Minimum + 19 ×
Chain Delay

TWENTY_CHAIN_D 3 20 Intrinsic I/O delay — 2,137 — ps

ELAY + Minimum + 20 ×
Chain Delay

TWENTYONE_CHAI 3 21 Intrinsic I/O delay — 2,222 — ps

N_DELAY + Minimum + 21 ×
Chain Delay

TWENTYTWO_CHAI 3 22 Intrinsic I/O delay — 2,305 — ps

N_DELAY + Minimum + 22 ×
Chain Delay

TWENTYTHREE_CH 3 23 Intrinsic I/O delay — 2,395 — ps

AIN_DELAY + Minimum + 23 ×
Chain Delay

TWENTYFOUR_CHA 3 24 Intrinsic I/O delay — 2,475 — ps

IN_DELAY + Minimum + 24 ×
Chain Delay

TWENTYFIVE_CHAI 3 25 Intrinsic I/O delay — 2,564 — ps

N_DELAY + Minimum + 25 ×
Chain Delay

TWENTYSIX_CHAIN 3 26 Intrinsic I/O delay — 2,644 — ps

_DELAY + Minimum + 26 ×
Chain Delay
continued...

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Name output_val_en output_val Description Min Typ Max Unit

TWENTYSEVEN_CH 3 27 Intrinsic I/O delay — 2,732 — ps

AIN_DELAY + Minimum + 27 ×
Chain Delay

TWENTYEIGHT_CH 3 28 Intrinsic I/O delay — 2,808 — ps

AIN_DELAY + Minimum + 28 ×
Chain Delay

TWENTYNINE_CHA 3 29 Intrinsic I/O delay — 2,901 — ps

IN_DELAY + Minimum + 29 ×
Chain Delay

THIRTY_CHAIN_DE 3 30 Intrinsic I/O delay — 2,979 — ps

LAY + Minimum + 30 ×
Chain Delay

Table 94. HPS Programmable I/O Delay (Input Path)

For specification status, see the Data Sheet Status table

Name input_val_en input_val Description Min Typ Max Unit

ZERO_CHAIN_DEL 0 0 Intrinsic I/O delay. — 0 — ps

AY Bypasses the delay
chain

CHAIN_DELAY 1 0 Intrinsic I/O delay — 0 — ps

+ Minimum + 0 ×
Chain Delay

ONE_CHAIN_DELA 1 1 Intrinsic I/O delay — 422 — ps

Y + Minimum + 1 ×
Chain Delay

TWO_CHAIN_DELA 1 2 Intrinsic I/O delay — 518 — ps

Y + Minimum + 2 ×
Chain Delay

THREE_CHAIN_DEL 1 3 Intrinsic I/O delay — 607 — ps

AY + Minimum + 3 ×
Chain Delay

FOUR_CHAIN_DEL 1 4 Intrinsic I/O delay — 705 — ps

AY + Minimum + 4 ×
Chain Delay
continued...

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Name input_val_en input_val Description Min Typ Max Unit

FIVE_CHAIN_DELA 1 5 Intrinsic I/O delay — 786 — ps

Y + Minimum + 5 ×
Chain Delay

SIX_CHAIN_DELAY 1 6 Intrinsic I/O delay — 874 — ps

+ Minimum + 6 ×
Chain Delay

SEVEN_CHAIN_DEL 1 7 Intrinsic I/O delay — 955 — ps

AY + Minimum + 7 ×
Chain Delay

EIGHT_CHAIN_DEL 1 8 Intrinsic I/O delay — 1,042 — ps

AY + Minimum + 8 ×
Chain Delay

NINE_CHAIN_DELA 1 9 Intrinsic I/O delay — 1,126 — ps

Y + Minimum + 9 ×
Chain Delay

TEN_CHAIN_DELAY 1 10 Intrinsic I/O delay — 1,214 — ps

+ Minimum + 10 ×
Chain Delay

ELEVEN_CHAIN_DE 1 11 Intrinsic I/O delay — 1,296 — ps

LAY + Minimum + 11 ×
Chain Delay

TWELVE_CHAIN_D 1 12 Intrinsic I/O delay — 1,382 — ps

ELAY + Minimum + 12 ×
Chain Delay

THIRTEEN_CHAIN_ 1 13 Intrinsic I/O delay — 1,462 — ps

DELAY + Minimum + 13 ×
Chain Delay

FOURTEEN_CHAIN 1 14 Intrinsic I/O delay — 1,552 — ps

_DELAY + Minimum + 14 ×
Chain Delay

FIFTEEN_CHAIN_D 1 15 Intrinsic I/O delay — 1,626 — ps

ELAY + Minimum + 15 ×
Chain Delay

— 1 [16:30] INVALID — — — —

— 2 — INVALID — — — —
continued...

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Name input_val_en input_val Description Min Typ Max Unit

— 3 [0:15] INVALID — — — —

SIXTEEN_CHAIN_D 3 16 Intrinsic I/O delay — 1,798 — ps

ELAY + Minimum + 16 ×
Chain Delay

SEVENTEEN_CHAIN 3 17 Intrinsic I/O delay — 1,885 — ps

_DELAY + Minimum + 17 ×
Chain Delay

EIGHTEEN_CHAIN_ 3 18 Intrinsic I/O delay — 1,967 — ps

DELAY + Minimum + 18 ×
Chain Delay

NINETEEN_CHAIN_ 3 19 Intrinsic I/O delay — 2,054 — ps

DELAY + Minimum + 19 ×
Chain Delay

TWENTY_CHAIN_D 3 20 Intrinsic I/O delay — 2,137 — ps

ELAY + Minimum + 20 ×
Chain Delay

TWENTYONE_CHAI 3 21 Intrinsic I/O delay — 2,222 — ps

N_DELAY + Minimum + 21 ×
Chain Delay

TWENTYTWO_CHAI 3 22 Intrinsic I/O delay — 2,305 — ps

N_DELAY + Minimum + 22 ×
Chain Delay

TWENTYTHREE_CH 3 23 Intrinsic I/O delay — 2,395 — ps

AIN_DELAY + Minimum + 23 ×
Chain Delay

TWENTYFOUR_CHA 3 24 Intrinsic I/O delay — 2,475 — ps

IN_DELAY + Minimum + 24 ×
Chain Delay

TWENTYFIVE_CHAI 3 25 Intrinsic I/O delay — 2,564 — ps

N_DELAY + Minimum + 25 ×
Chain Delay

TWENTYSIX_CHAIN 3 26 Intrinsic I/O delay — 2,644 — ps

_DELAY + Minimum + 26 ×
Chain Delay
continued...

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Name input_val_en input_val Description Min Typ Max Unit

TWENTYSEVEN_CH 3 27 Intrinsic I/O delay — 2,732 — ps

AIN_DELAY + Minimum + 27 ×
Chain Delay

TWENTYEIGHT_CH 3 28 Intrinsic I/O delay — 2,808 — ps

AIN_DELAY + Minimum + 28 ×
Chain Delay

TWENTYNINE_CHA 3 29 Intrinsic I/O delay — 2,901 — ps

IN_DELAY + Minimum + 29 ×
Chain Delay

THIRTY_CHAIN_DE 3 30 Intrinsic I/O delay — 2,979 — ps

LAY + Minimum + 30 ×
Chain Delay

You can program the number of delay steps by adjusting the I/O Delay register (io0_delay through io47_delay for I/Os 0
through 47).

Configuration Specifications

General Configuration Timing Specifications

Table 95. General Configuration Timing Specifications
For specification status, see the Data Sheet Status table

Symbol Description Requirement Unit

Min Max

tCF12ST1 nCONFIG high to nSTATUS high — 20 ms

tCF02ST0 nCONFIG low to nSTATUS low — 400 ms

tST0 nSTATUS low pulse during 0.5 10 ms

configuration error
continued...

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Symbol Description Requirement Unit

Min Max

tCD2UM (124) — 5 ms
CONF_DONE high to user mode

tST12CF0 Minimum time to drive nCONFIG 0 — ms

from high to low after nSTATUS
transitions from low to high

tST02CF1 Minimum time to drive nCONFIG 0 — ms

from low to high after nSTATUS
transitions from high to low

Figure 26. General Configuration Timing Diagram

tST0 tST12CF0 tCF02ST0 tCD2UM
tST02CF1
Reconfiguration Triggered Reconfiguration Configuration Error Recovered Reconfiguration
tCF12ST1
nCONFIG

nSTATUS

CONF_DONE

INIT_DONE

Configuration_State User Mode Device Clean Idle Configuration Err Configuration Fail Device Clean Idle Configuration Initialization User Mode

Note: CONF_DONE and INIT_DONE are de-asserted during device clean state after full device reconfiguration is triggered.

POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR
circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device
is ready to begin configuration.

(124)
This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.

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Table 96. POR Delay Specification

For specification status, see the Data Sheet Status table

POR Delay Minimum Maximum Unit

AS (Normal mode), AVST ×8, AVST ×16, 11.5 20.2 ms

AVST ×32

AS (Fast mode) 1.5 7.6 ms

External Configuration Clock Source Requirements

Table 97. External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements
For specification status, see the Data Sheet Status table

Description External Clock Source Min Typ Max Unit

Clock input frequency(125) Powered by VCCIO_SDM 25/100/125 MHz

Clock input peak-to-peak — — 2 %

period jitter tolerance

Clock input duty cycle 45 50 55 %

JTAG Configuration Timing

Table 98. JTAG Timing Parameters and Values
For specification status, see the Data Sheet Status table

Symbol Description Requirement Unit

Minimum Maximum

tJCP TCK clock period 30 — ns

tJCH TCK clock high time 14 — ns

continued...

(125) The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. You must match the external configuration clock frequency
on the OSC_CLK_1 pin to the configuration clock source assignment in the Intel Quartus Prime software. Other frequencies in the
range are not supported.

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Symbol Description Requirement Unit

Minimum Maximum

tJCL TCK clock low time 14 — ns

tJPSU (TDI) (126) 2 — ns

TDI JTAG port setup time

tJPSU (TMS) (126) 3 — ns

TMS JTAG port setup time

tJPH (126) JTAG port hold time 5 — ns

tJPCO JTAG port clock to output — 7(127) ns

tJPZX JTAG port high impedance to — 14 ns

valid output

tJPXZ JTAG port valid output to high — 14 ns

impedance

Figure 27. JTAG Timing Diagram

TMS

TDI
tJCP
tJCH tJCL tJPSU tJPH

TCK
tJPZX tJPCO tJPXZ
TDO

(126)
For boundary-scan testing, the TMS and TDI JTAG ports minimum setup time and hold time are 7 ns.
(127) Capacitance loading at 10 pF.

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AS Configuration Timing
Table 99. AS Timing Parameters

Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. Refer to the related information to calculate
the maximum allowable skew tolerance for nCSO and AS_DATA pins to AS_CLK.

For specification status, see the Data Sheet Status table

Symbol Description Minimum Typical Maximum Unit

Tclk (128) — 6.02 — ns

AS_CLK clock period

Tdutycycle AS_CLK duty cycle 45 50 55 %

Tdcsfrs AS_nCSO[3:0] asserted 8.5(129) — — ns

to first AS_CLK edge

Tdcslst Last AS_CLK edge to 6.8(129) — — ns

AS_nCSO[3:0]
deasserted
continued...

(128)
AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash
devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash
setup/hold time specifications and AS timing specifications in this data sheet. For AS using multiple serial flash devices, refer to the
related information for the recommended AS_CLK frequency and maximum board loading.
(129) AS operating at maximum clock frequency = 166 MHz. The delay is larger when operating at AS clock frequency lower than 166 MHz.

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Symbol Description Minimum Typical Maximum Unit

Tdo (130) –0.6 — 0.6 ns

AS_DATA[3:0] output
delay

Text_delay (131) (132) Total external propagation 0 — 13.5 ns

delay on AS signals

Tdcsb2b Minimum delay of slave 62 — — ns

select deassertion between
two back-to-back transfers

(130)
Load capacitance for DCLK = 12 pF and AS_DATA = 27 pF. Intel recommends obtaining the Tdo for a given link (including receiver,
transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash
setup time,
• Tsu = Tclk/2 - Tdo(max) + Tbd_clk – Tbd_data(max)
• Tho = Tclk/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
(131) Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
• Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
• Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the
minimum and maximum specification values.
• Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
• Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
(132)
Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency. For more details, refer to
the related information.

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Figure 28. AS Configuration Serial Output Timing Diagram

Tdcsb2b
Tdcsfrs Tdo (min) Tdcslst
Tdo (max)
nCSO

AS_CLK

AS_DATA OUT0 OUT1 OUTn

Figure 29. AS Configuration Serial Input Timing Diagram

Tdcsb2b
nCSO

AS_CLK
Text_delay
AS_DATA IN0 IN1 INn

Related Information
Agilex 7 Configuration User Guide
Provides more information about AS_CLK.

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Avalon Streaming (Avalon-ST) Configuration Timing

Table 100. Avalon-Streaming Timing Parameters for x8, ×16, and ×32 Configurations
For specification status, see the Data Sheet Status table

Symbol Description Minimum Unit

tACLKH AVST_CLK high time 3.6 ns

tACLKL AVST_CLK low time 3.6 ns

tACLKP AVST_CLK period 8 ns

tADSU (133) 2.1 ns

AVST_DATA setup time before rising
edge of AVST_CLK

tADH (133) 0.1 ns

AVST_DATA hold time after rising edge of
AVST_CLK

tAVSU AVST_VALID setup time before rising 2.1 ns

edge of AVST_CLK

tAVDH AVST_VALID hold time after rising edge 0 ns

of AVST_CLK

(133) Data sampled by the FPGA (sink) at the next rising clock edge.

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Figure 30. Avalon-ST Configuration Timing Diagram

tACLKP
tACLKH tACLKL
AVSTx8_CLK
or AVST_CLK
AVST_READY
or AVSTx8_READY tAVSU tAVDH

AVSTx8_VALID
or AVST_VALID
tADSU tADH must deassert
AVSTx8_DATA[7:0] within 6 cycles
AVST_DATA[15:0]
data0 data1 data2 data3
AVST_data[31:0]]

Configuration Bit Stream Sizes

Table 101. Configuration Bit Stream Sizes

Configuration bit stream sizes shown in this table are based on worst-case scenarios. The sizes are typically substantially smaller because of the use of the Intel
bit stream compression. The Intel bit stream compression efficiency has dependency on your design complexity.

128 Mb quad SPI flash size is adequate to store the periphery image.

For specification status, see the Data Sheet Status table

Variant Compressed Configuration Bit Stream Size (Mbits)

AGF 006, AGF 008 293

AGF 012, AGF 014 511

AGF 019, AGF 023 628

AGI 019, AGI 023 733

AGF 022, AGF 027 928

continued...

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Variant Compressed Configuration Bit Stream Size (Mbits)

AGI 022, AGI 027 969

AGI 035, AGI 040 1,436

AGI 041 1,166

I/O Timing
I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing
analysis. You may generate the I/O timing report manually using the Timing Analyzer.

The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the
design after you complete place-and-route.

Related Information
AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs
Provides the techniques to generate I/O timing information using the Intel Quartus Prime software.

Programmable IOE Delay

Table 102. Programmable IOE Delay
For specification status, see the Data Sheet Status table

Parameter Maximum Offset Minimum Offset Fast Model Slow Model Unit

Extended, –E1, –I1 –E2, –I2 –E3, –I3V

Industrial

Input Delay Chain 63 0 1.474 2.324 2.631 3.343 ns

(INPUT_DELAY_CH
AIN)

Output Delay Chain 15 0 0.356 0.552 0.629 0.808 ns

(OUTPUT_DELAY_C
HAIN)

Output Enable 15 0 0.356 0.552 0.629 0.808 ns

Delay Chain
(OE_DELAY_CHAIN
)

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Glossary
Table 103. Glossary
Term Definition

Differential I/O Standards Receiver Input Waveforms

Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground

Differential Waveform

VID
p-n=0V
VID

Transmitter Output Waveforms

Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground

Differential Waveform

VOD
p-n=0V
VOD

fHSCLK I/O PLL input clock frequency.

fHSDR LVDS SERDES block—maximum/minimum LVDS data transfer rate

(fHSDR = 1/TUI), non-DPA.
continued...

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Term Definition

fHSDRDPA LVDS SERDES block—maximum/minimum LVDS data transfer rate

(fHSDRDPA = 1/TUI), DPA.

J (SERDES factor) LVDS SERDES block—deserialization factor (width of parallel data bus).

JTAG Timing Specifications JTAG Timing Specifications:

TMS

TDI

t JCP
t JCH t JCL t JPSU tJPH
TCK

tJPZX tJPCO t JPXZ

TDO

RL Receiver differential input discrete resistor (external to the device).

Sampling window (SW) Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold
times determine the ideal strobe position in the sampling window, as shown:
Bit Time

0.5 x TCCS RSKM Sampling Window RSKM 0.5 x TCCS

(SW)

Single-ended voltage referenced I/O standard The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the
voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which
the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to
provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
continued...

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Term Definition

V CCIO

V OH
V IH(AC)
V IH(DC)
V REF
V IL(DC)
V IL(AC)

V OL
V SS

tC High-speed receiver/transmitter input and output clock period.

TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across
channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure
under SW in this table).

tDUTY LVDS SERDES block—duty cycle on high-speed transmitter output clock.

tFALL Signal high-to-low transition time (80–20%).

tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input.

tOUTPJ_IO Period jitter on the GPIO driven by a PLL.

tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL.

tRISE Signal low-to-high transition time (20–80%).

Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).

VCM(DC) DC Common mode input voltage.

VICM Input Common mode voltage—the common mode of the differential signal at the receiver.

VICM(DC) VCM(DC) DC Common mode input voltage.

VID Input differential voltage swing—the difference in voltage between the positive and complementary conductors of a
differential transmission at the receiver.

VDIF(AC) AC differential input voltage—minimum AC input differential voltage required for switching.

VDIF(DC) DC differential input voltage—minimum DC input differential voltage required for switching.
continued...

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Term Definition

VIH Voltage input high—the minimum positive voltage applied to the input which is accepted by the device as a logic high.

VIH(AC) High-level AC input voltage.

VIH(DC) High-level DC input voltage.

VIL Voltage input low—the maximum positive voltage applied to the input which is accepted by the device as a logic low.

VIL(AC) Low-level AC input voltage.

VIL(DC) Low-level DC input voltage.

VOCM Output Common mode voltage—the common mode of the differential signal at the transmitter.

VOD Output differential voltage swing—the difference in voltage between the positive and complementary conductors of a
differential transmission line at the transmitter.

VSWING Differential input voltage.

VOX Output differential cross point voltage.

VIX(AC) VIX Input differential cross point voltage.

W LVDS SERDES block—Clock Boost Factor.

Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and
I-Series
Document Changes
Version

2024.12.06 • Updated the status of AGI 041 R31E package from Advance to Preliminary in the Data Sheet Status for Agilex 7 FPGAs and SoCs I-Series table.
• Updated the titles to F-Tile FGT Supported Electrical Compliance List and F-Tile FHT Supported Electrical Compliance List.
• Added footnote to refer to case 14023487435 for BER compliance in the F-Tile FGT Supported Electrical Compliance List table.
• Added Output Enable Delay Chain parameter in the Programmable IOE Delay table.
continued...

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Document Changes
Version

• Updated the Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] (Th) specifications in the HPS USB UPLI Timing Characteristics table.
• Added a description about preventing F-Tile performance degradation in the F-Tile Power Supply Recommended Operating Conditions table.
• Added note about supporting Hot Swap with FHT PMA's for AC and DC coupled connections in the F-Tile Receiver Specifications table.

2024.07.08 • Updated the description for T(TX-RJ) symbol in the F-Tile FGT Transmitter Electrical Specifications table.
• Updated "Typical" values of Differential on-chip termination resistors parameter in the R-Tile Transmitter Specifications and R-Tile Receiver
Specifications tables.
• Added footnote in R-Tile Transmitter Specifications and R-Tile Receiver Specifications tables.
• Updated the "Typical" and "Maximum" values of Single sideband phase parameter in the F-Tile FHT Reference Clock Requirements table.
• Updated the "Typical" and "Maximum" values of PNREF-SSB (156.25MHz) parameter and the footnote in the F-Tile FGT Reference Clock Requirements
table.

2024.04.01 • Added AGI 041 R31E package in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs I-Series table.
• Updated the status from Advance to Preliminary for the following devices in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs F-Series table.
— AGF 006/008 R16A package
— AGF 006/008/012/014/019/022/023/027 R24C package
— AGF 019/022/023/027 R31C package
• Updated the status from Advance to Preliminary for AGI 041 R31B and AGI 022/027 R31A packages in the Data Sheet Status for Intel Agilex 7 FPGAs
and SoCs I-Series table.

2023.12.04 • Added AGF 006 and AGF 012 R24D package in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs F-Series table.
• Added footnote in F-Tile FGT Electrical Compliance List table.

2023.10.02 • Added AGF 008 and AGF 014 R24D package in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs F-Series table.
• Updated the status from Advance to Preliminary for AGI 041 R29D package in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs I-Series table.
• Updated supported –2 transceiver speed grade data rate for NRZ in the F-Tile FGT Transmitter and Receiver Data Rate Performance table.
• Updated the CONF_DONE and INIT_DONE signals in the General Configuration Timing Diagram and added a note for the signals.

2023.06.26 • Updated supported data rate for NRZ in the F-Tile FGT Transmitter and Receiver Data Rate Performance table.
• Added table description in the F-Tile FHT Reference Clocks Input Specifications table.
• Updated the F-Tile FGT Reference Clock Input Specifications table.
— Added supported I/O standards.
— Added footnote to ZREF-DIFF-DC.
• Added diagram: Simplified F-Tile FGT Reference Clock Input Buffer.
• Updated VTX-CM OUT, ZRL-DIFF-DC, ZRL-DIFF-NYQ, and ZRL-CMN specifications in the F-Tile FHT Transmitter Electrical Specification table.
• Updated ZRL-DIFF-DC, ZRL-DIFF-NYQ, and ZRL-CMN specifications in the F-Tile FGT Transmitter Electrical Specifications table.
continued...

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Document Changes
Version

• Updated VRX-CM-DC, ZRL-DIFF-DC, ZRL-DIFF-NYQ, ZRL-CM specifications in the F-Tile FHT Receiver Electrical Specifications table.
• Updated the F-Tile FGT Receiver Electrical Specifications table.
— Added footnote to VRX-DIFF-PKPK
— Updated footnote to VRX-CM-DC, IINS-LOSS-30Gb/s, and IINS-LOSS-25Gb/s.
— Updated VRX-DIFF-PKPK, IINS-LOSS-56Gb/s, IINS-LOSS-30Gb/s, IINS-LOSS-25Gb/s, ZRL-DIFF-DC, ZRL-DIFF-NYQ, and ZRL-CM specifications..
• Updated the F-Tile FGT Electrical Compliance List table.
— Updated lane rate for JESD204C protocol.
— Updated specification/clause for SerialLite IV protocol.

2023.04.19 Added AGI 041 R31B package in the Data Sheet Status for Intel Agilex Devices (I-Series) table.

2023.04.03 • Updated the Absolute Maximum Ratings table.

— Updated VCCH (for R-Tile and F-Tile devices), VCCH_SDM (for R-Tile and F-Tile devices), VCCEHT_GXR, VCCERT_GXR, VCCED_GXR, VCCE_PLL_GXR, VCCE_DTS_GXR,
VCCCLK_GXR, VCCHFUSE_GXR, VCC_HSSI_GXR, and VCCH_FGT_GXF specifications.
— Added VCC_HSSI_GXF, VCCFUSECORE_GXF, VCCFUSEWR_GXF, and VCCCLK_GXF specifications.
• Updated VCCH (for R-Tile and F-Tile devices) and VCCH_SDM (for R-Tile and F-Tile devices) in the Recommended Operating Conditions table.
• Updated the simple quad-port RAM specification for –2V speed grade in the Memory Block Performance Specifications table.
• Updated specifications for AGF 006/008 and AGI 019/023 in the Configuration Bit Stream Sizes table.

2023.02.20 • Updated product family name to "Intel Agilex 7".

• Retitled the document from Intel Agilex F-Series and I-Series Device Data Sheet to Intel Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-
Series.
• Added AGI 041 R29D package in the following tables:
— Data Sheet Status for Intel Agilex 7 FPGAs and SoCs I-Series
— Configuration Bit Stream Sizes
• Updated the status from Advance to Preliminary for the following devices in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs I-Series table:
— AGI 019/023 R18A package
— AGI 022/027 R29A package
— AGI 019/022/023/027 R31B package
— AGI 035/040 R39A package
• Updated VCCH_GXR[L,R] and VCCRT_GXR[L,R] specifications in the R-Tile Transceiver Power Supply Recommended Operating Conditions table.
• Added quad SPI flash size to store periphery image in the Configuration Bit Stream Sizes table.

2022.12.19 • Added AGI 022/027 R31A package in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
• Updated table description for the AS Timing Parameters table.
• Added Tdcsb2b symbol in the AS Configuration Serial Output Timing Diagram.
• Updated specifications for AGI 022 and AGI 027 devices in the Configuration Bit Stream Sizes table.
continued...

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Document Changes
Version

2022.11.01 • Renamed document title from Intel Agilex Device Data Sheet to Intel Agilex F-Series and I-Series Device Data Sheet.
• Removed device name in tables and descriptions.
• Changed the status for AGF 019/023 R25A package from Preliminary to Final in the Data Sheet Status for Intel Agilex Devices (F-Series) table.
• Removed conditions for CXL 2.5 GT/s and CXL 5 GT/s in the R-Tile Slow PLL Performance table.
• Updated typical frequency specification in the F-Tile FHT Reference Clock Requirements table.
• Updated VREFIN-CM-AC in the F-Tile FHT Reference Clocks Input Specifications table.
• Updated the parameter and description, and added a footnote for VREFIN-DIFF in the F-Tile FGT Reference Clock Input Specifications table.
• Added VTX-CM OUT specifications in the following tables:
— F-Tile FHT Transmitter Electrical Specifications
— F-Tile FGT Transmitter Electrical Specifications

2022.07.04 • Added AGI 035/040 R39A package in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
• Added VCCH_SDM specifications for F-tile devices in the Recommended Operating Conditions for Intel Agilex Devices table.
• Updated ZTX-DIFF-DC description and specifications in the F-Tile FGT Transmitter Electrical Specifications table.
• Updated RDIFF-DC specifications in the F-Tile FGT Receiver Electrical Specifications table.
• Added specifications for AGI 035 and AGI 040 devices in the Configuration Bit Stream Sizes for Intel Agilex Devices table.

2022.05.12 • Added R-tile and F-tile devices for VCCH specifications in the Absolute Maximum Rating for Intel Agilex Devices table.
• Updated the F-Tile FGT Reference Clock Input Specifications for Intel Agilex Devices table.
— Updated unit for VREFIN-DIFF-AC.
— Updated VREFIN-IL-DC and VREFIN-IH-DC specifications.
— Updated unit and specifications for TREF-RISE/FALL.
— Added VREFIN-CM-AC and VREFIN-CM-DC specifications.
— Updated parameter from PNREF-SSB to PNREF-SSB (156.25MHz).
• Updated the F-Tile FGT Reference Clock Output Driver Specifications for Intel Agilex Devices table.
— Updated TREF-RISE_OUT/FALL_OUT specifications.
— Updated unit for VREFIN-DIFF-AC_OUT.
— Added footnote to VREFIN-CM-OUT.
• Updated the F-Tile FHT Transmitter Electrical Specifications table.
— Removed TTX-DJ and TTX-RJ specifications.
— Updated unit for Transmitter DC impedance.
• Updated the F-Tile FGT Transmitter Electrical Specifications table.
— Updated unit for VTX-DIFF-PKPK.
— Removed VTX-EYE-PKPK specifications.
— Updated description and unit for Transmitter DC impedance.
— Updated ZRL-DIFF-DC specifications.
• Updated unit for Receiver DC impedance in the F-Tile FHT Receiver Electrical Specifications table.
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Document Changes
Version

• Updated the F-Tile FGT Receiver Electrical Specifications table.

— Updated IINS-LOSS-56Gb/s, IINS-LOSS-30Gb/s, and IINS-LOSS-25Gb/s specifications.
— Updated unit for Receiver DC impedance.
• Updated the F-Tile FGT Electrical Compliance List table.
— Removed JESD204A specifications.
— Updated specifications for JESD204B, JESD204C, and HDMI protocols.
• Updated tCF02ST0 specifications in the General Configuration Timing Specifications for Intel Agilex Devices table.

2022.04.15 • Removed R31A package in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
• Updated footnote to VCCBAT in the Recommended Operating Conditions for Intel Agilex Devices table.
• Changed the symbol from VCCR_CORE to VCCRCORE in the following tables:
— Absolute Maximum Rating for Intel Agilex Devices
— Recommended Operating Conditions for Intel Agilex Devices

2021.12.13 Updated the R-Tile Transmitter and Receiver Data Rate Performance for Intel Agilex Devices table.

2021.10.26 • Updated the Data Sheet Status for Intel Agilex Devices (F-Series) table.
— Updated status for AGF 012/014 R24A package.
— Updated status for AGF 022/027 R25A package.
— Added AGF 012/014 R24B package.
— Added AGF 019/023 R25A, R24C, and R31C packages.
• Added AGI 019/023 R18A and R31B packages in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
• Updated the Absolute Maximum Rating for Intel Agilex Devices table.
— Updated footnotes for IOUT condition.
— Changed symbol from VCCEH_FGT_GXF to VCCH_FGT_GXF.
• Updated the Recommended Operating Conditions for Intel Agilex Devices table.
— Added IBAT specifications.
— Updated VI and VO specifications.
• Added footnote to VCCCLK_GXP and VCCH_GXP in the P-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table.
• Updated the R-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table.
— Updated symbol from VCCEHT_GXR[L,R] to VCCH_GXR[L,R].
— Updated symbol from VCCERT_GXR[L,R] to VCCRT_GXR[L,R].
— Updated specifications for VCCH_GXR[L,R], VCCED_GXR[L,R], VCCCLK_GXR[L,R], and VCC_HSSI_GXR.
— Added footnote to VCCH_GXR[L,R] and VCCCLK_GXR[L,R].
• Updated descriptions in the Internal Weak Pull-Up Resistor section.
• Added VIL (min) and VIH (max) in the Single-Ended I/O Standards Specifications for Intel Agilex Devices (for HPS and SDM I/O Banks) table.
• Added footnotes to tREFPJ and tREFPN in the I/O PLL Specifications for Intel Agilex Devices table.
• Updated descriptions in the Remote Temperature Diode Specifications section.
continued...

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Document Changes
Version

• Added the following tables:

— Remote Temperature Diode Specifications for Intel Agilex Devices (R-Tile TSD)
— Remote Temperature Diode Specifications for Intel Agilex Devices (F-Tile TSD)
• Removed the reference to rate support and combined the following tables into one table: Memory Standards Supported by Intel Agilex Devices
— Memory Standards Supported by the Hard Memory Controller for Intel Agilex Devices
— Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices
— Memory Standards Supported by the HPS Hard Memory Controller for Intel Agilex Devices
• Added footnote to FREF in the F-Tile FGT Reference Clock Input Specifications for Intel Agilex Devices table.
• Updated ZREF-DIFF-DC_OUT and VREFIN-DIFF-AC_OUT descriptions in the F-Tile FGT Reference Clock Output Driver Specifications for Intel Agilex Devices
table.
• Updated the F-Tile FHT Transmitter Electrical Specifications table.
— Updated TTX-DJ specification.
— Removed NGPLL specification.
• Updated the F-Tile FGT Transmitter Electrical Specifications table.
— Updated VTX-DIFF-PKPK description.
— Added VTX-EYE-PKPK specifications.
— Removed NGPLL-PAM and NGPLL-NRZ specifications.
• Updated the F-Tile FHT Receiver Electrical Specifications table.
— Added VRX-MAX and VRX-MIN specifications.
— Removed NGPLL specification.
• Updated the F-Tile FGT Receiver Electrical Specifications table.
— Added VRX-MIN specifications.
— Updated footnote to VRX-MAX, VRX-CM-DC, and VIDLE-THRESH.
— Removed NGPLL-PAM and NGPLL-NRZ specifications.
• Updated the F-Tile FHT Electrical Compliance List table.
— Removed IEEE 802.3cd 137/136, IEEE 802.3bj/bm 93, IEEE 802.3bj/bm 92, and IEEE 802.3by 111/110 specifications.
— Updated the protocols for CEI 4.0/5.0 specification.
• Updated the F-Tile FGT Electrical Compliance List table.
— Updated specifications for SDI, JESD204A, JESD204B, JESD204C, Fiber Channel, Interlaken, and HDMI protocols.
— Added specifications for GPON protocol.
• Updated tCF02ST0 to add specifications when security features enabled in the General Configuration Timing Specifications for Intel Agilex Devices table.
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Document Changes
Version

• Updated the description for Tdo in the AS Timing Parameters for Intel Agilex Devices table.
• Updated the Configuration Bit Stream Sizes for Intel Agilex Devices table.
— Added table description.
— Added specifications for AGF 019, AGF 023, AGI 019, and AGI 023 devices.
— Updated specifications for AGF 012, AGF 014, AGF 022, AGF 027, AGI 022, and AGI 027 devices.
• Updated the Programmable IOE Delay for Intel Agilex Devices table.
— Added Industrial grade and updated the fast model specifications.
— Added –E1, –I1, –I2, and –I3V speed grades, and updated the slow model specifications.

2021.06.02 • Updated the Data Sheet Status for Intel Agilex Devices (F-Series) table.
— Removed R17A and R20A packages.
— Added AGF 006 and AGF 008 devices for R24C package.
• Added support for –E4X speed grade in the Intel Agilex Device Grades, Core Speed Grades, and Power Options Supported table.
• Updated the Absolute Maximum Rating for Intel Agilex Devices table.
— Updated the maximum specifications for VCCR_CORE and VCCA_PLL.
— Removed VCCIO3V_GXB, VI (for VCCIO3V_GXB), VCC_HSSI_GXB, VCCH_GXB, VCCT_GXB, and VCCR_GXB specifications.
— Added R-tile specifications: VCCEHT_GXR, VCCERT_GXR, VCCED_GXR, VCCE_PLL_GXR, VCCE_DTS_GXR, VCCCLK_GXR, VCCHFUSE_GXR, and VCC_HSSI_GXR.
— Added F-tile specifications: VCCERT1_FHT_GXF, VCCERT2_FHT_GXF, VCCEHT_FHT_GXF, VCCERT_FGT_GXF, VCCEH_FGT_GXF, and VCCERT_GXF_COMBINE.
• Updated the Recommended Operating Conditions for Intel Agilex Devices table.
— Added specifications for –4X speed grade for VCC and VCCP.
— Removed VCCH and VCCH_SDM specifications for H-tile and P-tile devices.
— Removed VCCIO3V_GXB and VI (for VCCIO3V_GXB) specifications.
— Added VCCH specifications for R-tile and F-tile devices.
— Removed condition for VCCH_SDM.
• Updated the HPS Power Supply Operating Conditions for Intel Agilex Devices table.
— Added specifications for –4X speed grade for VCCL_HPS and VCCPLLDIG_HPS.
— Added footnote for VCCL_HPS and VCCPLLDIG_HPS.
• Updated specifications for 34-Ω and 40-Ω RS in the OCT Calibration Accuracy Specifications for Intel Agilex Devices (for GPIO Bank) table.
• Updated VID and VICM(DC) specifications in the Differential I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) table.
• Added specifications for –4X speed grade in the Clock Tree Performance for Intel Agilex Devices table.
• Updated the I/O PLL Specifications for Intel Agilex Devices table.
— Added specifications for –4X speed grade for fIN, fVCO, fOUT, and fOUT_EXT.
— Updated tOUTDUTY specifications.
— Updated footnote for tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, and tOUTCCJ_IO.
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Document Changes
Version

• Updated the DSP Block Performance Specifications for Intel Agilex Devices table.
— Added specifications for –4X speed grade.
— Added footnote for Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode
— Updated the modes as FP32 floating-point vector dot product and FP16 floating-point vector dot product.
— Added the following modes:
• Sum/sub of two FP16 multiplications with FP32 (addition/subtraction)
• Sum/sub of two FP16 multiplications with accumulation (addition/subtraction)
• Added specifications for –4X speed grade in the Memory Block Performance Specifications for Intel Agilex Devices table.
• Added footnote to Sampling Rate in the Local Temperature Sensor Specifications for Intel Agilex Devices table.
• Removed description on H-tile in the Remote Temperature Diode Specifications section.
• Updated the Voltage Sensor Specifications for Intel Agilex Devices table.
— Added footnote to Sampling Rate and Voltage sensor accuracy.
— Removed Differential non-linearity (DNL) and Integral non-linearity (INL) specifications.
• Updated the description for the Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices table.
• Updated MPU frequency specifications in the Maximum HPS Clock Frequencies for Intel Agilex Devices table.
• Added the HPS Cold Reset for Intel Agilex Devices table.
• Updated Tsu specification in the SPI Master Timing Requirements for Intel Agilex Devices table.
• Updated Tsuss and Thss specifications in the SPI Slave Timing Requirements for Intel Agilex Devices table.
• Updated Td specifications in the HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Agilex Devices table.
• Updated Th specification in the HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel
Agilex Devices table.
• Updated footnotes for THIGH and TLOW specifications in the HPS I2C Timing Requirements for Intel Agilex Devices table.
• Updated Td specifications in the Trace Timing Requirements for Intel Agilex Devices table.
• Updated tJPH specification in the HPS JTAG Timing Requirements for Intel Agilex Devices table.
• Updated typical specifications in the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path)
for Intel Agilex Device tables.
• Added tST12CF0 and tST02CF1 specifications in the General Configuration Timing Specifications for Intel Agilex Devices table.
• Added General Configuration Timing Diagram.
• Updated the AS Timing Parameters for Intel Agilex Devices table.
— Updated table description.
— Updated Tclk, Tdcsfrs, Tdcslst, Tdo, Text_delay, and Tdcsb2b specifications.
— Updated footnote for Text_delay.
• Updated tADH specification in the Avalon-ST Timing Parameters for x8, ×16, and ×32 Configurations in Intel Agilex Devices table.
• Updated the Configuration Bit Stream Sizes for Intel Agilex Devices table.
— Removed AGF 004 device.
— Updated specifications for AGF 006 device.
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Document Changes
Version

• Added R-tile and F-tile specifications. Added the following tables/sections:

— R-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table
— F-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table
— R-Tile Transceiver Performance Specifications section
— F-Tile Transceiver Performance Specifications section
• Removed H-Tile specifications. The following tables/section are removed:
— H-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices
— Remote Temperature Diode Specifications for Intel Agilex Devices (H-Tile TSD)
— H-Tile Transceiver Performance Specifications
• Removed the following tables for 3 V I/O banks:
— Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 3 V I/O Bank)
— I/O Pin Leakage Current for Intel Agilex Devices (for 3 V I/O Bank)
— Bus Hold Parameters for Intel Agilex Devices (for 3 V I/O Bank)
— OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (for 3 V I/O Bank)
— Pin Capacitance for Intel Agilex Devices (for 3 V I/O Bank)
— Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (for 3 V I/O Bank)
— Single-Ended I/O Standards Specifications for Intel Agilex Devices (for 3 V I/O Bank)

2021.01.07 • Updated the Data Sheet Status for Intel Agilex Devices tables.
• Updated table title from Intel Agilex Device Grades and Speed Grades Supported to Intel Agilex Device Grades, Core Speed Grades, and Power
Options Supported.
• Added VCCIO3V_GXB, VI (for VCCIO3V_GXB), VCC_HSSI_GXB, VCCH_GXB, VCCT_GXB, and VCCR_GXB specifications in the Absolute Maximum Rating for Intel Agilex
Devices table.
• Updated the description in the Maximum Allowed Overshoot and Undershoot Voltage section.
• Updated the figure title to Intel Agilex Devices Overshoot Duration Example (for 1.2 V GPIO Bank at VCCIO_PIO = 1.26 V).
• Updated the Recommended Operating Conditions for Intel Agilex Devices table.
— Updated VCC and VCCP specifications.
— Updated description for VCCH.
— Added VCCH and VCCH_SDM specifications for H-tile and P-tile devices.
— Updated note to VCCBAT.
— Added VCCIO3V_GXB and VI (for VCCIO3V_GXB) specifications.
— Updated the minimum specification for tRAMP.
• Added the H-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table.
• Updated VCCL_HPS and VCCPLLDIG_HPS specifications in the HPS Power Supply Operating Conditions for Intel Agilex Devices table.
• Updated the specifications in the I/O Pin Leakage Current for Intel Agilex Devices (For GPIO Bank) table.
• Updated the specifications in the Bus Hold Parameters for Intel Agilex Devices (For GPIO Bank) table.
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Document Changes
Version

• Added specifications for 100-Ω RD for VCCIO_PIO = 1.2 V in the OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (For
GPIO Bank) table.
• Updated the specifications in the Pin Capacitance for Intel Agilex Devices table.
• Updated the specifications in the Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (For GPIO Bank) table.
• Updated the Single-Ended I/O Standards Specifications for Intel Agilex Devices (For GPIO Bank) table.
— Removed note to 1.2 V LVCMOS in the Single-Ended I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) table.
— Added VOL and VOH specifications.
• Added the following tables for HPS, SDM, and 3 V I/O banks:
— Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 3 V I/O Bank)
— I/O Pin Leakage Current for Intel Agilex Devices (for HPS and SDM I/O Bank)
— I/O Pin Leakage Current for Intel Agilex Devices (for 3 V I/O Bank)
— Bus Hold Parameters for Intel Agilex Devices (for 3 V I/O Bank)
— OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (for 3 V I/O Bank)
— Pin Capacitance for Intel Agilex Devices (for 3 V I/O Bank)
— Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Intel Agilex Devices (for HPS and SDM I/O Banks)
— Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (for 3 V I/O Bank)
— Hysteresis Specifications for Schmitt Trigger Input for Intel Agilex Devices (for HPS I/O Bank)
— Single-Ended I/O Standards Specifications for Intel Agilex Devices (for HPS and SDM I/O Banks)
— Single-Ended I/O Standards Specifications for Intel Agilex Devices (for 3 V I/O Bank)
• Updated specification for –1 speed grade in the Clock Tree Performance for Intel Agilex Devices table.
• Updated the I/O PLL Specifications for Intel Agilex Devices table.
— Updated fIN, fVCO, and fOUT specifications for –4F speed grade.
— Updated fOUT_EXT specifications for –2, –3, and –4 speed grades.
— Added tINCCJ specifications.
— Added note to tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, and tOUTCCJ_IO.
— Updated condition for tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, tOUTCCJ_IO, and tCASC_OUTPJ_DC.
• Updated the description in the Remote Temperature Diode Specifications section.
• Updated Ibias, Vbias, and diode ideality factor specifications in the Remote Temperature Diode Specifications for Intel Agilex Devices (E-Tile TSD) table.
• Added the Remote Temperature Diode Specifications for Intel Agilex Devices (H-Tile TSD) table.
• Updated the Voltage Sensor Specifications for Intel Agilex Devices table.
— Updated voltage sensor accuracy Vin range and specifications.
— Updated Unipolar Input Mode specifications.
• Updated tx Jitter for data rate 600 Mbps – 1.6 Gbps in the LVDS SERDES Specifications for Intel Agilex Devices table.
• Updated the jitter amplitude in the LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps diagram.
• Updated the sinusoidal jitter for F3 and F4 in the LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps table.
• Removed RLDRAM 3 specifications from the Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices table.
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Document Changes
Version

• Updated the E-Tile Receiver Specifications table.

— Updated absolute VMAX for a receiver pin specifications.
— Changed from VICM (AC coupled) to VCM (Internal AC coupled) and updated the specifications.
• Updated the P-Tile PLLA Performance table.
— Added PLL bandwidth (BWTX-PKG_PLL1) and PLL peaking (PKGTX-PLL1) specifications for PCIe 5.0 GT/s.
— Updated PLL peaking (PKGTX-PLL2) specifications.
— Added note on PLL bandwidth and PLL peaking.
• Updated the P-Tile PLLB Performance table.
— Added PLL bandwidth (BWTX-PKG_PLL2) and PLL peaking (PKGTX-PLL2) specifications.
— Added note on PLL bandwidth and PLL peaking.
• Updated the P-Tile Reference Clock Specifications table.
— Updated notes to Input reference clock frequency and TCCJITTER.
— Added conditions for Rising edge rate, Falling edge rate, Duty cycle, VICM, TCCJITTER, and TSSC-MAX-PERIOD-SLEW parameters.
— Updated spread-spectrum downspread, absolute VMAX, and absolute VMIN specifications.
• Added condition for differential on-chip termination resistors parameter in the P-Tile Transmitter Specifications table.
• Updated the P-Tile Receiver Specifications table.
— Updated VID (diff p-p) specifications for PCIe 16.0 GT/s.
— Removed VICM (AC coupled) specifications.
— Added RREF specifications.
• Added H-Tile Transceiver Performance Specifications section.
• Updated fixed VCCL_HPS and MPU frequency for –1 speed grade in the Maximum HPS Clock Frequencies for Intel Agilex Devices table.
• Updated the internal oscillator frequency in the HPS Internal Oscillator Frequency for Intel Agilex Devices table.
• Added the HPS JTAG Timing Diagram.
• Updated the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device
tables.
• Removed note to tCF12ST1 in the General Configuration Timing Specifications for Intel Agilex Devices table.
• Updated the POR Delay Specification for Intel Agilex Devices table.
• Updated the description for clock input peak-to-peak period jitter tolerance parameter in the External Configuration Clock Source (OSC_CLK_1) Clock
Input Requirements table.
• Added notes to tJPSU (TDI), tJPSU (TMS), tJPH, and tJPCO in the JTAG Timing Parameters and Values for Intel Agilex Devices table.
• Updated the AS Timing Parameters for Intel Agilex Devices table.
— Updated the note to Tdo.
— Updated Tdcsb2b specification.
• Updated the AS Configuration Serial Input Timing Diagram to include Tdcsb2b.
• Removed Maximum Configuration Time Estimation specifications.
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Document Changes
Version

2020.06.30 • Updated the Recommended Operating Conditions for Intel Agilex Devices table.
— Added note to VCCIO_PIO_SDM.
— Removed the note on HPS_PORSEL from tRAMP. HPS_PORSEL pin is not available for Intel Agilex devices.
• Added note to Text_delay in the AS Timing Parameters for Intel Agilex Devices table.
• Removed SD/MMC configuration mode specifications in the following tables:
— POR Delay Specification for Intel Agilex Devices
— Maximum Configuration Time Estimation for Intel Agilex Devices

2020.05.14 Updated VCCFUSEWR_SDM specifications in the Recommended Operating Conditions for Intel Agilex Devices table.

2020.03.18 • Added the Absolute Maximum Rating for Intel Agilex Devices table.
• Added Maximum Allowed Overshoot and Undershoot Voltage section.
• Updated the Recommended Operating Conditions for Intel Agilex Devices table.
— Updated the typical values for VCC and VCCP.
— Added VCCR_CORE specifications.
— Updated description for VCCPT and VCCIO_PIO_SDM.
— Updated VCCFUSEWR_SDM and VI specifications.
— Updated VCCA_PLL specifications and description.
— Added a note for TJ minimum specifications for Industrial.
— Updated tRAMP minimum specification.
• Updated the E-Tile Transceiver Power Supply Operating Conditions table.
— Updated VCCCLK_GXE for maximum DC level.
— Updated VCCCLK_GXE for recommended AC transient level.
— Updated wording for all recommended DC values from % of DC level to % of Vnominal.
• Updated wording for all recommended DC values from % of DC level to % of Vnominal in the P-Tile Transceiver Power Supply Operating Conditions.
• Updated the E-Tile Transmitter and Receiver Data Rate Performance Specifications table with the transceiver speed grades for the NRZ and PAM4
supported data rates.
• Updated the transmitter differential output voltage peak-to-peak typical value in the E-Tile Transmitter Specifications table.
• Updated the E-tile Receiver Specifications table:
— Added the absolute Vmax for a receiver pin specification
— Added the maximum peak-to-peak differential input voltage VID (diff p-p) before/after device configuration specification
— Added VICM (AC coupled) specification
— Removed the electrical idle detection voltage specification
• Updated P-Tile Transceiver Performance:
— Added supported data rate for Gen1, Gen 2, Gen 3, and Gen 4 in the P-Tile Transmitter and Receiver Data Rate Performance table.
— Removed the maximum VCO frequency value and replaced it with a typical value in the P-Tile PLLA Performance table.
— Removed the maximum VCO frequency value and replaced it with a typical value in the P-Tile PLLB Performance table.
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Document Changes
Version

• Updated P-Tile Transmitter Specifications:

— Added PCIe condition for Supported I/O Standards.
— Removed VOCM (AC Coupled).
• Updated P-Tile Receiver Specifications:
— Added PCIe condition for Supported I/O Standards.
— Added PCIe 8.0 GT/s and 16.0 GT/s specifications for the peak-to-peak differential input voltage VID (diff p-p) and added corresponding notes.
— Updated RESREF specification. Added a note to the RESREF specification.
• Updated VCCL_HPS and VCCPLLDIG_HPS specifications for SmartVID in the HPS Power Supply Operating Conditions for Intel Agilex Devices table.
• Changed Early Power Estimator (EPE) to Intel FPGA Power and Thermal Calculator.
• Added a note to 1.2 V LVCMOS in the Single-Ended I/O Standards Specifications for Intel Agilex Devices table.
• Added a note in the Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications for Intel Agilex Devices table.
• Updated the Differential I/O Standards Specifications for Intel Agilex Devices table.
— Updated I/O standard name from "1.5 V True Differential Signaling" to "True Differential Signaling (Transmitter & Receiver)".
— Added specifications for True Differential Signaling (Receiver only).
— Updated note to True Differential Signaling.
• Updated the I/O PLL Specifications for Intel Agilex Devices table.
— Added notes for tFCOMP, tOUTPJ_DC, and tOUTCCJ_DC.
— Removed tINCCJ specifications.
— Added tREFPJ and tREFPN specifications.
— Updated tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, tOUTCCJ_IO, and tCASC_OUTPJ_DC specifications.
• Added a note for fixed-point 27 × 27 multiplication mode in the DSP Block Performance Specifications for Intel Agilex Devices table.
• Updated the Memory Block Performance Specifications for Intel Agilex Devices table.
— Updated the specifications for MLAB memory.
— Updated the specifications for M20K block and added low power (LP) specifications.
• Updated the specifications in the Remote Temperature Diode Specifications for Intel Agilex Devices (Core Fabric TSD) table.
• Added the Remote Temperature Diode Specifications for Intel Agilex Devices (P-Tile TSD) table.
• Updated the LVDS SERDES Specifications for Intel Agilex Devices table.
— Updated the tx Jitter - True Differential I/O Standards specifications for –4 speed grade.
— Removed global, regional, or local in clock routing resource.
• Updated the DPA Lock Time Specifications for Intel Agilex Devices table.
— Updated the description of the table.
— Updated the maximum data transition from 960 to 768.
• Updated the jitter requirements in the Memory Output Clock Jitter Specifications section.
• Updated the specifications in the Maximum HPS Clock Frequencies for Intel Agilex Devices table.
• Updated the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device
tables.
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Send Feedback Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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 Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
683301 | 2024.12.06

Document Changes
Version

• Updated the following diagrams:

— USB ULPI Timing Diagram
— RGMII TX Timing Diagram
— RMII TX Timing Diagram
— RMII RX Timing Diagram
• Updated tST0 and tCD2UM specifications in the General Configuration Timing Specifications for Intel Agilex Devices table.
• Added notes to Tclk and Tdo specifications in the AS Timing Parameters for Intel Agilex Devices table.
• Updated tADSU and tAVSU specifications in the Avalon-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel Agilex Devices table.
• Added the following tables:
— Configuration Bit Stream Sizes for Intel Agilex Devices
— Maximum Configuration Time Estimation for Intel Agilex Devices
— Programmable IOE Delay for Intel Agilex Devices

2019.12.18 Updated the I/O PLL Specifications for Intel Agilex Devices table.
• Removed scanclk from fDYCONFIGCLK parameter.
• Corrected the maximum specification for fDYCONFIGCLK from 200 MHz to 100 MHz.

2019.04.02 Initial release.

Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series Send Feedback

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