Evaluation board available.

NX2124/2124A
300kHz SYNCHRONOUS PWM CONTROLLER
PRELIMINARY DATA SHEET
Pb Free Product

DESCRIPTION FEATURES
The NX2124/2124A controller IC is a synchronous Buck n
Bus voltage operation from 2V to 25V
controller IC designed for step down DC to DC con- Fixed n
300kHz voltage mode controller
verter applications. It is optimized to convert bus volt- Internal n
Digital Soft Start Function
ages from 2V to 25V to outputs as low as 0.8V voltage. Prebias n
Startup
The NX2124/2124A operates at fixed 300kHz, employs Less than n50 nS adaptive deadband
fixed loss-less current limiting by sensing the Rdson of Current n
limit triggers hiccup by sensing Rdson of
synchronous MOSFET followed by hiccup feature. Synchronous MOSFET
NX2124A has higher current limit threshold than NX2124. n No negative spike at Vout during startup and
Feedback under voltage also triggers hiccup. shutdown
Other features of the device are: 5V gate drive, Adaptive n Pb-free and RoHS compliant
deadband control, Internal digital soft start, Vcc APPLICATIONS
undervoltage lock out and shutdown capability via the
n Graphic Card on board converters
comp pin.
n Memory Vddq Supply in mother board applications
n On board DC to DC such as
5V to 3.3V, 2.5V or 1.8V
n Hard Disk Drive
n Set Top Box
TYPICAL APPLICATION
L2 1uH
Vin
+5V C4 C5 Cin
100uF 1uF 280uF
R5 D1 18mohm
10 MBR0530T1

C3
1uF 5 1
C6
Vcc BST 0.1uF
2 M1
7 Hdrv
COMP L1 1.5uH
NX2124

M3
HI=SD Vout
R4 8
37.4k SW +1.8V 9A
Co
C7 R1 2 x (1500uF,13mohm)
27pF C2 4 M2
Ldrv 4k
2.2nF
6
FB R2
C1
Gnd 4.7nF 10k
3

R3
8k

Figure1 - Typical application of 2124

ORDERING INFORMATION
Device Temperature Package Frequency OCP Threshold Pb-Free
NX2124CSTR 0 to 70oC SOIC-8L 300kHz 360mV Yes
NX2124ACSTR 0 to 70o C SOIC-8L 300kHz 540mV Yes

Rev.1.8 1
02/28/08
 NX2124/2124A

ABSOLUTE MAXIMUM RATINGS (NOTE1)

Vcc to GND & BST to SW voltage ................... 6.5V
BST to GND Voltage ...................................... 40V
SW to GND Voltage .......................................-3V to 35V
Storage Temperature Range ............................. -65oC to 150oC
Operating Junction Temperature Range ............. -40oC to 125oC

NOTE1: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION
8-PIN PLASTIC SOIC (S)

θJA ≈ 130o C/W

BST 1 8 SW
HDrv 2 7 Comp
Gnd 3 6 Fb
LDrv 4 5 Vcc

ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to TA
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage VREF 4.5V<Vcc<5.5V 0.8 V
Ref Voltage line regulation 0.4 %
Supply Voltage(Vcc)
VCC Voltage Range VCC 4.5 5 5.5 V
VCC Supply Current (Static) ICC (Static) Outputs not switching 3 mA
VCC Supply Current ICC CLOAD=3300pF FS=300kHz 5 mA
(Dynamic) (Dynamic)
Supply Voltage(VBST)
VBST Supply Current (Static) IBST (Static) Outputs not switching 0.15 mA
VBST Supply Current IBST CLOAD=3300pF FS=300kHz 5 mA
(Dynamic) (Dynamic)
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising 4.2 V
VCC-Hysteresis VCC_Hyst VCC Falling 0.22 V

Rev.1.8 2
02/28/08
 NX2124/2124A
PARAMETER SYM Test Condition Min TYP MAX Units
SS
Soft Start time Tss Fsw=300Khz 3.4 mS
Oscillator (Rt) 1.7
Frequency FS NX2124, NX2124A 300 kHz
Ramp-Amplitude Voltage VRAMP 1.6 V
Max Duty Cycle 84 %
Min Duty Cycle 0 %
Error Amplifiers
Transconductance 2000 umho
Input Bias Current Ib 10 nA
Comp SD Threshold 0.3 V
FBUVLO
Feedback UVLO threshold percent of nominal 65 70 75 %
High Side Driver(C L=2200pF)
Output Impedance , Sourcing Rsource(Hdrv) I=200mA 1.9 ohm
Output Impedance , Sinking Rsink(Hdrv) I=200mA 1.7 ohm
Sourcing Current Isource(Hdrv) 1 A
Sinking Current Isink(Hdrv) 1.2 A
Rise Time THdrv(Rise) 14 ns
Fall Time THdrv(Fall) 17 ns
Deadband Time Tdead(L to Ldrv going Low to Hdrv 30 ns
H) going High, 10%-10%
Low Side Driver (C L=2200pF)

Output Impedance, Sourcing Rsource(Ldrv) I=200mA 1.9 ohm

Current
Output Impedance, Sinking Rsink(Ldrv) I=200mA 1 ohm
Current
Sourcing Current Isource(Ldrv) 1 A
Sinking Current Isink(Ldrv) 2 A
Rise Time TLdrv(Rise) 13 ns
Fall Time TLdrv(Fall) 12 ns
Deadband Time Tdead(H to SW going Low to Ldrv 10 ns
L) going High, 10% to 10%
OCP
OCP voltage NX2124 360 mV
NX2124A 540

Rev.1.8 3
02/28/08
 NX2124/2124A

PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1 BST This pin supplies voltage to the high side driver. A high frequency
ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin.

2 HDRV High side MOSFET gate driver.

3 GND Ground pin.

4 LDRV Low side MOSFET gate driver. For the high current application, a 4.7nF capaci-
tor is recommended to be placed on low side MOSFET's gate to ground. This is
to prevent undesired Cdv/dt induced low side MOSFET's turn on to happen,
which is caused by fast voltage change on the drain of low side MOSFET in
synchronous buck converter and lower the system efficiency.

5 Vcc Voltage supply for the internal circuit as well as the low side MOSFET gate
driver. A 1uF high frequency ceramic capacitor must be connected from this pin
to GND pin.

6 FB This pin is the error amplifier inverting input. This pin is also connected to the
output UVLO comparator. When this pin falls below 0.56V, both HDRV and
LDRV outputs are in hiccup.

7 COMP This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop. This pin is also used as a shut
down pin. When this pin is pulled below 0.3V, both drivers are turned off and
internal soft start is reset.

8 SW This pin is connected to the source of the high side MOSFET and provides
return path for the high side driver. Also SW senses the low side MOSFETS
current, when the pin voltage is lower than 360mV for NX2124, 540mV for NX2124A,
hiccup will be triggered.

Rev.1.8 4
02/28/08
 NX2124/2124A

BLOCK DIAGRAM

VCC 70%Vp
Hiccup Logic
FB

Bias 1.25V OC
Generator 0.8V BST
UVLO POR

START
HDRV

COMP SW
0.3V OC
START 0.8V Control
Logic
OSC PWM VCC
Digital
start Up ramp
S
Q LDRV
R

FB

0.6V
CLAMP 1.3V 360mV/540mV
COMP CLAMP
Hiccup Logic
START
OCP
comparator
GND

Figure 2 - Simplified block diagram of the NX2124/NX2124A

Rev.1.8 5
02/28/08
 NX2124/2124A
VIN -VOUT VOUT 1
APPLICATION INFORMATION ∆IRIPPLE = × ×
LOUT VIN FS
Symbol Used In Application Information: 5V-1.8V 1.8v 1 ...(2)
= × × = 2.56A
VIN - Input voltage 1.5uH 5v 300kHz
VOUT - Output voltage
IOUT - Output current
Output Capacitor Selection
DVRIPPLE - Output voltage ripple Output capacitor is basically decided by the
FS - Working frequency amount of the output voltage ripple allowed during steady
DIRIPPLE - Inductor current ripple state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
Design Example of iterations to satisfy both condition.
The following is typical application for NX2124, the Based on DC Load Condition
schematic is figure 1. The amount of voltage ripple during the DC load
VIN = 5V condition is determined by equation(3).
VOUT=1.8V ∆IRIPPLE
∆VRIPPLE = ESR × ∆IRIPPLE +
FS=300kHz 8 × FS × COUT ...(3)
IOUT=9A Where ESR is the output capacitors' equivalent
DVRIPPLE <=20mV series resistance,COUT is the value of output capacitors.
DVDROOP<=100mV @ 9A step Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
Output Inductor Selection
types are used, the amount of the output voltage ripple
The selection of inductor value is based on induc-
is dominated by the first term in equation(3) and the
tor ripple current, power rating, working frequency and
second term can be neglected.
efficiency. Larger inductor value normally means smaller
For this example,electrolytic capacitors are cho-
ripple current. However if the inductance is chosen too
sen as output capacitors, the ESR and inductor current
large, it brings slow response and lower efficiency. Usu-
typically determines the output voltage ripple.
ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be ∆VRIPPLE 20mV
ESR desire = = = 7.8m Ω ...(4)
decided by design engineer according to various appli- ∆IRIPPLE 2.56A
cation requirements. The inductor value can be calcu- If low ESR is required, for most applications, mul-
lated by using the following equations: tiple capacitors in parallel are better than a big capaci-
tor. For example, SANYO electrolytic capacitor
VIN -VOUT VOUT 1
L OUT = × × 16ME1500WG is chosen.
∆IRIPPLE VIN FS
...(1)
IRIPPLE =k × IOUTPUT E S R E × ∆ IR I P P L E
N = ...(5)
∆ VR IPPLE
where k is between 0.2 to 0.4.
Select k=0.3, then
Number of Capacitor is calculated as
5V-1.8V 1.8V 1
L OUT = × ×
0.3 × 9A 5V 300kHz 13mΩ× 2.56A
N=
L OUT =1.4uH 20mV
Choose inductor from COILCRAFT DO5010P- N =1.7
152HC with L=1.5uH is a good choice. The number of capacitor has to be round up to a
Current Ripple is recalculated as integer. Choose N =2.
If ceramic capacitors are chosen as output ca
Rev.1.8 6
02/28/08
 NX2124/2124A
pacitors, both terms in equation (3) need to be evalu- of output capacitor. For low frequency capacitor such
ated to determine the overall ripple. Usually when this as electrolytic capacitor, the product of ESR and ca-
type of capacitors are selected, the amount of capaci- pacitance is high and L ≤ L crit is true. In that case, the
tance per single unit is not sufficient to meet the tran- transient spec is dependent on the ESR of capacitor.
sient specification, which results in parallel configura- In most cases, the output capacitors are multiple
tion of multiple capacitors . capacitors in parallel. The number of capacitors can be
For example, one 100uF, X5R ceramic capacitor calculated by the following
with 2mΩ ESR is used. The amount of output ripple is
ESR E × ∆Istep VOUT
N= + × τ2 ...(9)
∆VRIPPLE = 2mΩ× 2.56A +
2.56A ∆Vtran 2 × L × C E × ∆Vtran
8 × 300kHz × 100uF
where
= 15mV
Although this meets DC ripple spec, however it 0 if L ≤ L crit

needs to be studied for transient requirement. τ =  L × ∆Istep
 V − ESR E × CE if L ≥ L crit ...(10)
Based On Transient Requirement  OUT
Typically, the output voltage droop during transient
For example, assume voltage droop during tran-
is specified as:
sient is 100mV for 9A load step.
∆VDROOP <∆VTRAN @ step load DISTEP
If the SANYO electrolytic capaictor 16ME1500WG
During the transient, the voltage droop during the
(1500uF, 13mΩ ) is used, the critical inductance is given
transient is composed of two sections. One Section is
as
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as ESR E × C E × VOUT
L crit = =
input, output voltage. For example, for the overshoot, ∆Istep
when load from high load to light load with a DISTEP 13mΩ × 1500µF × 1.8V
= 3.9µH
transient load, if assuming the bandwidth of system is 9A
high enough, the overshoot can be estimated as the fol- The selected inductor is 1.5uH which is smaller
lowing equation. than critical inductance. In that case, the output voltage
transient only dependent on the ESR.
VOUT
∆Vovershoot = ESR × ∆Istep + × τ2 ...(6) number of capacitors is
2 × L × COUT
where τ is the a function of capacitor, etc. ESR E × ∆Istep VOUT
N= + × τ2
∆Vtran 2 × L × CE × ∆Vtran
0 if L ≤ L crit
 13mΩ × 9A
τ =  L × ∆Istep = +
 V − ESR × COUT if L ≥ L crit ...(7) 100mV
 OUT 1.8V
× (0) 2
where 2 ×1.5µH × 220µF × 100mV
ESR × COUT × VOUT ESR E × C E × VOUT = 1.2
L crit = = ...(8)
∆Istep ∆Istep
The number of capacitors has to satisfied both ripple
where ESRE and CE represents ESR and capaci- and transient requirement. Overall, we can choose N=2.
tance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected out-
put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR

Rev.1.8 7
02/28/08
 NX2124/2124A

It should be considered that the proposed equa-

1
tion is based on ideal case, in reality, the droop or over- FZ1 = ...(11)
2 × π × R 4 × C2
shoot is typically more than the calculation. The equa-
1
tion gives a good start. For more margin, more capaci- FZ2 = ...(12)
2 × π × (R 2 + R3 ) × C3
tors have to be chosen after the test. Typically, for high
1
frequency capacitor such as high quality POSCAP es- FP1 = ...(13)
2 × π × R3 × C3
pecially ceramic capacitor, 20% to 100% (for ceramic)
1
more capacitors have to be chosen since the ESR of FP2 = ...(14)
C1 × C2
capacitors is so low that the PCB parasitic can affect 2 × π × R4 ×
C1 + C2
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters. where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator. Their locations are shown in figure 4.
Compensator Design The transfer function of type III compensator for
Due to the double pole generated by LC filter of the
transconductance amplifier is given by:
power stage, the power system has 180o phase shift ,
Ve 1 − gm × Z f
and therefore, is unstable by itself. In order to achieve =
VOUT 1 + gm × Zin + Z in / R1
accurate output voltage and fast transient
response,compensator is employed to provide highest For the voltage amplifier, the transfer function of
possible bandwidth and enough phase margin.Ideally,the compensator is
Bode plot of the closed loop system has crossover fre-
Ve −Z f
quency between1/10 and 1/5 of the switching frequency, =
VOUT Zin
phase margin greater than 50o and the gain crossing
To achieve the same effect as voltage amplifier,
0dB with -20dB/decade. Power stage output capacitors
the compensator of transconductance amplifier must
usually decide the compensator type. If electrolytic
satisfy this condition: R 4>>2/gm. And it would be desir-
capacitors are chosen as output capacitors, type II com-
able if R 1||R2||R3>>1/gm can be met at the same time.
pensator can be used to compensate the system, be-
cause the zero caused by output capacitor ESR is lower
than crossover frequency. Otherwise type III compensa- Zf
Vout
tor should be chosen. Zin C1

A. Type III compensator design R3 C2 R4

R2
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero C3
Fb
caused by output capacitors is higher than the cross- Ve
gm
over frequency. In this case, it is necessary to compen- R1
sate the system with type III compensator. The follow- Vref
ing figures and equations show how to realize the type III
compensator by transconductance amplifier.
Figure 3 - Type III compensator using
transconductance amplifier

Rev.1.8 8
02/28/08
 NX2124/2124A
Case 1: FLC<FO<FESR R 2 × VREF 10k Ω × 0.8V
R1 = = = 8k Ω
VOUT -VREF 1.8V-0.8V

Choose R1=8kΩ.
3. Set zero FZ2 = FLC and Fp1 =FESR .
power stage
Gain(db)

FLC 4. Calculate R4 and C3 with the crossover

40dB/decade frequency at 1/10~ 1/5 of the switching frequency. Set
FO=30kHz.

1 1 1
C3 = ×( - )
2 × π × R2 Fz2 Fp1
loop gain
FESR 1 1 1
= ×( - )
2 × π × 10kΩ 6.2kHz 60.3kHz
=2.3nF
20dB/decade

VOSC 2 × π × FO × L
R4 = × × Cout
compensator Vin C3
1.5V 2 × π × 30kHz × 1.5uH
= × × 440uF
5V 2.2nF
=16.9kΩ
FZ1 FZ2 FO FP1 FP2 Choose C3=2.2nF, R 4=16.9kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).

Figure 4 - Bode plot of Type III compensator 1

C2 =
2 × π × FZ1 × R 4
Design example for type III compensator are in 1
=
order. The crossover frequency has to be selected as 2 × π × 0.75 × 6.2kHz × 16.9kΩ
FLC<FO<FESR and FO<=1/10~1/5Fs. Here two POSCAP = 2nF
2R5TPE220MC(220uF,12 mΩ) are chosen as output Choose C2=2.2nF.
capacitor. 6. Calculate C 1 by equation (14) with pole F p2 at
half the switching frequency.
1.Calculate the location of LC double pole F LC
and ESR zero FESR. 1
C1 =
2 × π × R 4 × FP2
1
FLC = 1
2 × π × L OUT × COUT =
2 × π × 16.9kΩ × 150kHz
=
1 = 63pF
2 × π × 1.5uH × 440uF
Choose C1=68pF.
= 6.2kHz
7. Calculate R 3 by equation (13).

1 1
FESR = R3 =
2 × π × ESR × C OUT 2 × π × FP1 × C3
1 1
= =
2 × π × 6m Ω × 440uF 2 × π × 60.3kHz × 2.2nF
= 60.3kHz = 1.2kΩ
2. Set R2 equal to 10kΩ. Choose R3=1.2kΩ.

Rev.1.8 9
02/28/08
 NX2124/2124A
Case 2: FLC<FESR<FO 2. Set R2 equal to 10kΩ.
R 2 × VREF 10kΩ × 0.8V
R1 = = = 8kΩ
VOUT -VREF 1.8V-0.8V
Choose R1=8.06kΩ.
power stage 3. Set zero FZ2 = FLC and Fp1 =FESR .
Gain(db)

FLC 4. Calculate C3 .
40dB/decade 1 1 1
C3 = ×( - )
2 × π × R2 Fz2 Fp1
FESR 1 1 1
= ×( - )
2 × π × 10kΩ 2.3kHz 8.2kHz
loop gain
=4.76nF
Choose C3=4.7nF.
20dB/decade 5. Calculate R3 .

1
R3 =
compensator 2 × π × FP1 × C3
1
=
2 × π × 8.2kHz × 4.7nF
= 4.1kΩ
Choose R3 =4kΩ.
FZ1 FZ2 FP1 FO FP2 6. Calculate R4 with FO=30kHz.

VOSC 2 × π × FO × L R2 × R3
R4 = × ×
Figure 5 - Bode plot of Type III compensator Vin ESR R 2 + R3
1.5V 2 × π × 30kHz × 1.5uH 10kΩ × 4kΩ
(FLC<FESR<FO) = × ×
5V 6.5mΩ 10kΩ + 4kΩ
If electrolytic capacitors are used as output =37.3kΩ
capacitors, typical design example of type III Choose R4=37.4kΩ.
compensator in which the crossover frequency is 7. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
selected as FLC<FESR<FO and F O<=1/10~1/5Fs is shown
as the following steps. Here two SANYO 16MV-WG1500 1
C2 =
with 13 mΩ is chosen as output capacitor. 2 × π × FZ1 × R 4
1. Calculate the location of LC double pole F LC 1
=
and ESR zero FESR. 2 × π × 0.75 × 2.3kHz × 37.4k Ω
= 2.4nF
1
FLC = Choose C2=2.2nF.
2 × π × LOUT × COUT 8. Calculate C 1 by equation (14) with pole F p2 at
1 half the switching frequency.
=
2 × π × 1.5uH × 3000uF 1
= 2.3kHz C1 =
2 × π × R 4 × FP2
1
1 =
FESR = 2 × π × 37.4kΩ × 150kHz
2 × π × ESR × COUT
= 28pF
1
=
2 × π × 6.5mΩ × 3000uF Choose C1=27pF.
= 8.2kHz

Rev.1.8 10
02/28/08
 NX2124/2124A
B. Type II compensator design
If the electrolytic capacitors are chosen as power Vout
stage output capacitors, usually the Type II compensa-
tor can be used to compensate the system. R2
Fb
Type II compensator can be realized by simple RC Ve
gm
circuit without feedback as shown in figure 6. R3 and C1
R1
introduce a zero to cancel the double pole effect. C2 R3
Vref
introduces a pole to suppress the switching noise. The C2
following equations show the compensator pole zero lo- C1
cation and constant gain.

R1
Gain=gm × × R3 ... (15)
R1+R2
Figure 7 - Type II compensator with
1
Fz = ... (16) transconductance amplifier
2 × π × R3 × C1
1
Fp ≈ ... (17) For this type of compensator, FO has to satisfy
2 × π × R3 × C2
FLC<FESR<<FO<=1/10~1/5Fs.
The following is parameters for type II compensa-
tor design. Input voltage is 5V, output voltage is 1.8V,
output inductor is 1.5uH, output capacitors are two
power stage
1500uF with 13mΩ electrolytic capacitors.
Gain(db)

1.Calculate the location of LC double pole F LC

40dB/decade
and ESR zero FESR.

1
loop gain FLC =
2 × π × L OUT × COUT
1
20dB/decade =
2 × π × 1.5uH × 3000uF
= 2.3kHz

compensator 1
FESR =
Gain 2 × π × ESR × C OUT
1
=
2 × π × 6.5m Ω × 3000uF
= 8.2kHz
FZ FLC FESR FO FP
2.Set R2 equal to 1kΩ.
R 2 × VREF 1kΩ × 0.8V
Figure 6 - Bode plot of Type II compensator R1 = = = 800Ω
VOUT -VREF 1.8V-0.8V
Choose R1=800Ω.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
4.Calculate R3 value by the following equation.

Rev.1.8 11
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 NX2124/2124A
Vout
4.Calculate R3 value by the following equation.
R2
V 2 × π × FO × L 1 VOUT Fb
R3 = OSC × × ×
Vin RESR gm VREF
1.5V 2 × π × 30kHz × 1.5uH 1 R1
= × × Vref
5V 6.5mΩ 2.0mA/V
1.8V
×
0.8V Voltage divider
=14.6kΩ
Figure 8 - Voltage divider
Choose R 3 =14.7kΩ.
5. Calculate C1 by setting compensator zero FZ Input Capacitor Selection
at 75% of the LC double pole. Input capacitors are usually a mix of high frequency
1 ceramic capacitors and bulk capacitors. Ceramic ca-
C1=
2 × π × R 3 × Fz pacitors bypass the high frequency noise, and bulk ca-
1 pacitors supply switching current to the MOSFETs. Usu-
=
2 × π × 14.7kΩ × 0.75 × 2.3kHz ally 1uF ceramic capacitor is chosen to decouple the
=6.3nF
high frequency noise.The bulk input capacitors are de-
Choose C1=6.8nF. cided by voltage rating and RMS current rating. The RMS
6. Calculate C 2 by setting compensator pole Fp current in the input capacitors can be calculated as:
at half the swithing frequency.
IRMS = IOUT × D × 1- D
1
C2= VOUT
π × R 3 × Fs D=
VIN ...(19)
1
=
p × 1 4 .7k Ω × 3 0 0 k H z VIN = 5V, VOUT=1.8V, IOUT=9A, using equation (19),
=72pF the result of input RMS current is 4.3A.
Choose C1=68pF. For higher efficiency, low ESR capacitors are rec-
ommended. One Sanyo OS-CON 16SP270M 16V 270uF
18mΩ with 4.4A RMS rating are chosen as input bulk
Output Voltage Calculation capacitors.
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed Power MOSFETs Selection
at 0.8V. The divider consists of two ratioed resistors The power stage requires two N-Channel power
so that the output voltage applied at the Fb pin is 0.8V MOSFETs. The selection of MOSFETs is based on
when the output voltage is at the desired value. The maximum drain source voltage, gate source voltage,
following equation and picture show the relationship maximum current rating, MOSFET on resistance and
between VOUT , VREF and voltage divider.. power dissipation. The main consideration is the power
R 2 × VR E F loss contribution of MOSFETs to the overall converter
R 1=
V O U T -V R E F ...(18) efficiency. In this design example, two IRFR3706 are
where R 2 is part of the compensator, and the used. They have the following parameters: V DS=30V, ID
value of R1 value can be set by voltage divider. =75A,RDSON =9mΩ,QGATE =23nC.
See compensator design for R1 and R2 selection. There are two factors causing the MOSFET power
loss:conduction loss, switching loss.
Conduction loss is simply defined as:
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 NX2124/2124A

PHCON =IOUT 2 × D × RDS(ON) × K 360mV

ISET =
K × RDSON
PLCON =IOUT 2 × (1 − D) × RDS(ON) × K ...(20)
If MOSFET RDSON=9mΩ, the worst case thermal
PTOTAL =PHCON + PLCON
consideration K=1.5, then
where the RDS(ON) will increases as MOSFET junc- 320mV 360mV
ISET = = = 26.7A
tion temperature increases, K is RDS(ON) temperature K × RDSON 1.5 × 9mΩ
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4 Layout Considerations
at 125oC according to IRFR3706 datasheet. Conduc-
The layout is very important when designing high
tion loss should not exceed package rating or overall
frequency switching converters. Layout will affect noise
system thermal budget.
pickup and can cause a good design to perform with
Switching loss is mainly caused by crossover con-
less than expected results.
duction at the switching transition. The total switching
There are two sets of components considered in
loss can be approximated.
the layout which are power components and small sig-
1
PSW = × VIN × IOUT × TSW × FS ...(21) nal components. Power components usually consist of
2 input capacitors, high-side MOSFET, low-side MOSFET,
where IOUT is output current, TSW is the sum of TR inductor and output capacitors. A noisy environment is
and TF which can be found in mosfet datasheet, and FS generated by the power components due to the switch-
is switching frequency. Switching loss PSW is frequency ing power. Small signal components are connected to
dependent. sensitive pins or nodes. A multilayer layout which in-
Also MOSFET gate driver loss should be consid- cludes power plane, ground plane and signal plane is
ered when choosing the proper power MOSFET. recommended .
MOSFET gate driver loss is the loss generated by dis- Layout guidelines:
charging the gate capacitor and is dissipated in driver 1. First put all the power components in the top
circuits.It is proportional to frequency and is defined as: layer connected by wide, copper filled areas. The input
Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(22) capacitor, inductor, output capacitor and the MOSFETs
where QHGATE is the high side MOSFETs gate should be close to each other as possible. This helps to
charge,QLGATE is the low side MOSFETs gate charge,VHGS reduce the EMI radiated by the power loop due to the
is the high side gate source voltage, and VLGS is the low high switching currents through them.
side gate source voltage. 2. Low ESR capacitor which can handle input RMS
This power dissipation should not exceed maxi- ripple current and a high frequency decoupling ceramic
mum power dissipation of the driver device. cap which usually is 1uF need to be practically touch-
ing the drain pin of the upper MOSFET, a plane connec-
Over Current Limit Protection tion is a must.
Over current Limit for step down converter is 3. The output capacitors should be placed as close
achieved by sensing current through the low side as to the load as possible and plane connection is re-
MOSFET. For NX2124, the current limit is decided by quired.
the RDSON of the low side mosfet. When synchronous 4. Drain of the low-side MOSFET and source of
FET is on, and the voltage on SW pin is below 360mV, the high-side MOSFET need to be connected thru a plane
the over current occurs. The over current limit can be ans as close as possible. A snubber nedds to be placed
calculated by the following equation. as close to this junction as possible.
5. Source of the lower MOSFET needs to be con-

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 NX2124/2124A
nected to the GND plane with multiple vias. One is not back to the resistor divider should not go through high
enough. This is very important. The same applies to the frequency signals.
output capacitors and input capacitors. 9. All GNDs need to go directly thru via to GND plane.
6. Hdrv and Ldrv pins should be as close to 10. The feedback part of the system should be kept
MOSFET gate as possible. The gate traces should be away from the inductor and other noise sources, and be
wide and short. A place for gate drv resistors is needed placed close to the IC.
to fine tune noise if needed. 11. In multilayer PCB, separate power ground and
7. Vcc capacitor, BST capacitor or any other by- analog ground. These two grounds must be connected
passing capacitor needs to be placed first around the IC together on the PC board layout at a single point. The
and as close as possible. The capacitor on comp to goal is to localize the high current path to a separate loop
GND or comp back to FB needs to be place as close to that does not interfere with the more sensitive analog con-
the pin as well as resistor divider. trol function.
8. The output sense line which is sensing output

TYPICAL APPLICATION

L2 1uH
Vin
+12V C3 C5 Cin
33uF 1uF 2 x 16SP180M

D1 MBR0530T1
Vin
C6
+5V 1uF 5 1
C4
Vcc BST 0.1uF
7 2 M1 IRF3706
Comp Hdrv
NX2124

M3
HI=SD C2 L1 1uH
C1 15nF
220pF 8 Vout
R4
SW +1.8V,20A
5k M2 Co
2 x (1500uF,13mohm)
6 4 2 x IRF3706
Fb Ldrv
C7 4.7nF
Gnd
3

R2 R1 1k
800

Figure 9 - High output current application of 2124

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 NX2124/2124A

SOIC8 PACKAGE OUTLINE DIMENSIONS

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 NX2124/2124A

Rev.1.8 16
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 NX2124/2124A

Customer Service
NEXSEM Inc.
500 Wald
Irvine, CA 92618
U.S.A.
Tel: (949)453-0714
Fax: (949)453-0713
WWW.NEXSEM.COM

Rev.1.8 17
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