LNBH25

LNB supply and control IC with step-up and I²C interface

Features
■ Complete interface between LNB and I²C bus
■ Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93 % @
0.5 A)
■ Selectable output current limit by external
resistor
■ Compliant with main satellite receivers output
voltage specification (15 programmable levels)
■ Accurate built-in 22 kHz tone generator suits QFN24 (4 x 4 mm)
widely accepted standards
■ 22 kHz tone waveform integrity guaranteed
also at no load condition
■ Low-drop post regulator and high efficiency
step-up PWM with integrated power N-MOS Description
allowing low power losses
Intended for analog and digital satellite
■ LPM function (low power mode) to reduce
receivers/Sat-TV and Sat-PC cards, the LNBH25
dissipation
is a monolithic voltage regulator and interface IC,
■ Overload and overtemperature internal assembled in QFN24 4x4 specifically designed to
protections with I²C diagnostic bits provide the 13/18 V power supply and the 22 kHz
■ LNB short-circuit dynamic protection tone signalling to the LNB down-converter in the
antenna dish or to the multi-switch box. In this
■ +/- 4 kV ESD tolerant on output power pins
application field, it offers a complete solution with
extremely low component count and low power
Applications dissipation together with a simple design and I²C
standard interfacing.
■ STB satellite receivers
■ TV satellite receivers
■ PC card satellite receivers

Table 1. Device summary

Order code Package Packaging

LNBH25PQR QFN24 (4 x 4) Tape and reel

February 2012 Doc ID 022433 Rev 4 1/34

www.st.com 34
Contents LNBH25

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4
2.3 Data encoding by external DiSEqC envelope control
through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 LPM (low power mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 DiSEqC 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.9 Surge protections and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.10 FLT: fault flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.11 VMON: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.12 TMON: 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.13 TDET: 22 kHz tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.14 IMON: minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.15 PDO: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 8
2.16 Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 8
2.17 PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.18 ISW: inductor switching current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.19 COMP: boost capacitor ESR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.20 OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 9
2.21 OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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LNBH25 Contents

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2 Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Doc ID 022433 Rev 4 3/34

Block diagram LNBH25

1 Block diagram

Figure 1. Block diagram

ADDR SCL SDA

LX
DSQIN
I2C Digital core

PWM CTRL
DETIN

Isense
Tone
DSQOUT detector

DAC
Drop control
PGND
Tone ctrl
FLT
Diagnostics
Protections VUP

BPSW

Gate ctrl
Current
Linear
Limit
Regulator VOUT
selection

Voltage
reference

GND BYP VCC ISEL AM10400v1

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LNBH25 Application information

2 Application information

This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V),
generates the voltages (Vup) that let the integrated LDO post-regulator (generating the 13 V
/18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum
dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at
Vup-VOUT = 1 V typ.). The LDO power dissipation can be further reduced when the 22 kHz
tone output is disabled by setting the LPM bit to “1” (see 2.4: LPM (low power mode)). The
IC is also provided with an undervoltage lockout circuit that disables the whole circuit when
the supplied VCC drops below a fixed threshold (4.7 V typ.). The step-up converter soft-start
function reduces the inrush current during start-up. The SS time is internally fixed at 4 ms
typ. to switch from 0 to 13 V and 6 ms typ. switch from 0 to 18 V.

2.1 DiSEqC data encoding (DSQIN pin)

The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards,
and can be activated in 3 different ways:
1. by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL
compatible). In this case the I²C Tone control bits must be set: EXTM = TEN = 1.
2. by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this
case the I²C Tone control bits must be set: EXTM = 0 and TEN = 1.
3. through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this
case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”.
Each of the above solutions requires that during the 22 kHz tone activation and/or DiSEqC
data transmission, the LPM bit must be set to “0” (see 2.4: LPM (low power mode)).

2.2 Data encoding by external 22 kHz tone TTL signal

In order to improve design flexibility an external tone signal can be input to the DSQIN pin by
setting the EXTM bit to “1”.
The DSQIN is a logic input pin which activates the 22 kHz tone to the VOUT pin, by using the
LNBH25 integrated tone generator.
The output tone waveforms are internally controlled by the LNBH25 tone generator in terms
of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is
used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz
signal is required for the proper control of the DSQIN pin function. Before sending the TTL
signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as
the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH25
activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL signal
activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has
expired (refer to Figure 2).

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Application information LNBH25

Figure 2. Tone enable and disable timing (using external waveform)

DSQIN

~ 60 µs
~ 1 µs
Tone
Output

AM10426v1

2.3 Data encoding by external DiSEqC envelope control through

the DSQIN pin
If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz
generator activated during the tone transmission by connecting the DiSEqC envelope
source to the DSQIN pin. In this case the I²C Tone control bits must be set: EXTM = 0 and
TEN = 1. In this way, the internal 22 kHz signal is superimposed to the VOUT DC voltage to
generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH,
the internal control circuit activates the 22 kHz tone output.
The 22 kHz tone on the VOUT pin is activated with about 6 µs delay from the DSQIN TTL
signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22
kHz TTL signal on DSQIN has expired (refer to Figure 3).

Figure 3. Tone enable and disable timing (using envelope signal)

DSQIN

~ 6 µs 15 µs ~ 60 µs
Tone
Output

AM10427v1

2.4 LPM (low power mode)

In order to reduce total power loss, the LNBH25 is provided with the LPM I²C bit that can be
activated (LPM=1) in applications where the 22 kHz tone can be disabled for long time
periods. The LPM bit can be set to “1” when the DiSEqC data transmission is not requested
(no 22 kHz tone output is present); at this condition the drop voltage across the integrated
LDO regulator (VUP-VOUT) is reduced to 0.6 V typ. and, consequently, the power loss inside
the LNBH25 linear regulator is reduced too. For example: at 500 mA load, LPM=1 allowing a
minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM bit to “0”
before starting the 22 kHz DiSEqC data transmission; at this condition the drop voltage
across the LDO is kept to 1 V typ. Keep LPM=0 at all times in case the LPM function is not
used.

2.5 DiSEqC 2.0 implementation

The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC 2.0 interfacing.
The input pin (DETIN) must be AC coupled to the DiSEqC BUS, and extracted PWK data is
available on the DSQOUT pin. To comply with the bi-directional DiSEqC 2.0 bus hardware

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LNBH25 Application information

requirements an output RL filter is needed. In order to avoid 22 kHz waveform distortion

during tone transmission, LNBH25 is provided with the BPSW pin to be connected to an
external transistor, which allows to bypass the output RL filter in DiSEqC 2.x applications
while in transmission mode. Before starting tone transmission by means of the DSQIN pin,
make sure that the TEN bit is preventively set to “1” and after ending tone transmission,
make sure that the TEN bit is set to “0”.

2.6 Output current limit selection

The linear regulator current limit threshold can be set by an external resistor connected to
the ISEL pin. The resistor value defines the output current limit by the equation:

Equation 1

13915
IMAX ( typ.) =
RSEL1.111

with ISET=0

Equation 2

6808
IMAX (typ.) =
RSEL1.068

with ISET=1
(Refer also to the ISET bit description in Table 9).
where RSEL is the resistor connected between ISEL and GND expressed in kΩ and
IMAX(typ.) is the typical current limit threshold expressed in mA. IMAX can be set up to 1 A.

2.7 Output voltage selection

The linear regulator output voltage level can be easily programmed in order to accomplish
application specific requirements, using 4 bits of an internal DATA 1 register (see 7.3: Data
registers and Table 14 for exact programmable values). Register writing is accessible via the
I²C bus.

2.8 Diagnostic and protection functions

LNBH25 has 8 diagnostic internal functions provided via the I²C bus, by reading 8 bits on
two STATUS registers (in read mode). All the diagnostic bits are, in normal operation (that is
no failure detected), set to LOW. Two diagnostic bits are dedicated to the overtemperature
and overload protection status (OTF and OLF) while the remaining 6 bits are dedicated to
the output voltage level (VMON), to 22 kHz tone characteristics (TMON), to the minimum
load current (IMON), to external voltage source presence on the VOUT pin (PDO), to the
input voltage Power Not Good function (PNG) and to the 22 kHz tone presence on the
DETIN pin (TDET). Once the OLF (or OTF or PNG) bit has been activated (set to “1”), it is
latched to “1” until relevant cause is removed and a new register reading operation is done.

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Application information LNBH25

2.9 Surge protections and TVS diodes

The LNBH25 device is directly connected to the antenna cable in a set-top box. Atmospheric
phenomenon can cause high voltage discharges on the antenna cable causing damage to
the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an
external (outdoor) circuit. This leads to currents or electromagnetic fields causing high
voltage or current transients. Transient voltage suppressor (TVS) devices are usually
placed, as shown in the following schematic, to protect the STB output circuits where the
LNBH25 and other devices are electrically connected to the antenna cable.

Figure 4. Surge protection circuit

For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically
designed by ST. The selection of LNBTVS diodes should be made based on the maximum
peak power dissipation that the diode is capable of supporting (see Ppp (W) parameter in
the LNBTVS datasheet for further details).

2.10 FLT: fault flag

In order to get an immediate feedback on diagnostic status, LNBH25 is equipped with a
dedicated fault flag pin (FLT). In the case of overload (OLF bit=1) or overheating (OTF bit=1)
or if Power No Good (PNG bit=1) condition is detected, the FLT pin (open drain output) is set
to low and is kept low until the relevant activating diagnostic bit is cleared. Be aware that
diagnostic bits OLF, OTF and PNG, once activated, are kept latched to “1” until the cause
origin is removed and a new register reading operation is performed by the microprocessor.
The FLT pin must be connected to a positive voltage (5 V max.) by means of a pull-up
resistor.

2.11 VMON: output voltage diagnostic

When device output voltage is activated (VOUT pin), its value is internally monitored and, as
long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to “1”.
See Table 17 for more details.

2.12 TMON: 22 kHz tone diagnostic

The 22 kHz tone can be internally detected and monitored if the DETIN pin is connected to
the LNB output bus (see typical application circuit in Figure 7) through a decoupling
capacitor.
The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz tone amplitude
and/or the tone frequency is out of the guaranteed limits (see Table 19), the TMON I²C bit is
set to “1”.

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LNBH25 Application information

2.13 TDET: 22 kHz tone detection

When a 22 kHz tone presence is detected on the DETIN pin, the TDET I²C bit is set to “1”.

2.14 IMON: minimum output current diagnostic

In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH25 is provided with a minimum output current flag by the
IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than
12 mA (typ.). It is recommended to use IMON function only with the 22 kHz tone
transmission deactivated, otherwise the IMON bit could be set to “0” even if the output
current is below the minimum current threshold. To activate IMON diagnostic function, set to
“1” the EN_IMON I²C bit in the DATA 4 register. Be aware that as soon as the IMON function
is activated by means of EN_IMON=1, the VOUT is immediately increased to 21 V (typ.)
independently on the VSEL bit setting. This operation is applied in order to be sure that the
LNBH25 output has the higher voltage present in the LNB bus. Do not use this function in an
application environment where 21 V voltage level is not supported by other peripherals
connected to the LNB bus.

2.15 PDO: overcurrent detection on output pull-down stage

When an overcurrent occurs on the pull-down output stage due to an external voltage
source greater than LNBH25 nominal VOUT and for a time longer than ISINK_TIME-OUT (10
ms typ.), the PDO I²C bit is set to “1”. This may happen due to an external voltage source
present on the LNB output (VOUT pin).
For current threshold and deglitch time details, see Table 13.

2.16 Power-on I²C interface reset and undervoltage lockout

The I²C interface built into LNBH25 is automatically reset at power-on. As long as the VCC
stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not
respond to any I²C command and all DATA register bits are initialized to zeroes, therefore
keeping the power blocks disabled. Once the VCC rises above 4.8 V typ. the I²C interface
becomes operative and the DATA registers can be configured by the main microprocessor.

2.17 PNG: input voltage minimum detection

When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds,
the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to Table 13 for threshold details.

2.18 ISW: inductor switching current limit

In order to allow low saturation current inductors to be used, the maximum DC-DC inductor
switching current limit threshold can be set by means of one I²C bit (ISW). Two values are
available: 2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).

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Application information LNBH25

2.19 COMP: boost capacitor ESR

DC-DC converter compensation loop can be optimized in order to work well with high or low
ESR capacitors (on the VUP pin). For this purpose, one I²C bit in the DATA 4 register
(COMP) can be set to “1” or “0”. It is recommended to reset this bit to “0” unless using high
ESR capacitors.

2.20 OLF: overcurrent and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition,
the device is provided with a dynamic short-circuit protection. It is possible to set the short-
circuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C DATA 3 register. When the PCL (pulsed current limiting) bit is set Io LOW, the
overcurrent protection circuit works dynamically: as soon as an overload is detected, the
output current is provided for TON time (90 ms or 180 ms typ., according to the TIMER bit
programmed in the DATA 3 register) and after that, the output is set in shutdown for TOFF
time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system register is
set to “1” and the FLT pin is set to low level. After this time has elapsed, the output is
resumed for a time TON. At the end of TON, if the overload is still detected, the protection
circuit cycles again through TOFF and TON. At the end of a full TON in which no overload is
detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after a
register reading is done. Typical TON +TOFF time is 990 ms (if TIMER=0) or 1080 ms (if
TIMER=1) and an internal timer determines it. This dynamic operation can greatly reduce
the power dissipation in short-circuit condition, still ensuring excellent power-on startup in
most conditions. However, there could be some cases in which a highly capacitive load on
the output may cause a difficult startup when the dynamic protection is chosen. This can be
solved by initiating any power startup in static mode (PCL=1) and, then, switching to the
dynamic mode (PCL=0) after a chosen amount of time depending on the output
capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to
low) when the current clamp limit is reached and returns LOW when the overload condition
is cleared and register reading is done.
After the overload condition is removed, normal operation can be resumed in two ways,
according to the OLR I²C bit on the DATA 4 register.
If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To re-
enable output stage, the VSEL bits must be set again by the microprocessor, and the OLF
bit is reset to “0” after a register reading operation.
If OLR=0, output is automatically re-enabled as soon as the overload condition is removed,
and the OLF bit is reset to “0” after a register reading operation.

2.21 OTF: thermal protection and diagnostic

The LNBH25 is also protected against overheating: when the junction temperature exceeds
150 °C (typ.), the step-up converter and the linear regulator are shut off, the diagnostic OTF
bit in the STATUS1 register is set to “1” and the FLT pin is set to low level. After the
overtemperature condition is removed, normal operation can be resumed in two ways,
according to the THERM I²C bit on the DATA 4 register.
If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To re-
enable output stage, the VSEL bits must be set again by the microprocessor, while the OTF
bit is reset to “0” after a register reading operation.
If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is
removed, while the OTF bit is reset to “0” after a register reading operation.

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LNBH25 Pin configuration

3 Pin configuration

Figure 5. Pin connections (top view)

24 23 22 21 20 19

NC DSQOUT DSQIN/
DSQIN VUP VOUT DETIN
EXTM

1 NC BPSW 18

2 FLT VCC 17

3 LX-A
LX VBYP 16

4 PGND GND 15

5 NC NC 14

6 ADDR NC 13

SCL SDA ISEL NC NC NC

7 8 9 10 11 12 AM09909v1

Table 2. Pin description

Pin n° Symbol Name Pin function

Open drain output for IC fault conditions. It is set low in case of

2 FLT FLT overload (OLF bit) or overheating status (OTF bit) or power not good
(PNG) is detected. To be connected to pull-up resistor (5 V max.).
3 LX N-MOS drain Integrated N-channel Power MOSFET drain.
DC-DC converter power ground. To be connected directly to the
4 P-GND Power ground
Epad.
Two I²C bus addresses available by setting the address pin level
6 ADDR Address setting
voltage. See Table 16.
7 SCL Serial clock Clock from I²C BUS.
8 SDA Serial data Bi-directional data from/to I²C BUS.
The resistor “RSEL” connected between ISEL and GND defines the
linear regulator current limit threshold. Refer to Section 2.6 in the
9 ISEL Current selection
Application Information section. Also see the ISET bit description in
Table 9.
15 GND Analog ground Analog circuits ground. To be connected directly to the Epad.
Needed for internal pre-regulator filtering. The BYP pin is intended
only to connect an external ceramic capacitor. Any connection of
16 BYP Bypass capacitor
this pin to external current or voltage sources may cause permanent
damage to the device.
17 VCC Supply input 8 to 16 V IC DC-DC power supply.

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Pin configuration LNBH25

Table 2. Pin description (continued)

Pin n° Symbol Name Pin function

To be connected to an external transistor to be used to bypass the

output RL filter needed in DiSEqC 2.x applications during the
18 BPSW Switch control
DiSEqC transmitting mode (see Section 5). Set to ground if not
used. Open drain pin.
Tone detector 22 kHz tone decoder input open drain pin, must be AC coupled to
19 DETIN
input the DiSEqC 2.0 bus. Set to ground if not used.
Output of the integrated very low drop linear regulator. See Table 14
20 VOUT LNB output port
for voltage selections and description.
Input of the linear post-regulator. The voltage on this pin is
21 VUP Step-up voltage monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.
It can be used as DiSEqC envelope input or external 22 kHz TTL
DSQIN for input depending on the EXTM I²C bit setting as follows:
DiSEqC envelope EXTM=0, TEN=1: it accepts the DiSEqC envelope code from the
input main microcontroller. The LNBH25 uses this code to modulate the
22 DSQIN
or internally generated 22 kHz carrier.
External 22 kHz If EXTM=TEN=1: it accepts external 22 kHz logic signals which
TTL input activate the 22 kHz tone output (refer to Section 2.3).
Pull-up high if the tone output is activated only by the TEN I²C bit.
Open drain output of the tone detector to the main microcontroller
23 DSQOUT DiSEqC output for DiSEqC 2.0 data decoding. It is low when tone is detected to the
DETIN input pin. Set to ground if not used.
To be connected with power grounds and to the ground layer
Epad Epad Exposed pad
through vias to dissipate the heat.
1, 5, 10, 11, Not internally Not internally connected pins. These pins can be connected to GND
N.C.
12, 13, 14, 24 connected to improve thermal performances.

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LNBH25 Maximum ratings

4 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC power supply input voltage pins -0.3 to 20 V

VUP DC input voltage -0.3 to 40 V
IOUT Output current Internally limited mA
VOUT DC output pin voltage -0.3 to 40 V
VI Logic input pins voltage (SDA, SCL, DSQIN, ADDR pins) -0.3 to 7 V
VO Logic output pins voltage (FLT, DSQOUT) -0.3 to 7 V
VBPSW BPSW pin voltage -0.3 to 40 V
VDETIN Detector input signal amplitude -0.6 to 2 V
IO Logic output pins current (FLT, DSQOUT, BPSW) 10 mA
LX LX input voltage -0.3 to 30 V
VBYP Internal reference pin voltage -0.3 to 4.6 V
ISEL Current selection pin voltage -0.3 to 3.5 V
TSTG Storage temperature range -50 to 150 °C
TJ Operating junction temperature range -25 to 125 °C
ESD rating with human body model (HBM) all pins, unless power output
2
ESD pins kV
ESD rating with human body model (HBM) for power output pins 4

Table 4. Thermal data

Symbol Parameter Value Unit

RthJC Thermal resistance junction-case 2 °C/W

Thermal resistance junction-ambient with device soldered on 2s2p 4-
RthJA 40 °C/W
layer PCB provided with thermal vias below exposed pad.

Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to network ground terminal.

Doc ID 022433 Rev 4 13/34

Typical application circuits LNBH25

5 Typical application circuits

Figure 6. DiSEqC 1.x application circuit

D2

to LNB
21 Vup
Vout 20

D1
C2 C3 C5 D3

3 LX
LNBH25
L1

Vin 17 Vcc
12V C1 C4

DiSEqC
22KHz TTL
22 DSQIN
or
DiSEqC
6 ADDR
Envelope TTL

{
8 SDA
I 2C Bus
7 SCL FLT 2

R1 (RSEL)
9 ISEL P-GND A -GND Byp 16

4 15 C7
AM10431v1

Table 5. DiSEqC 1.X bill of material

Component Notes

R1 (RSEL) SMD resistor. Refer to Table 13 and ISEL pin description in Table 2
C1, C2 > 25 V electrolytic capacitor, 100 µF is suitable.
C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.
C5 From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.
C4, C7 220 nF ceramic capacitors.
D1 STPS130A or similar schottky diode.
BAT54, BAT43, 1N5818, or any low power schottky diode with IF (AV) > 0.2 A,
D3
VRRM > 25 V, VF < 0.5 V. To be placed as close as possible to VOUT pin.
D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier.
L1 10 µH inductor with Isat > Ipeak where Ipeak is the boost converter peak current.

14/34 Doc ID 022433 Rev 4

LNBH25 Typical application circuits

Figure 7. DiSEqC 2.x application circuit

D2

to LNB
L2
21 Vup
Vout 20

D1 15 Ω
C2 C3
C5 D3

3 LX
LNBH25
4.7k TR1

L1 BPSW 18

4.7k
C6

Vin 17 Vcc DETIN 19

10k
12V C1 C4

DiSEqC
22KHz TTL
22 DSQIN
or
DiSEqC Open drains
6 ADDR
Envelope TTL to µController
DSQOUT

{
23
8 SDA
I2C Bus
7 SCL FLT 2

R1 (RSEL)
9 ISEL P-GND A
-GND Byp 16

4 15 C7

AM10432v1

Table 6. DiSEqC 2.x bill of material

Component Notes

R1 (RSEL) SMD resistors. Refer to Table 13 and ISEL pin description in Table 2
C1, C2 > 25 V electrolytic capacitor, 100 µF is suitable.
C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.
C5 From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.
C4, C7 220 nF ceramic capacitors.
C6 10 nF ceramic capacitors.
D1 STPS130A or similar schottky diode.
BAT54, BAT43, 1N5818, or any low power schottky diode with IF (AV) > 0.2 A,
D3
VRRM > 25 V, VF < 0.5 V. To be placed as close as possible to VOUT pin.
D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier.
L1 10 µH inductor with Isat > Ipeak where Ipeak is the boost converter peak current.
L2 220 µH inductor.
2STR2160 or 2STF2340 or any small power PNP with, IC > 250 mA, VCE > 30 V can
be used.
TR1
Also any small power PMOS with ID > 250 mA, RDSON < 0.5Ω, VDS > 20 V, can be
used.

Doc ID 022433 Rev 4 15/34

I²C bus interface LNBH25

6 I²C bus interface

Data transmission from the main microprocessor to the LNBH25 and vice versa takes place
through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors
to positive supply voltage must be externally connected).

6.1 Data validity

As shown in Figure 8, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.

6.2 Start and stop condition

As shown in Figure 9, a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.

6.3 Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.

6.4 Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 10). The peripheral (LNBH25) which acknowledges
must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA
line is stable LOW during this clock pulse. The peripheral which has been addressed has to
generate acknowledge after the reception of each byte, otherwise the SDA line remains at
the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH25 won't generate
acknowledge if the VCC supply is below the undervoltage lockout threshold (4.7 V typ.).

6.5 Transmission without acknowledge

Avoiding to detect the acknowledges of the LNBH25, the microprocessor can use a simpler
transmission: it simply waits one clock without checking the slave acknowledging, and sends
the new data. This approach is of course less protected from misworking and decreases
noise immunity.

16/34 Doc ID 022433 Rev 4

LNBH25 I²C bus interface

Figure 8. Data validity on the I²C bus

Figure 9. Timing diagram of I²C bus

Figure 10. Acknowledge on the I²C bus

Doc ID 022433 Rev 4 17/34

I²C interface protocol LNBH25

7 I²C interface protocol

7.1 Write mode transmission

The LNBH25 interface protocol comprises:
● a start condition (S)
● a chip address byte with the LSB bit R/W = 0
● a register address (internal address of the first register to be accessed)
● a sequence of data (byte to write in the addressed internal register + acknowledge)
● the following bytes, if any, to be written in successive internal registers
● a stop condition (P). The transfer lasts until a stop bit is encountered
● the LNBH25, as slave, acknowledges every byte transfer.

Figure 11. Example of writing procedure starting with first data address 0x2 (a)

CHIP ADDRESS REGISTER ADDRESS

MSB LSB MSB LSB

R/W = 0
ACK

ACK

S 0 0 0 1 0 0 X 0 0 0 0 0 X X X

DATA 1 DATA 2 DATA 3 DATA 4

Add=0x2 Add=0x3 Add=0x4 Add=0x5
MSB LSB MSB LSB MSB LSB MSB LSB

EN_IMON
THERM
VSEL4
VSEL3
VSEL2
VSEL1

TIMER

COMP
EXTM

ACK

ACK

ACK
ACK

LPM
TEN

PCL
ISW
ISET

OLR
N/A
N/A
N/A
N/A
N/A

N/A
N/A
N/A
N/A

N/A
N/A

N/A
N/A
N/A
N/A
N/A
N/A

AM09913v2

ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see Chip Address in Table 16 for pin
selection) and to select the REGISTER Address (see Table 7).

a. The writing procedure can start from any Register Address by simply setting the X values in the Register
Address byte (after the Chip Address). It can be also stopped from the master by sending a stop condition after
any acknowledge bit.

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LNBH25 I²C interface protocol

7.2 Read mode transmission

In Read mode the bytes sequence must be as follows:
● a start condition (S)
● a chip address byte with the LSB bit R/W=0
● the register address byte of the internal first register to be accessed
● a stop condition (P)
● a new master transmission with the chip address byte and the LSB bit R/W=1
● after the acknowledge the LNBH25 starts to send the addressed register content. As
long as the master keeps the acknowledge LOW, the LNBH25 transmits the next
address register byte content.
● the transmission is terminated when the master sets the acknowledge HIGH with a
following stop bit.

Figure 12. Example of reading procedure starting with first status address 0X0 (b)

CHIP ADDRESS REGISTER ADDRESS CHIP ADDRESS

MSB LSB MSB LSB MSB LSB

R/W = 0

R/W = 1
ACK

ACK

ACK
S 0 0 0 1 0 0 X 0 0 0 0 0 X X X P S 0 0 0 1 0 0 X

STATUS 1 STATUS 2
Add=0x0 Add=0x1
MSB LSB MSB LSB
TMON
VMON

TDET
IMON
PNG

PDO

ACK

ACK
OLF
OTF
N/A

N/A

N/A

N/A
N/A
N/A

N/A

N/A

DATA 1 DATA 2 DATA 3 DATA 4

Add=0x2 Add=0x3 Add=0x4 Add=0x5
MSB LSB MSB LSB MSB LSB MSB LSB
EN_IMON
THERM
VSEL4
VSEL3
VSEL2
VSEL1

TIMER

COMP
EXTM

ACK

ACK
ISET
ACK

ACK
PCL
TEN

ISW
LPM

OLR
N/A
N/A
N/A
N/A
N/A

N/A
N/A
N/A
N/A

N/A
N/A

N/A
N/A
N/A
N/A
N/A
N/A

AM09914v2

ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see Chip Address in Table 16 for pin
selection) and to select the REGISTER Address (see Table 7).

b. The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X
values in the register address byte (after the first Chip Address in the above figure). It can be also stopped from
the master by sending a stop condition after any acknowledge bit.

Doc ID 022433 Rev 4 19/34

I²C interface protocol LNBH25

7.3 Data registers

The DATA 1..4 registers can be addressed both in write and read mode. In read mode they
return the last writing byte status received in the previous write transmission.
The following tables provide the Register Address values of Data 1..4 and a function
description of each bit.

Table 7. DATA 1 (Read/Write register. Register address = 0X2)

BIT Name Value Description

Bit 0
VSEL1 0/1
(LSB)
Bit 1 VSEL2 0/1 Output voltage selection bits. (Refer to Table 14)
Bit 2 VSEL3 0/1
Bit 3 VSEL4 0/1
Bit 4 N/A 0 Reserved. Keep to "0"
Bit 5 N/A 0 Reserved. Keep to "0"
Bit 6 N/A 0 Reserved. Keep to "0"
Bit 7
N/A 0 Reserved. Keep to "0"
(MSB)

N/A = Reserved bit.

All bits reset to “0” at power-on.

Table 8. DATA 2 (Read/Write register. Register address = 0X3)

BIT Name Value Description

Bit 0 1 22 kHz tone enabled. Tone output controlled by DSQIN pin

TEN
(LSB) 0 22 kHz tone output disabled
1 Low power mode activated (used only with 22 kHz tone output disabled)
Bit 1 LPM Low power mode deactivated (keep always LPM = 0 during 22 kHz tone
0
transmission)
1 DSQIN input pin is set to receive external 22 kHz TTL signal source
Bit 2 EXTM
0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal
Bit 3 N/A 0 Reserved. Keep to “0”
Bit 4 N/A 0 Reserved. Keep to "0"
Bit 5 N/A 0 Reserved. Keep to "0"
Bit 6 N/A 0 Reserved. Keep to "0"
Bit 7
N/A 0 Reserved. Keep to "0"
(MSB)

N/A = Reserved bit.

All bits reset to 0 at power-on.

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LNBH25 I²C interface protocol

Table 9. DATA 3 (Read/Write register. Register address = 0X4)

BIT Name Value Description

Current limit of LNB output (VOUT pin) set to lower current range.
1
Bit 0 Refer to Section 2.6 in Application Information section.
ISET
(LSB) Current Limit of LNB output (VOUT pin) set to default range.
0
Refer to Section 2.6 in Application Information section.
1 DC-DC, inductor switching current limit set to 2.5 A typ.
Bit 1 ISW
0 DC-DC, inductor switching current limit set to 4 A typ.
1 Pulsed (Dynamic) LNB output current limiting is deactivated
Bit 2 PCL
0 Pulsed (Dynamic) LNB output current limiting is activated
1 Pulsed (Dynamic) LNB output current TON time set to 180 ms typ.
Bit 3 TIMER
0 Pulsed (Dynamic) LNB output current TON time set to 90 ms typ.
Bit 4 N/A 0 Reserved. Keep to "0"
Bit 5 N/A 0 Reserved. Keep to "0"
Bit 6 N/A 0 Reserved. Keep to "0"
Bit 7
N/A 0 Reserved. Keep to "0"
(MSB)

N/A = Reserved bit.

All bits reset to 0 at power-on.

Table 10. DATA 4 (Read/Write register. Register address = 0X5)

BIT Name Value Description

Bit 0 1 IMON Diagnostic function is enabled. (VOUT is set to 21 V typ.)

EN_IMON
(LSB) 0 IMON Diagnostic function is disabled, keep always at “0” if IMON is not used
Bit 1 N/A - Reserved
Bit 2 N/A - Reserved
In case overload protection activation (OLF=1), all VSEL 1..4 bits are reset to “0”
1 and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the
master after the overcurrent condition is removed (OLF=0).
Bit 3 OLR
In case of overload protection activation (OLF=1) the LNB output (VOUT pin) is
0 automatically enabled as soon as the overload conditions is removed (OLF=0)
with the previous VSEL bits setting.
Bit 4 N/A - Reserved
Bit 5 N/A - Reserved

Doc ID 022433 Rev 4 21/34

I²C interface protocol LNBH25

Table 10. DATA 4 (Read/Write register. Register address = 0X5) (continued)

BIT Name Value Description

If Thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and
1 LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master
after the overtemperature condition is removed (OTF=0).
Bit 6 THERM
In case of Thermal protection activation (OTF=1) the LNB output (VOUT pin) is
0 automatically enabled as soon as the overtemperature condition is removed
(OTF=0) with the previous VSEL bits setting.

Bit 7 1 DC-DC converter compensation set to use HIGH ESR capacitors (VUP pin)
COMP
(MSB) 0 DC-DC converter compensation set to use LOW ESR capacitors (VUP pin)

N/A = Reserved bit.

All bits reset to 0 at power-on.

7.4 Status registers

The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic
functions described in the following tables.

Table 11. STATUS 1 (Read register. Register address = 0X0)

BIT Name Value Description

VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 9 for
Bit 0 1
OLF the overload operation settings (ISET, PCL, TIMER bits).
(LSB)
0 No overload protection has been triggered to the VOUT pin (IOUT < IMAX).
Bit 1 N/A - Reserved
Output voltage (VOUT pin) lower than VMON specification thresholds. Refer to
1
Bit 2 VMON Table 17.
0 Output voltage (VOUT pin) is within the VMON specifications.
Bit 3 N/A - Reserved
Overcurrent detected on output pull-down stage for a time longer than the deglitch
1 period. This may happen due to an external voltage source present on the LNB
Bit 4 PDO output (VOUT pin).
0 No overcurrent detected on output pull-down stage.
Bit 5 N/A - Reserved
Junction overtemperature is detected, TJ > 150 °C. See also THERM bit setting in
1
Table 10.
Bit 6 OTF
Junction overtemperature not detected, TJ < 135 °C. TJ is below thermal
0
protection threshold.

Bit 7 1 Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to Table 13.
PNG
(MSB) 0 Input voltage (VCC pin) higher than LPD thresholds. Refer to Table 13.

N/A = Reserved bit.

All bits reset to 0 at power-on.
22/34 Doc ID 022433 Rev 4
LNBH25 I²C interface protocol

Table 12. STATUS 2 (Read register. Register address = 0X1)

BIT Name Value Description

Bit 0 1 22 kHz tone presence is detected on the DETIN pin

TDET
(LSB) 0 No 22 kHz tone is detected on the DETIN pin
Bit 1 N/A - Reserved
22 kHz tone present on the DETIN pin is out of TMON specification thresholds.
1 That is: the tone frequency or the ATONE (tone Amplitude) are out of the thresholds
Bit 2 TMON guaranteed in the TMON electrical characteristics table.
22 kHz tone present on the DETIN pin is within TMON specification thresholds.
0
Refer to Table 19.
Bit 3 N/A - Reserved
Output current (from VOUT pin) is lower than IMON specification thresholds. Refer
1
to Table 18.
Bit 4 IMON
Output current (from VOUT pin) is higher than IMON specifications. Refer
0
toTable 18.
Bit 5 N/A - Reserved
Bit 6 N/A - Reserved
Bit 7
N/A - Reserved
(MSB)

N/A = Reserved bit.

All bits reset to 0 at power-on.

Doc ID 022433 Rev 4 23/34

Electrical characteristics LNBH25

8 Electrical characteristics

Refer to Section 5, TJ from 0 to 85 °C, all DATA 1..4 register bits set to 0 unless VSEL1 = 1,
RSEL = 11.5 kΩ, DSQIN = LOW, VIN = 12 V, IOUT = 50 mA, unless otherwise stated. Typical
values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See software description section
for I²C access to the system register (Section 6 and Section 7).

Table 13. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIN Supply voltage (1) 8 12 16 V

IOUT = 0 mA 6 mA
22 kHz Tone enabled (TEN=1),
IIN Supply current 10 mA
DSQIN = High, IOUT= 0 mA
VSEL1=VSEL2=VSEL3=VSEL4=0 1 mA
VOUT Output voltage total accuracy Valid at any VOUT selected level -3.5 +3.5 %
VOUT Line regulation VIN = 8 to 16 V 40
mV
VOUT Load regulation IOUT from 50 to 750 mA 100
RSEL = 11.5 kΩ, ISET = 0 750 1100
Output current limiting
IMAX RSEL = 16.2 kΩ, ISET = 0 500 750 mA
thresholds
RSEL = 22 kΩ, ISET = 0 350 550
RSEL = 11.5 kΩ, ISET = 1 500
Output current limiting
IMAX RSEL = 16.2 kΩ, ISET = 1 350 mA
thresholds
RSEL = 22 kΩ, ISET = 1 250
ISC Output short-circuit current RSEL = 11.5 kΩ, ISET= 0 500 mA
SS Soft-start time VOUT from 0 to 13 V 4 ms
SS Soft-start time VOUT from 0 to 18 V 6 ms
T13-18 Soft transition rise time VOUT from 13 to 18 V 1.5 ms
T18-13 Soft transition fall time VOUT from 18 to 13 V 1.5 ms
Dynamic overload protection
TOFF PCL=0, Output Shorted 900
OFF Time
ms
Dynamic overload protection PCL = TIMER = 0, Output Shorted TOFF/10
TON
ON Time PCL = 0, TIMER = 1, Output Shorted TOFF/5
DSQIN=High, EXTM=0, TEN=1
ATONE Tone amplitude IOUT from 0 to 750 mA 0.55 0.675 0.8 VPP
CBUS from 0 to 750 nF
FTONE Tone frequency 20 22 24 kHz
DTONE Tone duty cycle DSQIN=High, EXTM=0, TEN=1 43 50 57 %
tr, tf Tone rise or fall time (2)
5 8 15 µs
EffDC/DC DC-DC converter efficiency IOUT = 500 mA 93 %

24/34 Doc ID 022433 Rev 4

LNBH25 Electrical characteristics

Table 13. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

DC-DC converter switching

FSW 440 kHz
frequency

Undervoltage lockout UVLO Threshold Rising 4.8

UVLO V
thresholds UVLO Threshold Falling 4.7

Low power diagnostic (LPD) VLP Threshold Rising 7.2

VLP V
thresholds VLP Threshold Falling 6.7
VIL DSQIN, pin logic low 0.8 V
VIH DSQIN, pin logic high 2 V
IIH DSQIN, pin input current VIH = 5 V 15 µA
Tone detector frequency
FDETIN 0.4VPP sine wave 19 22 25 kHz
capture range (3)
Tone detector input
VDETIN Sine wave signal, 22 kHz 0.3 1.5 VPP
amplitude (3)
Tone detector input
ZDETIN 150 kΩ
impedance
VOL_BPS IOL_BPSW = 5 mA, DSQIN = high,
BPSW pin low voltage 0.7 V
W EXTM=0, TEN=1
DSQOUT, FLT pins logic
VOL DETIN Tone present, IOL= 2 mA 0.3 0.5 V
LOW
DSQOUT, FLT pins leakage
IOZ DETIN Tone absent, VOH = 6 V 10 µA
current
IOBK Output backward current All VSELx=0, VOBK = 30 V -3 -6 mA
ISINK Output low-side sink current VOUT forced at VOUT_NOM + 0.1 V 70 mA
VOUT forced at VOUT_NOM + 0.1 V
ISINK_ Low-side sink current time-
PDO I²C bit is set to 1 after this time 10 ms
TIME-OUT out
is elapsed
VOUT forced at VOUT_NOM + 0.1 V
IREV Max. reverse current after PDO bit is set to 1 2 mA
(ISINK_TIME-OUT elapsed)
Thermal shut-down
TSHDN 150 °C
threshold
Thermal shut-down
ΔTSHDN 15 °C
hysteresis
1. In applications where (VCC -VOUT) > 1.3 V the increased power dissipation inside the integrated LDO must be taken into
account in the application thermal management design.
2. Guaranteed by design.
3. Frequency range in which the DETIN function is guaranteed. The VPP level is intended on the LNB bus (before the C6
capacitor. See typical application circuit for DiSEqC 2.x). IOUT from 0 to 750 mA, CBUS from 0 to 750 nF.

Doc ID 022433 Rev 4 25/34

Electrical characteristics LNBH25

Table 14. Output voltage selection table (Data1 register, write mode) (1)
VOUT VOUT pin VOUT
VSEL4 VSEL3 VSEL2 VSEL1 Function
min. voltage max.

VOUT disabled. LNBH25 set in standby

0 0 0 0 0.000
mode
0 0 0 1 12.545 13.000 13.455
0 0 1 0 12.867 13.333 13.800
0 0 1 1 13.188 13.667 14.145
0 1 0 0 13.51 14.000 14.490
0 1 0 1 13.832 14.333 14.835
0 1 1 0 14.153 14.667 15.180
0 1 1 1 14.475 15.000 15.525

1 0 0 0 17.515 18.150 18.785

1 0 0 1 17.836 18.483 19.130
1 0 1 0 18.158 18.817 19.475
1 0 1 1 18.48 19.150 19.820
1 1 0 0 18.801 19.483 20.165
1 1 0 1 19.123 19.817 20.510
1 1 1 0 19.445 20.150 20.855
1 1 1 1 19.766 20.483 21.200
1. TJ from 0 to 85 °C, VI = 12 V.

TJ from 0 to 85 °C, VI = 12 V.

Table 15. I²C electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL LOW level input voltage SDA, SCL 0.8 V

VIH HIGH level input voltage SDA, SCL 2 V
IIN Input current SDA, SCL, VIN = 0.4 to 4.5 V -10 10 µA
VOL (1)
Low level output voltage SDA (open drain), IOL = 6 mA 0.6 V
FMAX Maximum clock frequency SCL 400 kHz
1. Guaranteed by design.

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LNBH25 Electrical characteristics

TJ from 0 to 85 °C, VI = 12 V.

Table 16. Address pin characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

“0001000(R/W)” Address pin R/W bit determines the transmission

VADDR-1 0 0.8 V
voltage range mode: read (R/W=1) write (R/W=0)
“0001001(R/W)” Address pin R/W bit determines the transmission
VADDR-2 2 5 V
voltage range mode: read (R/W=1) write (R/W=0)

Refer to Section 5, TJ from 0 to 85°C, All DATA 1..4 register bits set to “0”, RSEL = 11.5 kΩ,
DSQIN = LOW, VIN = 12 V, IOUT = 50 mA, unless otherwise stated. Typical values are
referred to TJ = 25 °C. VOUT = VOUT pin voltage. See software description section for I²C
access to the system register.

Table 17. Output voltage diagnostic (VMON bit, STATUS 1 register) characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit

Diagnostic low threshold at VSEL1=1,

VTH-L 80 90 95 %
VOUT = 13.0 V VSEL2 = VSEL3 = VSEL4 = 0
Diagnostic low threshold at VSEL4=1,
VTH-L 80 90 95 %
VOUT = 18.15 V VSEL1 = VSEL2 = VSEL3 = 0

Note: If the output voltage is lower than the min. value the VMON I²C bit is set to 1.
If VMON=0 then VOUT > 80 % of VOUT typical
If VMON=1 then VOUT < 95 % of VOUT typical
Refer to Section 5, TJ from 0 to 85 °C, RSEL = 11.5 kΩ, DSQIN = LOW, VIN = 12 V, unless
otherwise stated. Typical values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See
software description section for I²C access to the system register.

Table 18. Output current diagnostic (IMON bit, STATUS 2 register) characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit

Minimum current diagnostic

ITH EN_IMON = 1 (VOUT is set to 21 V typ.) 5 12 20 mA
threshold

Note: If the output current is lower than the min. threshold limit, the IMON I²C bit is set to 1. If the
output current is higher than the max. threshold limit, the IMON I²C bit is set to 0.

Doc ID 022433 Rev 4 27/34

Electrical characteristics LNBH25

Refer to Section 5, TJ from 0 to 85 °C, All DATA 1..4 register bits set to “0” unless
VSEL1 = 1, TEN=1, RSEL = 11.5 kΩ, DSQIN = HIGH, VIN = 12 V, IOUT = 50 mA, unless
otherwise stated. Typical values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See
software description section for I²C access to the system register.

Table 19. 22 kHz tone diagnostic (TMON bit, STATUS 2 register) characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit

ATH-L Amplitude diagnostic low threshold DETIN pin AC coupled 200 300 400 mV
Amplitude diagnostic high
ATH-H DETIN pin AC coupled 900 1100 1200 mV
threshold
Frequency diagnostic low
FTH-L DETIN pin AC coupled 13 16.5 20 kHz
thresholds
Frequency diagnostic high
FTH-H DETIN pin AC coupled 24 29.5 38 kHz
thresholds

Note: If the 22 kHz Tone parameters are lower or higher than the above limits, the TMON I²C bit is
set to “1”.

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LNBH25 Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.

Table 20. QFN24L (4 x 4 mm) mechanical data

(mm)
Dim.
Min. Typ. Max.

A 0.80 0.90 1.00

A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 3.90 4.00 4.10
D2 2.55 2.70 2.80
E 3.90 4.00 4.10
E2 2.55 2.70 2.80
e 0.45 0.50 0.55
L 0.25 0.35 0.45

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Package mechanical data LNBH25

Figure 13. QFN24L (4 x 4 mm) package dimensions

7596209_D

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LNBH25 Package mechanical data

Tape & reel QFNxx/DFNxx (4x4) mechanical data

mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.

A 330 12.992

C 12.8 13.2 0.504 0.519

D 20.2 0.795

N 99 101 3.898 3.976

T 14.4 0.567

Ao 4.35 0.171

Bo 4.35 0.171

Ko 1.1 0.043

Po 4 0.157

P 8 0.315

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Package mechanical data LNBH25

Figure 14. QFN24L (4 x 4) footprint recommended data (mm.)

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LNBH25 Revision history

10 Revision history

Table 21. Document revision history

Date Revision Changes

09-Nov-2011 1 Initial release.

Updated mechanical data Table 20 on page 29 and Table 13 on page 30.
01-Dec-2011 2
Added Section 2.9 and Figure 4 on page 8.
13-Jan-2012 3 Modified: header Table 14 on page 26 and test condition Table 17 on page 27.
15-Feb-2012 4 Modified: D1, D3 Table 5 on page 14 and Table 6 on page 15.

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 LNBH25

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