Introduction (cont.
Main components of a sequential circuit
Clock Signal
Clock Signal (cont.)
Clock serves two distinct purposes
¾ Synchronization point
Start of a cycle
End of a cycle
Intermediate point at which the clock signal changes
levels
¾ Timing information
Clock period, ON, and OFF periods
Propagation delay
¾ Time required for the output to react to changes in the
inputs
Clock Signal (cont.)
SR Latches
Can remember a bit
Level-sensitive (not edge-sensitive)
A NOR gate implementation of SR latch
SR Latches (cont.)
SR latch outputs follow inputs
In clocked SR latch, outputs respond at specific instances
¾ Uses a clock signal
D Latches
D Latch
¾ Avoids the SR = 11 state
Positive Edge-Triggered D Flip-Flops
Edge-sensitive devices
¾ Changes occur either at positive or negative edges
Notation for Latches & Flip-Flops
Not strictly followed in the literature
Latches Flip-flops
Low level High level Positive edge Negative edge
Example of Shift Register Using D Flip-Flops
74164 shift
Register chip
Memory Design Using D Flip-Flops
Require separate data in and out lines
JK Flip-Flops
JK flip-flop
(master-slave)
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Qn
Examples of D & JK Flip-Flops
Two example chips
D latches JK flip-flops
Example of Shift Register Using JK Flip-Flops
Shift Registers
¾ Can shift data left or right with each clock pulse
A 4-bit shift register using JK flip-flops
Example of Counter Using JK Flip-Flops
Counters
¾ Easy to build using JK flip-flops
Use the JK = 11 to toggle
¾ Binary counters
Simple
p designg
B bits can count from 0 to 2B−1
Ripple counter
Increased delay as in ripple-carry adders
Delay proportional to the number of bits
Synchronous counters
Output changes more or less simultaneously
Additional cost/complexity
Modulo-8 Binary Ripple Counter Using JK Flip-Flops
LSB
Synchronous Modulo-8 Counter
Designed using the following simple rule
¾ Change output if the preceding count bits are 1
Q1 changes whenever Q0 = 1
Q2 changes whenever Q1Q0 = 11
Example Counters
Sequential Circuit Design
Sequential circuit consists of
¾ A combinational circuit that produces output
¾ A feedback circuit
We use JK flip-flops for the feedback circuit
Si l counter
Simple t examples
l using
i JK flip-flops
fli fl
¾ Provides alternative counter designs
¾ We know the output
Need to know the input combination that produces
this output
Use an excitation table
Built from the truth table
Sequential Circuit Design (cont.)
Sequential Circuit Design (cont.)
Build a design table that consists of
¾ Current state output
¾ Next state output
¾ JK inputs for each flip-flop
Bi
Binary counter
t example
l
¾ 3-bit binary counter
¾ 3 JK flip-flops are needed
¾ Current state and next state outputs are 3 bits each
¾ 3 pairs of JK inputs
Sequential Circuit Design (cont.)
Design table for the binary counter example
Sequential Circuit Design (cont.)
Use K-
maps to
simplify
expression
s for JK
inputs
Sequential Circuit Design (cont.)
Final circuit for the binary counter example
¾ Compare this design with the synchronous counter design
Sequential Circuit Design (cont.)
A more general counter
design
¾ Does not step in sequence
0→3→5→7→6→0
Same design process
One significant change
¾ Missing states
1, 2, and 4
Use don’t cares for these
states
Sequential Circuit Design (cont.)
Design table
for the
general
counter
example
Sequential Circuit Design (cont.)
K-maps to
simplify JK
input
p
expressions
Sequential Circuit Design (cont.)
Final circuit for the general counter example
