Additional Modes down counter as these micro-operations use plus-one and

Module 1 Auto-increment mode: The effective address of the operand

is the contents of a register specified in the instruction. After
Module 2 minus-one operation respectively. The arithmetic add micro-
operations are defined by the statement:
ADDRESSING MODES accessing the operand, the contents of this register are Register transfer logic 𝐹 ← 𝐴 + 𝐵.
automatically incremented to point to the next item in a list. Logic Micro-Operations
The different ways for specifying the locations of instruction Register transfer logic is a means of describing the information
Auto-increment mode is written as (Ri)+
operands are known as addressing modes. flow and the processing task among the data stored in the Logic micro-operations specify binary operations for strings of
Auto-decrement mode: The contents of a register specified in
registers. bits stored in registers. These operations consider each bit of
Implementation of Variables and Constants the instruction are first automatically decremented and are
the register separately and treat them as binary variables. For
In assembly language, a variable is represented by allocating a then used as the effective address of the operand. The Auto- Components of Register Transfer Logic example, the exclusive-OR micro-operation with the contents
register or a memory location to hold its value. This value can increment mode is written as (Ri)-
1. The set of registers in the system and their functions: A of two registers A and B is symbolized by the statement:
be changed as needed using appropriate instructions. 𝐹 ← 𝐴 ⊕ 𝐵
Register mode: The operand is the contents of a processor
Addressing mode for representing: register also encompasses all type of registers including shift
registers, counters and memory units.
register; the name of the register is given in the instruction. Array - Indexed addressing mode Shift Micro-Operations
2. The binary-coded information stored in the registers: The
Example: The instruction 𝐴𝑑𝑑 𝑅4, 𝑅2, 𝑅3 uses the Register Pointers - Indirect addressing mode Shift micro-operations shift the contents of a register either
binary information stored in registers may be binary numbers,
mode for all three operands. Registers R2 and R3 hold the two Constants - Immediate addressing mode left or right. These micro-operations are generally used for
binary coded decimal numbers, alphanumeric characters,
source operands, while R4 is the destination. Variables - Direct Addressing mode serial transfer of data. They are also used along with
control information or any other binary coded information.
Absolute mode: The operand is in a memory location; the Loops – Auto-increment / decrement arithmetic, logic, and other data-processing operations. No
3. The operations performed on the information stored in the
address of this location is given explicitly in the instruction. conventional symbol for shift operation. Here adopt symbols
Single Bus organization of Processor registers: The operations performed on data stored in
Example: The Absolute mode is used in the instruction shl or shr [shl - shift left shr - shift right] for Example:
registers are called micro operations. Examples are shift,
𝐿𝑜𝑎𝑑 𝑅2, 𝑁𝑈𝑀1 which loads the value in the memory Figure shows the organization in which the arithmetic and 𝐴 ← 𝑠ℎ𝑙 𝐴 //1-bit shift to the left of register A
count, add, clear and load
location NUM1 into register R2. logic unit (ALU) and all the registers are interconnected via a 𝐵 ← 𝑠ℎ𝑟 𝐵 //1-bit shift to the right of register B
4. The control functions that initiate the sequence of
Immediate mode: Operand is given explicitly in instruction. single common bus. This bus is internal to the processor. operations: The control functions that initiate the sequence of
Example: The instruction 𝐴𝑑𝑑 𝑅4, 𝑅6, #200 adds the value
operations consists of timing signals that sequence the Scratchpad memory
200 to the contents of R6, and places the result into R4.
operations one at a time.
The most common ways to represent a register are: The register in a processor unit can be enclosed in a small
Indirection and Pointers memory unit. When included in a processor unit, a small
Some programs require a capability for modifying the address
memory is sometimes called a scratchpad memory. The use of
of the memory operand during each pass through the loop.
a small memory is a cheaper alternative to collecting
Indirect mode: The effective address of the operand is the processor registers through a bus system. The difference
contents of a register that is specified in the instruction. We between the two systems is the manner in which information
denote indirection by placing the name of the register given in is selected for transfer into the ALU. In a bus system, the
the instruction in parentheses.
information transfer is selected by the multiplexer that form
Example: To execute 𝐿𝑜𝑎𝑑 𝑅2, (𝑅5) instruction, the processor
the buses.
uses the value B, which is in register R5, as the effective Transfer Logic for a conditional control statement
address of the operand. It requests a Read operation to fetch
the contents of location B in the memory. Representation of a (conditional) transfer x’T1: A ← B. A
binary condition (x’T1 equals to 0 or 1) determines when the
Indexing and Arrays transfer occurs. In this the content of B is transferred into A
Index mode: The effective address of the operand is only if x is 0 and T1 is 1. Hardware implementation of a
generated by adding a constant value to the contents of a controlled transfer: x’T1: A ← B is as follows
register. The register used in this mode is referred as the index
register. We indicate the Index mode symbolically as X(Ri)
where X denotes a constant signed integer value contained in
the instruction and Ri is the name of the register involved. The
effective address of the operand is given byEA = X + [Ri]
Relative Addressing
In index addressing, if the program counter PC, is used instead
of a general-purpose register then X(PC) can be used to
address a memory location that is X bytes away from the
location presently pointed to by the program counter. ARITHMETIC, LOGIC AND SHIFT MICRO OPERATION
Relative mode: The effective address is determined by the Arithmetic Micro-Operation
Index mode using the program counter in place of the general- The basic arithmetic micro-operations are:
The data and address lines of the external memory bus are
purpose register Ri.  Addition,
connected to the internal processor bus via the memory data
This mode can be used to access data operands. But, its most
register, MDR, and the memory address register, MAR,  Subtraction,
common use is to specify the target address in branch
respectively. Register MDR has two inputs and two outputs.  Increment,
instructions. An instruction such as Branch>0 LOOP causes
Data may be loaded into MDR either from the memory bus or  Decrement
program execution to go to the branch target location
from the internal processor bus.  Arithmetic shift.
identified by the name LOOP if the branch condition is
The data stored in MDR may be placed on either bus. The The increment and decrement micro-operations are
satisfied.
input of MAR is connected to the internal bus, and its output implemented with a combinational circuit or with a binary up-

Hazards MICRO-PROGRAM CONTROL

Module 3 Pipeline hazards are situations that prevent the next
Module 4 In a micro-program control, the control variables that initiate
instruction in the instruction stream from executing during its micro-operations are stored in memory. The control memory
Booth's Multiplication Algorithm Working of a micro program sequencer
designated clock cycles. Any condition that causes a stall in the is usually a ROM, since the control sequence is permanent and
pipeline operations can be called a hazard. There are primarily Micro-program sequencer works in a way to generate the needs no alteration. The control variables stored in memory
three types of hazards: control signals from the microprogram by transitioning from are read one at a time to initiate the sequence of micro-
one state to another in every clock cycle. A state is defined by operations for the system.
Data Hazards: the micro-instruction that has to be run in that clock cycle. It
A data hazard is any condition in which either the source or has two main functions
the destination operands of an instruction are not available at 1. Control Function: The micro-operations that need to be
the time expected in the pipeline. As a result of which some executed to perform a certain microinstruction are to be
operation has to be delayed and the pipeline stalls. Whenever defined and be known. The micro-operation(s) are dependent
there are two instructions one of which depends on the data on parameters like selected destination, operand etc.
obtained from the other. 2. Sequencing Function: The address of next micro-instruction
Solution: Handling Data Hazards in Software to be executed is generated while controlling test conditions.
Let the compiler detect and handle the hazard: Thus, to summarize, to execute an instruction, the
I1: Mul R2, R3, R4 microprogram sequencer executes a micro-instruction in
NOP every clock cycle and determines which micro-instruction
NOP (state) to run next. It can be thought in terms of a state
I2: Add R5, R4, R6 diagram.
The compiler can reorder the instructions to perform some
useful work during the NOP slots.
Structural Hazards:
This situation arises mainly when two instructions require a
given hardware resource at the same time and hence for one
1. Multiplicand is placed in BR and Multiplier in QR of the instructions the pipeline needs to be stalled. The most
2. Accumulator register AC, Qn+1 are initialized to 0 common case is when memory is accessed at the same time
3. Sequence counter SC is initialized to n by two instructions. One instruction may need to access the
4. Compare Qn and Qn+1 and perform the following memory as part of the Execute or Write back phase while The micro programmed control unit consists of following:
01 –> AC=AC+BR other instruction is being fetched.
10 –> AC=AC+BR’+1 Solution: Branch Prediction Control memory:
00 –> No arithmetic operation • Better performance can be achieved if we arrange for In micro programmed control, the micro programs for all
11-> No arithmetic operation some branch instructions to be predicted as taken and instructions are stored in the control memory (CM). The
5. ASHR- Arithmetic Shift right AC, QR others as not taken. control signals to be activated at any time are specified by a
6. Decrement SC by 1 • Use hardware to observe whether the target address is microinstruction, which is fetched from Control memory (CM).
The final product will be store in AC, QR lower or higher than that of the branch instruction.
• Let compiler include a branch prediction bit. Control address register
Features of Booth Algorithm: The control address register holds the address of the next
• So far the branch prediction decision is always the same
• Booth algorithm works equally well for both negative and microinstruction to be read. When address is available in
every time a given instruction is executed – static branch
positive multipliers. control address register, the sequencer issues READ command
prediction.
• Booth algorithm deals with signed multiplication of given to the control memory.
number. Control hazards:
• Speed up the multiplication process. The instruction fetch unit of the CPU is responsible for Microinstruction register
providing a stream of instructions to the execution unit. The After issue of READ command, the word from the addressed
instructions fetched by the fetch unit are in consecutive location is read into the microinstruction register. Now the
Array Multiplier content of the micro instruction register generates control
memory locations and they are executed.
Binary multiplication can be implemented in a combinational signals and next address information for the sequencer.
two-dimensional logic array called array multiplier. PIPELINING
Micro-program sequencer
• The main component in each in each cell is a full adder, FA. Pipelining is a technique of decomposing a sequential process A sequence of one or more micro operations designed to
• The AND gate in each cell determines whether a into sub operations, with each sub process being executed in control specific operation, such as addition, multiplication is
multiplicand bit mj, is added to the incoming partial product a special dedicated segment that operates concurrently with called a micro program. The sequencer loads a new address
bit based on the value of the multiplier bit, qi. all other segments. A pipeline can be visualized as a collection into the control address register based on the next address
• Each row i, where 0<= i <=3, adds the multiplicand of processing segments through which binary information information.
(appropriately shifted) to the incoming parcel product, PPi, to flows.
generate the outgoing partial product, PP(i+1), if qi.=1. Each segment performs partial processing dictated by the way
• If qi.=0, PPi is passed vertically downward unchanged. PP0 is the task is partitioned. The result obtained from the
all 0’s and PP4 is the desired product. The multiplication is computation in each segment is transferred to the next
shifted left one position per row by the diagonal signal path. segment in the pipeline. The final result is obtained after the
data have passed through all segments.
Two port memory organization Organization of a Processor unit is connected to the external bus. The control lines of the MULTIPLE BUS ORGANIZATION
memory bus are connected to the instruction decoder and
Some processor employ a 2 port memory in order to A bus organization for four processor registers where each control logic block.
overcome the delay caused when reading two source register is connected to two multiplexers (MUX) to form input Three registers Y, Z, and TEMP registers are used by the
registers. A 2-port has two separate address lines to select two buses A and B. The selection lines of each multiplexer select processor for temporary storage during execution of some
words of memory simultaneously. The organization of a one register for the particular bus. The A and B buses are instructions. The multiplexer MUX selects either the output of
processor unit with a 2-port scratchpad memory is shown applied to a common arithmetic logic unit. The function register Y or a constant value 4 to be provided as input A of
below: selected in the ALU determines the particular operation that the ALU. The constant 4 is used to increment the contents of
is to be performed. the program counter.
The shift micro-operations are implemented in the shifter. The With few exceptions, an instruction can be executed by
result of the micro-operation goes through the output bus S performing one or more of the following operations in some
into the inputs of all registers. The destination register that specified sequence:
receives the information from the output bus is selected by a • Transfer a word of data from one processor register to
decoder. another or to the ALU
• Perform an arithmetic or a logic operation and store the
When enabled, this decoder activates one of the register load result in a processor register
inputs to provide a transfer path between the data on the S • Fetch the contents of a given memory location and load
bus and the inputs of the selected destination register. The them into a processor register
output bus S provides the terminals for transferring data to an • Store a word of data from a processor register into a given
external destination. One input of multiplexer A or B can memory location
receive data from the outside the control unit that supervises
the processor bus system directs the information flow through Control sequence for Add[R3],R1
the ALU by selecting the various components in the unit. 1. PC out, MAR in, Read, Select4, Add, Z in
2. Z out, PC in, Y in, WMF C
3. MDR out, IR in
Status Registers 4. R3 out, MAR in, Read
The relative magnitude of two numbers may be determined 5. R1 out, Y in, WMF C
by subtracting one number from the other and then checking 6. MDR out, SelectY, Add, Z in
certain bit conditions in the resultant difference. This status 7. Z out, R1 in, End
bit conditions (often called condition-code bits or flag bits) are
stored in a status register. Status register is a 4 bit register. Big Endian / Little Endian
The four bits are C (carry), Z (zero), S (sign) and V (overflow).
These bits are set or cleared as a result of an operation Big-endian and little-endian are terms that describe the order
performed in the ALU. in which a sequence of bytes are stored in computer memory.
• Bit C is set if the output carry of an ALU is 1. Big-endian is an order in which the "big end" (most significant
• Bit S is set to 1 if the highest order bit of the result in the value in the sequence) is stored first (at the lowest storage
output of the ALU is 1. address). i.e., in big endian, you store the most significant byte
• Bit Z is set to 1 if the output of the ALU contains all O's. in the smallest address.
• Bit V is set if the exclusive —OR of carries C8 and C9 is 1,
Address 1000 1001 1002 1003
and cleared otherwise.
Value 90 AB 12 CD
This is the condition for overflow when the numbers are in
signed 2's complement representation. For an 8 bit ALU, V is
Little-endian is an order in which the "little end" (least
set if the result is greater than 127 or less than -128. After an
significant value in the sequence) is stored first. i.e., in little
ALU operation, status bits can be checked to determine the
endian, you store the least significant byte in the smallest Consider the three-operand instruction: 𝐴𝑑𝑑 𝑅4, 𝑅5, 𝑅6
relationship that exist between the values of A and B.
address. The control sequence for executing this instruction is:
Address 1000 1001 1002 1003 Step 1: the contents of the PC are passed through the ALU,
Value CD 12 AB 90 using the R=B control signal, and loaded into the MAR to start
a memory read operation. At the same time the PC is
For example, to perform the micro operation: 𝑅1 ← 𝑅2 + 𝑅3 incremented by 4. Note that the value loaded into MAR is the
The control must provide binary selection variables to the original contents of the PC. The incremented value is loaded
following selector inputs: into the PC at the end of the clock cycle and will not affect the
 MUX A selector: to place the contents of R2 onto bus A. contents of MAR.
 MUX B selector: to place the contents of R3 onto bus B. Step 2: Processor waits for MFC and loads the data into MDR.
 ALU function selector: to provide operation A + B. Step 3: Transfers the data received in MDR to IR.
 Shift selector: for direct transfer from the output of the Step 4: The execution phase of the instruction requires only
ALU onto output bus S (no shift). one control step to complete.
 Decoder destination selector: to transfer the contents of By providing more paths for data transfer a significant
bus S into R 1. reduction in the number of clock cycles needed to execute an
instruction is achieved.

Horizontal Micro-Instructions A pipeline processor may process each instruction in 4 steps: Processor Pipelining
F Fetch: Read the instruction from the memory Pipeline processing of the same data stream by a cascade of
The scheme of micro-instruction by assigning one bit position D Decode: Decode the instruction and fetch source operands processors, each of which processes a specific task. The data
to each control signal is called horizontal micro-instructions. E Execute: Perform the operation specified by the instruction stream passes the first processor with the results stored in
Example: 011101001101001110 W Write: Store the result in the destination location. memory block which is also accessible by the second
In a horizontal microinstruction every bit in the control field
processor. The second processor then passes the refined
attaches to a controller. Horizontal microinstructions
results to the third and so on.
represent several micro-operations that are executed at the
same time. However, in extreme cases, each horizontal
microinstruction controls all the hardware resources of the
system.
Vertical Micro-Instructions
We can reduce the length of the horizontal micro-instruction
so easily by implementing another method known as vertical
micro-instructions. In this case, most signals are not needed PIPELINE CONFLICTS
simultaneously and many others are mutually exclusive
In a vertical microinstruction, a code is used for each action to CLASSIFICATION OF PIPELINE PROCESSORS RESOURCE CONFLICTS: They are caused by access to memory
be performed and the decoder translates this code into by two segments at the same time. Most of these conflicts can
individual control signals. The vertical microinstruction Arithmetic Pipelining be resolved by using separate instruction and data memories.
resembles the conventional machine language format The arithmetic logic units of a computer can be segmented for
pipeline operations in various data formats. An arithmetic DATA DEPENDENCY: these conflicts arise when an instruction
comprising one operation and a few operands. As opposed to depends on the result of a previous instruction, but this result
horizontal microinstructions, the vertical microinstruction pipeline divides an arithmetic operation into sub operations
for execution in the pipeline segments. Pipeline arithmetic is not yet available.
represents single micro-operations. 3. BRANCH DIFFERENCE: they arise from branch and other
units are usually found in very high speed computers. They are
Horizontal vs Vertical micro instructions used to implement floating point operations, multiplication of instructions that change the value of PC.

Horizontal Vertical fixed point numbers, and similar computations encountered

Long formats. Short formats in scientific problems.
Ability to express a high Limited ability to express
degree of parallelism. parallel micro operations.
Little encoding of the Considerable encoding of the
control information. control information
Higher operating speeds. Slower operating speeds.
Instruction Pipelining
PLA control The execution of stream of instructions can be pipelined by
overlapping the execution of current instruction with the
The external sequence register establishes the present state fetch, decode and execution of subsequent instructions. This
of the control circuit. The PLA outputs determine which micro- technique is known as instruction look ahead.
operations should be initiated depending on the external An instruction pipeline operates on a stream of instructions by
input conditions and the present state of the sequence overlapping the fetch, decode, and execute phases of
register. At the same time other PLA outputs determine the instruction cycle. An instruction pipeline reads consecutive
next state of the sequence register. instructions from memory while previous instructions are
being executed in other segments. This causes the instruction
fetch and executes phases to overlap and perform
simultaneous operations.
 Polling Scheme
Module 5 If two devices have activated the interrupt request line, the
ISR for the selected device (first device) will be completed &
Cache Mapping Functions / Techniques
then the second request can be serviced.
At any given time, only some blocks in the main memory are
held in the cache, which blocks in the main memory in the Vectored Interrupt
cache is determined by a “mapping function”. The mapping • Here the device requesting an interrupt may identify itself
functions are used to map a particular block of main memory to the processor by sending a special code over the bus & then
to a particular block of cache. This mapping function is used to the processor start executing the ISR.
transfer the block from main memory to cache memory. • The code supplied by the processor indicates the starting
Mapping functions determine how memory blocks are placed address of the ISR for the device.
in the cache. Three mapping functions: • The code length ranges from 4 to 8 bits.
• Direct mapping. • The location pointed to by the interrupting device is used to
• Associative mapping. store the staring address to ISR.
• Set-associative mapping. • The processor reads this address, called the interrupt vector
& loads into PC.
Direct Mapping
• The interrupt vector also includes a new value for the
A particular block of main memory can be brought to a
Processor Status Register.
particular block of cache memory. So, it is not flexible. The
• When the processor is ready to receive the interrupt vector
simplest way of associating main memory blocks with cache
code, it activate the interrupt acknowledge (INTA) line.
block is the direct mapping technique. In this technique, block
k of main memory maps into block k modulo m of the cache DIRECT MEMORY ACCESS (DMA)
(𝑘 % 𝑚), where m is the total number of blocks in cache.
• It is a technique used for high speed I/O device.
Associative mapping • Here, the device interface transfer data directly to or from
In the associative mapping technique, a main memory block the memory without continuous involvement by processor.
can potentially reside in any cache block position. In this case, • A special control unit may be provided to allow the transfer
the main memory address is divided into two groups, a low- of large block of data at high speed directly between the
order bit identifies the location of a word within a block and a external device and main memory, without continuous
high-order bit identifies the block. In the associative mapping, intervention by the processor. This approach is called DMA.
any block of main memory can go to any block of cache, so it • DMA transfers are performed by a control circuit called the
has got the complete flexibility and we have to use proper DMA Controller.
replacement policy to replace a block from cache if the
To initiate the transfer of a block of words, the processor
currently accessed block of main memory is not in the cache.
sends: Starting address, No of words in the block, Direction of
Set-Associative mapping transfer.
This mapping technique is intermediate to the previous two When a block of data is transferred , the DMA controller
techniques. Blocks of the cache are grouped into sets, and the increment the memory address for successive words and keep
mapping allows a block of main memory to reside in any block track of number of words and it also informs the processor by
of a specific set. Therefore, the flexibility of associative raising an interrupt signal.
mapping is reduced from full freedom to a set of specific While DMA control is taking place, the program requested the
blocks. This also reduces the searching overhead, because the transfer cannot continue and the processor can be used to
search is restricted to number of sets, instead of number of execute another program.
blocks. Also the contention problem of the direct mapping is After DMA transfer is completed, the processor returns to the
eased by having a few choices for block replacement. program that requested the transfer.

INTERRUPTS
When a program enters a wait loop, it will repeatedly check
the device status. During this period, the processor will not
perform any function. There are many situations where other
tasks can be performed while waiting for an I/O device to
become ready. To allow this to happen, we can arrange for the
I/O device to alert the processor when it becomes ready. It can
do so by sending a hardware signal called an interrupt to the
processor. At least one of the bus control lines called an
interrupt request line is usually dedicated for this purpose.
Cycle Stealing Centralized Arbitration
• Requests by DMA devices for using the bus are having higher • Here the processor is the bus master and it may grants bus
priority than processor requests. mastership to one of its DMA controller.
• Top priority is given to high speed peripherals such as: Disk, • A DMA controller indicates that it needs to become the bus
High speed Network Interface and Graphics display device. master by activating the Bus Request line (BR) which is an
• Since the processor originates most memory access cycles, open drain line.
the DMA controller can be said to steal the memory cycles • The signal on BR is the logical OR of the bus request from all
from the processor. devices connected to it.
• This interviewing technique is called Cycle stealing. • When BR is activated the processor activates the Bus Grant
Signal (BGI) and indicated the DMA controller that they may
Burst Mode: The DMA controller may be given exclusive use the bus when it becomes free.
access to the main memory to transfer a block of data without • This signal is connected to all devices using a daisy chain
interruption. This is known as Burst/Block Mode arrangement.
Bus Master: The device that is allowed to initiate data • If DMA requests the bus, it blocks the propagation of Grant
transfers on the bus at any given time is called the bus master. Signal to other devices and it indicates to all devices that it is
using the bus by activating open collector line, Bus Busy
Bus Arbitration: It is the process by which the next device to (BBSY).
become the bus master is selected and the bus mastership is
transferred to it. There are 2 approaches to bus arbitration.
They are: • Centralized arbitration • Distributed arbitration.

Static Memories (SRAM)

Static memories are the memories that consist of circuits
capable of retaining their state as long as power is applied.
Two transistor inverters are cross connected to implement a
basic flip-flop. The cell is connected to one word line and two
bits lines by transistors T1 and T2. When word line is at ground
level, transistors are turned off and the latch retains its state.
Distributed Arbitration
Dynamic Memories (DRAM)
• It means that all devices waiting to use the bus have equal
Dynamic random access memory stores each bit of data in a responsibility in carrying out the arbitration process without
separate capacitor within an integrated circuit. The charging using a central arbiter.
and discharging of the capacitor represent 0 and 1, i.e., the • Each device on the bus is assigned a 4 bit id.
two possible values that can be stored in a bit. • When one or more devices request the bus, they assert the
DRAM is widely used in digital electronics where low-cost and Start-Arbitration signal & place their 4 bit ID number on four
high-capacity memory is required. open collector lines, ARB0 to ARB3.
Dynamic RAMs (DRAMs) are cheap and area efficient, but they • A winner is selected as a result of the interaction among the
cannot retain their state indefinitely – need to be periodically signals transmitted over these lines.
refreshed. Dynamic memory cell consists of a capacitor C, and • The net outcome is that the code on the four lines
a transistor T. represents the request that has the highest ID number.
Synchronous vs Asynchronous DRAM • The drivers are of open collector type. Hence, if the input to
one driver is equal to 1, the input to another driver connected
Synchronous DRAM Asynchronous DRAM to the same bus line is equal to 0, then bus will be in low-
A DRAM type that uses an An older type of DRAM used voltage state.
externally supplied clock in earlier personal
signal to coordinate the computers.
operations.
The system clockDoes not use a system clock
coordinates the memory to coordinate the memory
access. access.
Provides high performance. Provides low performance.
Manufacture ofManufacture of
synchronous DRAM is high. asynchronous DRAM is
relatively rare.
Modern PCs with high speed Traditional PCs with low
memory use SDRAM. speed memory use ADRAM.