Digital Circuits and Systems Lab

Laboratory report submitted for the partial fulfillment

of the requirements for the degree of

Bachelor of Technology
in
Electronics and Communication Engineering

by

Sankalp Jain - 18UEC173

Course Coordinator
Dr. Kusum Lata

Department of Electronics and Communication Engineering

The LNM Institute of Information Technology, Jaipur

August 2018
Copyright c The LNMIIT 2018
All Rights Reserved
 Contents

Chapter Page

1 Experiment - 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Name of the Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.1 Half Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.2 Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Coding Techniques used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3.1 Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3.2 Behavioural . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3.3 Structural . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4.1 Half Adder using Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4.2 Half Adder using Behavioural . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.3 Full Adder using Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.4 Full Adder using Behavioural . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.5 Full Adder using Structural . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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 Chapter 1

Experiment - 1

1.1 Name of the Experiment

To study various types of adders design using VHDL

1.2 Theory

1.2.1 Half Adder

Half adder is a combinational circuit which adds two numbers and produce a sum (s) and a carry (c).
It takes two input i.e a and b and gives two output i.e s and c. The expression of sum and carry is given
by s = a xor b and c = a.b respectively. Hence we need a XOR gate and AND gate to implement a half
adder.

1.2.2 Full Adder

Full adder is a combinational circuit which adds three one bit numbers and produces sum (s) and
carry(carryout). Full adder takes three input i.e a,b and cin and gives two output i.e s and c. The
expression of sum and carry is given by s = a xor b xor cin and c = a.b or b.cin or a.cin respectively.
Hence we can implement full adder using two XOR, two AND and one OR gate as it can be implemented
using 2 half adders and one OR gate.

1.3 Coding Techniques used

There are three types of coding techniques used: Dataflow

Behavioural
Structural

1
1.3.1 Dataflow
Dataflow style describes a system in terms of how the data flows through the system.A dataflow
description directly implies a gate-level implementation.

1.3.2 Behavioural
A behavioural description describes a system’s behaviour or function in an algorithmic fashion. Be-
havioural style consists of one or more process statements. Each process statement is a single concurrent
statement that itself contains one or more sequential statements.

1.3.3 Structural
Structural style of modelling has an entity described as a set of interconnected components.Structural
style is most useful and efficient when a complex system is described as an interconnection of moder-
ately complex design entities.

2
1.4 Simulation and Results
1.4.1 Half Adder using Dataflow

Figure 1.1 Schematic of the Half added using Dataflow modeling

Figure 1.2 Project Summary of the Half added using Dataflow modeling

3
 Figure 1.3 Simulation of the Half added using Dataflow modeling

1.4.2 Half Adder using Behavioural

4
 Figure 1.4 Schematic of the Half added using Behavioural modeling

Figure 1.5 Project Summary of the Half added using Behavioural modeling

5
 Figure 1.6 Simulation of the Half added using Behavioural modeling

1.4.3 Full Adder using Dataflow

6
 Figure 1.7 Schematic of the Full adder using Dataflow modeling

Figure 1.8 Project Summary of the Full adder using Dataflow modeling

7
 Figure 1.9 Simulation of the Full adder using Dataflow modeling

1.4.4 Full Adder using Behavioural

Figure 1.10 Schematic of the Full adder using Behavioural modeling

8
Figure 1.11 Project Summary of the Full adder using Behavioural modeling

Figure 1.12 Simulation of the Full adder using Behavioural modeling

9
1.4.5 Full Adder using Structural

Figure 1.13 Schematic of the Full adder using Structural modeling

Figure 1.14 Project Summary of the Full adder using Structural modeling

10
 Figure 1.15 Simulation of the Full adder using Structural modeling

1.5 Summary
Tabular comparison of all the codes in terms of area and power usage.

Name of the Entity No. of LUT used Total On chip Power

Half Adder using Dataflow 1 0.771W
Half Adder using Behavioural 1 0.771W
Full Adder using Dataflow 1 0.973W
Full Adder using Behavioural 1 1.013W
Full Adder using Structural 1 0.681W

Table 1.1 comparision of Area and power requirements for different kinds of adders.

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