FUJITSU SEMICONDUCTOR

DATA SHEET DS705-00010-2v0-E

32-bit Microcontroller
FR Family FR81S

MB91590 Series
MB91F591B/F591BS/F591BH/F591BHS/F592B/F592BS/F592BH/F592BHS
MB91F594B/F594BS/F594BH/F594BHS/F596B*/F596BS*/F596BH*/F596BHS*
MB91F597B*/F597BS*/F597BH*/F597BHS*/F599B*/F599BS*/F599BH*/F599BHS*
*:Under consideration

 OVERVIEW
This series is Fujitsu 32-bit microcontroller designed for automotive and industrial control applications. It
contains the FR81S CPU that is compatible with the FR family. The FR81S has a high level performance
among the Fujitsu FR family by enhancing CPU instruction pipeline and load store processing, and
improving internal bus transfer.
It is best suited for application control for automotive.

Note: FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Semiconductor
Limited.

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved

2012.1

FUJITSU SEMICONDUCTOR CONFIDENTIAL r2.0

MB91590 Series

 FEATURES
 FR81S CPU Core
· 32-bit RISC, load/store architecture, pipeline 5-stage structure
· Maximum operating frequency: 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied (PLL clock
multiplication system))
· General-purpose register : 32 bits ×16 sets
· 16-bit fixed length instructions (basic instruction), 1 instruction per cycle
· Instructions appropriate to embedded applications
· Memory-to-memory transfer instruction
· Bit processing instruction
· Barrel shift instruction etc.
· High-level language support instructions
· Function entry/exit instructions
· Register content multi-load and store instructions
· Bit search instructions
· Logical 1 detection, 0 detection, and change-point detection
· Branch instructions with delay slot
· Reduced overhead during branch process
· Register interlock function
· Easy assembler writing
· The support at the built-in / instruction level of the multiplier
· Signed 32-bit multiplication : 5 cycles
· Signed 16-bit multiplication : 3 cycles
· Interrupt (PC/PS saving)
· 6 cycles (16 priority levels)
· The Harvard architecture allows simultaneous execution of program and data access.
· Instruction compatibility with the FR Family
· Built-in memory protection function (MPU)
· Eight protection areas can be specified commonly for instructions and the data.
· Control access privilege in both privilege mode and user mode.
· Built-in FPU (floating point arithmetic)
· IEEE754 compliant
· Floating-point register 32-bit × 16 sets

 Peripheral functions
· Clock generation (equipped with SSCG function)
· Main oscillation (4MHz)
· Sub oscillation (32KHz) or none sub oscillation
· PLL multiplication rate : 1 to 32 times
· Built-in Program flash memory capacity 1024 + 64KB
· Built-in Data flash memory capacity(WorkFlash) 64KB
· Built-in RAM capacity
· Main RAM 64KB
· Backup RAM 8KB
· General-purpose ports (5V Pin) : 63 (dual clock products : 61)
· Included I2C pseudo open drain support ports : 4
· General-purpose ports (3V Pin) : 93
· Included 48 combined external bus interface (For GDC external memory I/F)
· External bus interface
· GDC external memory for I/F use
· 25-bit address, 16-bit data
· Power supply voltage fixed to 3.3V
· DMA Controller
· Up to 16 channels can be started simultaneously.
· 2 transfer factors (Internal peripheral request and software)

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· A/D converter (successive approximation type)

· 8/10-bit resolution : 32 channels
· Conversion time : 3μs
· External interrupt input: 16 channels
· Level ("H" / "L"), or edge detection (rising or falling) enabled
· LIN-UART
· 6 channels, ch.2 to ch.7
· UART, synchronous mode, LIN-UART mode is selectable.
· LIN protocol Revision 2.1 is supported
· SPI (Serial Peripheral Interface) supported (synchronous mode)
· Full-duplex double buffering system
· LIN synch break detection (linked to the input capture)
· Built-in dedicated baud rate generator
· DMA transfer support
· Multi-function serial communication (built-in transmission/reception FIFO memory) : 2 channels
< UART (Asynchronous serial interface) >
· Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO
memory
· Parity or no parity is selectable.
· Built-in dedicated baud rate generator
· An external clock can be used as the transfer clock
· Parity, frame, and overrun error detect functions provided
· DMA transfer support
<CSIO (Synchronous serial interface) >
· Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO
memory
· SPI supported; master and slave systems supported; 5 to 9-bit data length can be set.
· Built-in dedicated baud rate generator (Master operation)
· An external clock can be entered. (Slave operation)
· Overrun error detect function is provided
· DMA transfer support
<LIN-UART (Asynchronous Serial Interface for LIN) >
· Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO
memory
· LIN protocol Revision 2.1 supported
· Master and slave systems supported
· Framing error and overrun error detection
· LIN synch break generation and detection; LIN synch delimiter generation
· Built-in dedicated baud rate generator
· An external clock can be adjusted by the reload counter
· DMA transfer support
< I2C >
· Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO
memory
· Standard mode (Max. 100kbps) / high-speed mode (Max. 400kbps) supported
· DMA transfer supported (for transmission only)
· CAN Controller (C-CAN) : 3 channels
· Transfer speed : Up to 1Mbps
· 64-transmission/reception message buffering : 1 channel,
32-transmission/reception message buffering : 2 channels
· PPG : 16-bit × 24 channels
· Reload timer : 16-bit × 4 channels
· Free-run timer : 32-bit × 2 channels (Can select each channel for input capture, output compare)
32-bit × 2 channels (LSYN (LIN synch field detection) for exclusive input capture)
· Input capture : 32-bit × 6 channels (linked to the free-run timer) LSYN (LIN synch field detected)
Exclusive 32-bit × 2 channels (linked to the free-run timer)
· Output compare : 32-bit × 4 channels (linked to the free-run timer)
· Sound generator : 5 channels
· Frequency and amplitude sequencers provided

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MB91590 Series

· Stepping motor controller : 6 channels

· 8/10-bit PWM
· High current output supported (4 lines × 6 channels)
· Can refer back electromotive force using pin-shared A/D converter
· Real-time clock (RTC) (for day, hours, minutes, seconds)
· Main/sub oscillation frequency can be selected for the operation clock (dual product only)
· Calibration: The hardware watchdog for CR oscillation drive and real-time clock (RTC) for sub clock
drive (dual product only)
· The CR oscillation frequency can be trimmed
· The main clock to sub clock (dual product only) ratio can be corrected by setting the real-time clock
prescaler
· Clock Supervisor
· Monitoring abnormality (damage of crystal etc.) of sub oscillation (32KHz) (two system clock kinds)
of the outside and main oscillation (4 MHz)
· When abnormality is detected, it switches to the CR clock.
· Base timer : 2 channels
· 16-bit timer
· Any of four PWM/PPG/PWC/reload timer functions can be selected and used
· A 32-bit timer can be used in 2 channels of cascade mode
· CRC generation
· Watchdog timer
· Hardware watchdog
· Software watchdog
· NMI
· Interrupt controller
· Interrupt request batch read
· Multiple interrupts from peripherals can be read by a series of registers.
· I/O relocation
· Peripheral function pins can be reassigned.
· Low-power consumption mode
· Sleep / Stop / Watch / Sub RUN mode
· Stop (power shutdown) / Watch (power shutdown) mode
· GDC part self-support power supply
· Power on reset
· Low-voltage detection reset(external low-voltage detection)
· Low-voltage detection reset(internal low-voltage detection)
· GDC
· Internal/memory frequency : 81MHz
· The resolution of the display which can support : 800 × 480 at the maximum
Screen overlay of five simultaneous layers at the maximum (window)
Size of the resolution which can be supported varies depending on color format.
· Analog video input (NTSC)
· Digital video input (RGB666/555)
· YUV input (BT.656)
· Video image expansion/reduction /invert function is supported
· RGB Digital output (6-bit × 3)
· Built-in 2D rendering engine
The line drawing is supported.
The Bitblt function is supported.
Display list operation is supported
8bpp indirect color
ARGB-1555 direct color
Alpha blending, anti-aliasing

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 MB91590 Series

· Built-in Sprite engine

Equipped with automatic display function when booted
Maximum of 512 sprites are supported
32 special sprites capable of automatic animation are supported.
The command list execution is supported.
1bpp, 2bpp, 4bpp, 8bpp indirect color
ARGB-1555, RGB-565, ARGB-8888 direct color
The color format for each sprite can be set.
Horizontal invert, Vertical invert
Alpha blending

· Built-in memory (800KB)

· Device Package : LQFP-208, HQFP-208*
· CMOS 90nm Technology
· Power supplies
· 5V/3.3V Power supply
· The internal 1.2V is generated from 5V/3.3V with the depression circuit.
· I/O of an external bus and GDC, 3.3V power supply used.
· For other I/O, 5V power supply used.
· If 2 power supplies are used, they must turn on in the specified sequence (5V →3.3V) .
*: Under consideration. For detailed information about mount conditions, contact your sales
representative.

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MB91590 Series

 PRODUCT LINEUP
Product
Item MB91F591B/S MB91F591BH/S

CPU core FR81S

Technology 90nm
Package LQFP208
Yes (Non-S series)
Sub clock
No (S series)
Maximum CPU operating frequency 80MHz
Maximum GDC operating frequency 81MHz
Built-in CR oscillator 100kHz
System clock On chip PLL
Main 576KB
Flash
Sub 64KB
Main 40KB
RAM
Backup 8KB
VRAM 260KB
1ch Hardware
Watchdog timer
1ch Software
Clock supervisor Initial value "ON" Initial value "OFF"
Low-voltage detection reset
Yes
(External low-voltage detection)
Low-voltage detection reset
Yes
(Internal low-voltage detection)
NMI function Yes
DMA Controller 16ch
1ch (64msg)
CAN
2ch (32msg)
LINx6
USART
MFSx2
A/D converter (8bit/10bit) 1unit/32ch
Reload timer(16bit) 4ch
Base timer(16bit) 2ch
Free-run timer(32bit) 2ch
Input capture(32bit) 6ch
Output compare(32bit) 4ch
PPG timer(16bit) 24ch
Sound generator 5ch
Real-time clock Yes
External interrupt 16ch
CR/SUB compensation function Yes
CRC generation Yes
Stepping motor control 6ch

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 MB91590 Series

Product
Item MB91F591B/S MB91F591BH/S

Stop mode (including power shut-off) Supported

MICOM : 4.5V to 5.5V
Power supply voltage
GDC : 3.0V to 3.6V
Operating temperature -40°C to +105°C
Allowable power [mW] 1250
Others Flash product
On chip debugger Yes

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MB91590 Series

Product
Item MB91F592B/S MB91F592BH/S MB91F594B/S MB91F594BH/S

CPU core FR81S

Technology 90nm
Package LQFP208
Yes (Non-S series)
Sub clock
No (S series)
Maximum CPU operating
80MHz
frequency
Maximum GDC operating
81MHz
frequency
Built-in CR oscillator 100kHz
System clock On chip PLL
Main 576KB 1088KB
Flash
Sub 64KB
Main 40KB 64KB
RAM
Backup 8KB
VRAM 800KB
1ch Hardware
Watchdog timer
1ch Software
Initial value Initial value Initial value Initial value
Clock supervisor
"ON" "OFF" "ON" "OFF"
Low-voltage detection reset
Yes
(External low-voltage detection)
Low-voltage detection reset
Yes
(Internal low-voltage detection)
NMI function Yes
DMA Controller 16ch
1ch (64msg)
CAN
2ch (32msg)
LINx6
USART
MFSx2
A/D converter (8bit/10bit) 1unit/32ch
Reload timer(16bit) 4ch
Base timer(16bit) 2ch
Free-run timer(32bit) 2ch
Input capture(32bit) 6ch
Output compare(32bit) 4ch
PPG timer(16bit) 24ch
Sound generator 5ch
Real-time clock Yes
External interrupt 16ch
CR/SUB compensation function Yes
CRC generation Yes
Stepping motor control 6ch

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 MB91590 Series

Product
Item MB91F592B/S MB91F592BH/S MB91F594B/S MB91F594BH/S

Stop mode (including power

Supported
shut-off)
MICOM:4.5V to 5.5V
Power supply voltage
GDC:3.0V to 3.6V

Operating temperature -40°C to +105°C

Allowable power [mW] 1250

Others Flash product
On chip debugger Yes

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MB91590 Series

Product
Item MB91F596B/S* MB91F596BH/S* MB91F597B/S* MB91F597BH/S*

CPU core FR81S

Technology 90nm
Package HQFP208
Yes (Non-S series)
Sub clock
No (S series)
Maximum CPU operating
128MHz
frequency
Maximum GDC operating
81MHz
frequency
Built-in CR oscillator 100kHz
System clock On chip PLL
Main 576KB
Flash
Sub 64KB
Main 40KB
RAM
Backup 8KB
VRAM 260KB 800KB
1ch Hardware
Watchdog timer
1ch Software
Initial value Initial value Initial value
Clock supervisor Initial value "OFF"
"ON" "ON" "OFF"
Low-voltage detection reset
Yes
(External low-voltage detection)
Low-voltage detection reset
Yes
(Internal low-voltage detection)
NMI function Yes
DMA Controller 16ch
1ch (64msg)
CAN
2ch (32msg)
LINx6
USART
MFSx2
A/D converter (8bit/10bit) 1unit/32ch
Reload timer(16bit) 4ch
Base timer(16bit) 2ch
Free-run timer(32bit) 2ch
Input capture(32bit) 6ch
Output compare(32bit) 4ch
PPG timer(16bit) 24ch
Sound generator 5ch
Real-time clock Yes
External interrupt 16ch
CR/SUB compensation
Yes
function
CRC generation Yes
Stepping motor control 6ch

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 MB91590 Series

Product
Item MB91F596B/S* MB91F596BH/S* MB91F597B/S* MB91F597BH/S*

Stop mode (including power

Supported
shut-off)
MICOM:4.5V to 5.5V
Power supply voltage
GDC:3.0V to 3.6V
Operating temperature -40°C to +105°C
Allowable power [mW] 2500
Others Flash product
On chip debugger Yes
*: Under consideration. For detailed information about mount conditions, contact your sales representative.

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MB91590 Series

Product
Item MB91F599B/S* MB91F599BH/S*

CPU core FR81S

Technology 90nm
Package HQFP208
Yes (Non-S series)
Sub clock
No (S series)
Maximum CPU operating
128MHz
frequency
Maximum GDC operating
81MHz
frequency
Built-in CR oscillator 100kHz
System clock On chip PLL
Main 1088KB
Flash
Sub 64KB
Main 64KB
RAM
Sub 8KB
VRAM 800KB
1ch Hardware
Watchdog timer
1ch Software
Clock supervisor Initial value "ON" Initial value "OFF"
Low-voltage detection reset
(External low-voltage Yes
detection)
Low-voltage detection reset
(Internal low-voltage Yes
detection)
NMI function Yes
DMA Controller 16ch
1ch (64msg)
CAN
2ch (32msg)
LINx6
USART
MFSx2
A/D Converter (8bit/10bit) 1unit/32ch
Reload timer(16bit) 4ch
Base timer(16bit) 2ch
Free-run timer(32bit) 2ch
Input capture(32bit) 6ch
Output compare(32bit) 4ch
PPG timer(16bit) 24ch
Sound generator 5ch
Real-time clock Yes
External interrupt 16ch
CR/SUB compensation
Yes
function
CRC generation Yes
Stepping motor control 6ch

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 MB91590 Series

Product
Item MB91F599B/S* MB91F599BH/S*

Stop mode (including power

Supported
shut-off)
MICOM:4.5V to 5.5V
Power supply voltage
GDC:3.0V to 3.6V
Operating temperature -40°C to +105°C
Allowable power [mW] 2500
Others Flash product
On chip debugger Yes
*: Under consideration. For detailed information about mount conditions, contact your sales representative.

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MB91590 Series

 PIN ASSIGNMENT
 Pin Assignment (single clock product)

(TOP VIEW)

PPG6_2
PPG5_2

PPG0_1
PPG9_1
PPG4_2
PPG3_2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-
-
PPG7_2

ICU5_1
ICU4_1
ICU1_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-

-
-
-
-
-

-
-
-
TOT2
TOT1
TOT0
TIN3
TIN2
TIN1
TIN0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-
-

-
-
-
PPG0_2 -
INT15
INT11
clock product)
clock product)

TRG4

TRG3
TOT3
INT7
INT6

INT8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-

-
-

-
CMDTRG

VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0

SCK5
SOT5
SIN5
SCK4
SOT4
SIN4
SCK3
SOT3
SIN3

ADTG
-
-
-
-
-
-
-
-

-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-
-

-
-

-
-
(Single
(Single
DCKIN
CSOUT

FRCK0
FRCK1
HSIN
VSIN
CCLK
BIN7
BIN6
BIN5
BIN4
BIN3
BIN2

GIN7
GIN6
GIN5
GIN4
GIN3
GIN2
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2

OCU0

SGO3
SGA3
SGO2
SGA2

SGO1
WOT

RX2
TX2
-
-
-
-
-
-
-
-

-
-

-
-
-

-
-

-
REFOUT
AVCC3
AVSS3

AVSS3
AVCC3
AVR3

VCC3

VCC3

VCC5
P136
P137

P122
P121
P120
P117
P116
P115
P114
P097
P094
P113
P112
P090
VSS

VIN

PG0
PG3
PG2
PG1
PH3
PC7
PC6
PC5
PC4
PC3
PC2

VSS
PB7
PB6
PB5
PB4
PB3
PB2
PA7
PA6
PA5
PA4
PA3
PA2

VSS

VSS
MD2
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
●
- - - - - - VCC3 1 156 DVCC - - - - - -
- - - - - ROUT2 PD2 2 155 DVSS - - - - - -
- - - - - ROUT3 PD3 3 154 P087 PWM2M5 AN31 ICU4_2 PPG23 - -
- - - - - ROUT4 PD4 4 153 P086 PWM2P5 AN30 ICU3_2 PPG22 - -
- - - - - ROUT5 PD5 5 152 P085 PWM1M5 AN29 ICU2_2 PPG21 - -
- - - - - ROUT6 PD6 6 151 P084 PWM1P5 AN28 ICU1_2 PPG20 - -
- - - - - ROUT7 PD7 7 150 P083 PWM2M4 AN27 ICU0_2 PPG19 - -
- - - - - GOUT2 PE2 8 149 P082 PWM2P4 AN26 SCK6 PPG18 - -
- - - - - GOUT3 PE3 9 148 P081 PWM1M4 AN25 SOT6 PPG17 - -
- - - - - GOUT4 PE4 10 147 P080 PWM1P4 AN24 SIN6 PPG16 - -
- - - - - GOUT5 PE5 11 146 DVCC - - - - - -
- - - - - GOUT6 PE6 12 145 DVSS - - - - - -
- - - - - GOUT7 PE7 13 144 P077 PWM2M3 AN23 SCK7_1 PPG15_1 - -
- - - - - BOUT2 PF2 14 143 P076 PWM2P3 AN22 SOT7_1 PPG14_1 - -
- - - - - BOUT3 PF3 15 142 P075 PWM1M3 AN21 SIN7_1 PPG13_1 - -
- - - - - BOUT4 PF4 16 141 P074 PWM1P3 AN20 - PPG12_1 - -
- - - - - BOUT5 PF5 17 140 P073 PWM2M2 AN19 - - - -
- - - - - - VCC3 18 139 P072 PWM2P2 AN18 - - - -
- - - - - - VSS 19 138 P071 PWM1M2 AN17 - - - -
- - - - - - C_3 20 137 P070 PWM1P2 AN16 - - - -
- - - - - BOUT6 PF6 21 136 DVCC - - - - - -

FR+GDC
- - - - - BOUT7 PF7 22 135 DVSS - - - - - -
- - - - - DCKOUT PG4 23 134 P067 PWM2M1 AN15 - - - -
- - - - - VSYNC PG5 24 133 P066 PWM2P1 AN14 - - - -
- - - - - HSYNC PG6 25 132 P065 PWM1M1 AN13 - - - -
-
-
-
- -
PPG0
PPG1
-
TIN0_2
TIN1_2
-
SIN2_1
SOT2_1
DEOUT
D0
D1
PG7
P000
P001
26
27
28
TOP VIEW 131
130
129
P064
P063
P062
PWM1P1
PWM2M0
PWM2P0
AN12
AN11
AN10
-
-
-
-
-
-
-
-
-
-
-
-

LQFP-208 / HQFP-208
- PPG2 TIN2_2 SCK2_1 D2 P002 29 128 P061 PWM1M0 AN9 - - - -
- PPG3 TIN3_2 SIN3_1 D3 P003 30 127 P060 PWM1P0 AN8 - - - -
- PPG4 TOT0_2 SOT3_1 D4 P004 31 126 DVCC - - - - - -
- PPG5 TOT1_2 SCK3_1 D5 P005 32 125 DVSS - - - - - -
- PPG6 TOT2_2 - D6 P006 33 124 C_1 - - - - - -
- PPG7 TOT3_2 - D7 P007 34 123 VSS - - - - - -
- - - - D8 P010 35 122 VCC5 - - - - - -
- - - - - - VSS 36 121 P107 SGO4_1 AN7 - - - PPG5_1
- - - - - - VCC3 37 120 P106 SGA4_1 AN6 - - - PPG4_1
- - - ROUT0 D9 P011 38 119 P105 SCK5_1 AN5 TOT1_1 - - PPG3_1
- - - ROUT1 D10 P012 39 118 P104 SOT5_1 AN4 TOT0_1 - - PPG2_1
- - - GOUT0 D11 P013 40 117 P103 SIN5_1 AN3 TIN3_1 - - PPG1_1
- - - GOUT1 D12 P014 41 116 P102 SCK4_1 AN2 TIN2_1 - - PPG10
- - - BOUT0 D13 P015 42 115 P101 SOT4_1 AN1 TIN1_1 - - PPG9
- - - BOUT1 D14 P016 43 114 P100 SIN4_1 AN0 TIN0_1 - - PPG8
- - - - D15 P017 44 113 AVSS5/AVRL5 - - - - - -
- - - - WEX P020 45 112 AVRH5 - - - - - -
- - - - CS0X P021 46 111 AVCC5 - - - - - -
- - - - CS1X P022 47 110 P125 OCU3 - - ICU0 - PPG10_2
- - - - REX P023 48 109 P124 OCU2 - - ICU5_2 - PPG9_2
- - - - - P024 49 108 P123 OCU1 - - - - PPG8_2
- - - - - P025 50 107 P096 RX0 - INT9 - - -
- - - - A00 P026 51 106 P095 TX0 - - - - PPG10_1
- - - - - - VSS 52 105 VCC5 - - - - - -
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VCC3
P027
P030
P031
P032
P033
P034
P035
P036
P037
P040
P041
P042
P043
P044
P045
P046
P047
VCC3
VSS
C_2
P050
P051
P052
P053
P054
P055
P056
P057
VSS
X1
X0
MD1
MD0
RSTX
VSS
VCC5
P126
P127
P130
P131
P132
P133
P134
NMIX
P091
P092
P093
P110
P111
DEBUGIF
VSS
-
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
-
-
-
A18
A19
A20
A21
A22
A23
A24
RDY
-
-
-
-
-
-
-
-
TRG0
-
-
TRG1
-
TRG5
TRG2
-
SGA0
SGO0
SGA1
TX1
RX1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI_DO
SPI_DI
SPI_SCK
SPI_XCS
-
-
-
-
-
-
-
-
-
SIN0
SOT0
SCK0
-
-
PPG11_1
PPG1_3
-
SIN2
SCK2
SOT2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SIN1
SOT1
SCK1
-
-
INT12
INT13
INT14
-
INT10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INT1
-
INT0
INT4
INT2
INT3
INT5
-
TOT2_1
TOT3_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICU1
ICU2
ICU3
ICU4
ICU5
-
ICU2_1
ICU0_1
ICU3_1
-
-
-
-
-

-
-
-

-
-
-
-
-
-
-
-
-
-
TIOA0
TIOA1
TIOB0
TIOB1
-
-
PPG6_1
PPG7_1
PPG8_1
PPG1_2
PPG2_2
-
-

14 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

 Pin Assignment (dual clock product)

(TOP VIEW)

PPG6_2
PPG5_2

PPG0_1
PPG9_1
PPG4_2
PPG3_2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-
-
PPG7_2

ICU5_1
ICU4_1
ICU1_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-

-
-
-
-
-

-
-
-
TOT2
TOT1
TOT0
TIN3
TIN2
TIN1
TIN0
(Dual clock product)
(Dual clock product)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-
-

-
-
-
PPG0_2 -
INT15
INT11
TRG4

TRG3
TOT3
INT7
INT6

INT8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-

-
-

-
CMDTRG

VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0

SCK5
SOT5
SIN5
SCK4
SOT4
SIN4
SCK3
SOT3
SIN3

ADTG
-
-
-
-
-
-
-
-

-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

-
-
-

-
-

-
-
DCKIN
CSOUT

(X1A)
(X0A)

FRCK0
FRCK1
HSIN
VSIN
CCLK
BIN7
BIN6
BIN5
BIN4
BIN3
BIN2

GIN7
GIN6
GIN5
GIN4
GIN3
GIN2
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2

OCU0

SGO3
SGA3
SGO2
SGA2

SGO1
WOT

RX2
TX2
-
-
-
-
-
-
-
-

-
-

-
-
-

-
-

-
REFOUT
AVCC3
AVSS3

AVSS3
AVCC3
AVR3

VCC3

VCC3

VCC5

P122
P121
P120
P117
P116
P115
P114
P097
P094
P113
P112
P090
VSS

VIN

PG0
PG3
PG2
PG1
PH3
PC7
PC6
PC5
PC4
PC3
PC2

VSS
PB7
PB6
PB5
PB4
PB3
PB2
PA7
PA6
PA5
PA4
PA3
PA2

VSS

VSS
MD2
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
●
- - - - - - VCC3 1 156 DVCC - - - - - -
- - - - - ROUT2 PD2 2 155 DVSS - - - - - -
- - - - - ROUT3 PD3 3 154 P087 PWM2M5 AN31 ICU4_2 PPG23 - -
- - - - - ROUT4 PD4 4 153 P086 PWM2P5 AN30 ICU3_2 PPG22 - -
- - - - - ROUT5 PD5 5 152 P085 PWM1M5 AN29 ICU2_2 PPG21 - -
- - - - - ROUT6 PD6 6 151 P084 PWM1P5 AN28 ICU1_2 PPG20 - -
- - - - - ROUT7 PD7 7 150 P083 PWM2M4 AN27 ICU0_2 PPG19 - -
- - - - - GOUT2 PE2 8 149 P082 PWM2P4 AN26 SCK6 PPG18 - -
- - - - - GOUT3 PE3 9 148 P081 PWM1M4 AN25 SOT6 PPG17 - -
- - - - - GOUT4 PE4 10 147 P080 PWM1P4 AN24 SIN6 PPG16 - -
- - - - - GOUT5 PE5 11 146 DVCC - - - - - -
- - - - - GOUT6 PE6 12 145 DVSS - - - - - -
- - - - - GOUT7 PE7 13 144 P077 PWM2M3 AN23 SCK7_1 PPG15_1 - -
- - - - - BOUT2 PF2 14 143 P076 PWM2P3 AN22 SOT7_1 PPG14_1 - -
- - - - - BOUT3 PF3 15 142 P075 PWM1M3 AN21 SIN7_1 PPG13_1 - -
- - - - - BOUT4 PF4 16 141 P074 PWM1P3 AN20 - PPG12_1 - -
- - - - - BOUT5 PF5 17 140 P073 PWM2M2 AN19 - - - -
- - - - - - VCC3 18 139 P072 PWM2P2 AN18 - - - -
- - - - - - VSS 19 138 P071 PWM1M2 AN17 - - - -
- - - - - - C_3 20 137 P070 PWM1P2 AN16 - - - -
- - - - - BOUT6 PF6 21 136 DVCC - - - - - -

FR+GDC
- - - - - BOUT7 PF7 22 135 DVSS - - - - - -
- - - - - DCKOUT PG4 23 134 P067 PWM2M1 AN15 - - - -
- - - - - VSYNC PG5 24 133 P066 PWM2P1 AN14 - - - -
- - - - - HSYNC PG6 25 132 P065 PWM1M1 AN13 - - - -
-
-
-
- -
PPG0
PPG1
-
TIN0_2
TIN1_2
-
SIN2_1
SOT2_1
DEOUT
D0
D1
PG7
P000
P001
26
27
28
TOP VIEW 131
130
129
P064
P063
P062
PWM1P1
PWM2M0
PWM2P0
AN12
AN11
AN10
-
-
-
-
-
-
-
-
-
-
-
-

LQFP-208 / HQFP-208
- PPG2 TIN2_2 SCK2_1 D2 P002 29 128 P061 PWM1M0 AN9 - - - -
- PPG3 TIN3_2 SIN3_1 D3 P003 30 127 P060 PWM1P0 AN8 - - - -
- PPG4 TOT0_2 SOT3_1 D4 P004 31 126 DVCC - - - - - -
- PPG5 TOT1_2 SCK3_1 D5 P005 32 125 DVSS - - - - - -
- PPG6 TOT2_2 - D6 P006 33 124 C_1 - - - - - -
- PPG7 TOT3_2 - D7 P007 34 123 VSS - - - - - -
- - - - D8 P010 35 122 VCC5 - - - - - -
- - - - - - VSS 36 121 P107 SGO4_1 AN7 - - - PPG5_1
- - - - - - VCC3 37 120 P106 SGA4_1 AN6 - - - PPG4_1
- - - ROUT0 D9 P011 38 119 P105 SCK5_1 AN5 TOT1_1 - - PPG3_1
- - - ROUT1 D10 P012 39 118 P104 SOT5_1 AN4 TOT0_1 - - PPG2_1
- - - GOUT0 D11 P013 40 117 P103 SIN5_1 AN3 TIN3_1 - - PPG1_1
- - - GOUT1 D12 P014 41 116 P102 SCK4_1 AN2 TIN2_1 - - PPG10
- - - BOUT0 D13 P015 42 115 P101 SOT4_1 AN1 TIN1_1 - - PPG9
- - - BOUT1 D14 P016 43 114 P100 SIN4_1 AN0 TIN0_1 - - PPG8
- - - - D15 P017 44 113 AVSS5/AVRL5 - - - - - -
- - - - WEX P020 45 112 AVRH5 - - - - - -
- - - - CS0X P021 46 111 AVCC5 - - - - - -
- - - - CS1X P022 47 110 P125 OCU3 - - ICU0 - PPG10_2
- - - - REX P023 48 109 P124 OCU2 - - ICU5_2 - PPG9_2
- - - - - P024 49 108 P123 OCU1 - - - - PPG8_2
- - - - - P025 50 107 P096 RX0 - INT9 - - -
- - - - A00 P026 51 106 P095 TX0 - - - - PPG10_1
- - - - - - VSS 52 105 VCC5 - - - - - -
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VCC3
P027
P030
P031
P032
P033
P034
P035
P036
P037
P040
P041
P042
P043
P044
P045
P046
P047
VCC3
VSS
C_2
P050
P051
P052
P053
P054
P055
P056
P057
VSS
X1
X0
MD1
MD0
RSTX
VSS
VCC5
P126
P127
P130
P131
P132
P133
P134
NMIX
P091
P092
P093
P110
P111
DEBUGIF
VSS
-
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
-
-
-
A18
A19
A20
A21
A22
A23
A24
RDY
-
-
-
-
-
-
-
-
TRG0
-
-
TRG1
-
TRG5
TRG2
-
SGA0
SGO0
SGA1
TX1
RX1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI_DO
SPI_DI
SPI_SCK
SPI_XCS
-
-
-
-
-
-
-
-
-
SIN0
SOT0
SCK0
-
-
PPG11_1
PPG1_3
-
SIN2
SCK2
SOT2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SIN1
SOT1
SCK1
-
-
INT12
INT13
INT14
-
INT10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INT1
-
INT0
INT4
INT2
INT3
INT5
-
TOT2_1
TOT3_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICU1
ICU2
ICU3
ICU4
ICU5
-
ICU2_1
ICU0_1
ICU3_1
-
-
-
-
-

-
-
-

-
-
-
-
-
-
-
-
-
-
TIOA0
TIOA1
TIOB0
TIOB1
-
-
PPG6_1
PPG7_1
PPG8_1
PPG1_2
PPG2_2
-
-

DS705-00010-2v0-E 15

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

 PIN DESCRIPTION
I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
84 X0 – L Main clock oscillation input pin

83 X1 – L Main clock oscillation output pin

171
(dual
clock
X0A – N Sub clock oscillation input pin
product)

172
(dual
X1A – N Sub clock oscillation output pin
clock
product)
171
(single
P137 – A General-purpose I/O port
clock
product)

172
(single
P136 – A General-purpose I/O port
clock
product)

97 NMIX N F1 Non-masking interrupt input pin

170 VSS – – GND pin
87 RSTX N F1 External reset input pin
86 MD0 – P Mode pin 0
85 MD1 – P Mode pin 1
169 MD2 – F2 Mode pin 2
P000 – General-purpose I/O port (3V pin)
D0 – External bus · Data bit0 I/O pin
27 SIN2_1 – O LIN-UART ch.2 serial data input pin (1)
TIN0_2 – Reload timer ch.0 event input pin (2)
PPG0 – PPG ch.0 output pin
P001 – General-purpose I/O port (3V pin)
D1 – External bus · Data bit1 I/O pin
28 SOT2_1 – O LIN-UART ch.2 serial data output pin (1)

TIN1_2 – Reload timer ch.1 event input pin (2)

PPG1 – PPG ch.1 output pin

16 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P002 – General-purpose I/O port (3V pin)

D2 – External bus · Data bit2 I/O pin

29 SCK2_1 – O LIN-UART ch.2clock I/O pin (1)
TIN2_2 – Reload timer ch.2 event input pin (2)
PPG2 – PPG ch.2 output pin
P003 – General-purpose I/O port (3V pin)
D3 – External bus · Data bit3 I/O pin

30 SIN3_1 – O LIN-UART ch.3 serial data input pin (1)

TIN3_2 – Reload timer ch.3 event input pin (2)
PPG3 – PPG ch.3 output pin
P004 – General-purpose I/O port (3V pin)

D4 – External bus · Data bit4 I/O pin

31 SOT3_1 – O LIN-UART ch.3 serial data output pin (1)

TOT0_2 – Reload timer ch.0 output pin (2)

PPG4 – PPG ch.4 output pin
P005 – General-purpose I/O port (3V pin)
D5 – External bus · Data bit5 I/O pin
32 SCK3_1 – O LIN-UART ch.3 clock I/O pin (1)
TOT1_2 – Reload timer ch.1 output pin (2)
PPG5 – PPG ch.5 output pin
P006 – General-purpose I/O port (3V pin)
D6 – External bus · Data bit6 I/O pin
33 O
TOT2_2 – Reload timer ch.2 output pin (2)
PPG6 – PPG ch.6 output pin
P007 – General-purpose I/O port (3V pin)
D7 – External bus · Data bit7 I/O pin
34 O
TOT3_2 – Reload timer ch.3 output pin (2)
PPG7 – PPG ch.7 output pin
P010 – General-purpose I/O port (3V pin)
35 O
D8 – External bus · Data bit8 I/O pin
P011 – General-purpose I/O port (3V pin)
38 D9 – O External bus · Data bit9 I/O pin
ROUT0 – Display digital R0 output pin

DS705-00010-2v0-E 17

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P012 – General-purpose I/O port (3V pin)
39 D10 – O External bus · Data bit10 I/O pin
ROUT1 – Display digital R1 output pin
P013 – General-purpose I/O port (3V pin)
40 D11 – O External bus · Data bit11 I/O pin
GOUT0 – Display digital G0 output pin
P014 – General-purpose I/O port (3V pin)
41 D12 – O External bus · Data bit12 I/O pin
GOUT1 – Display digital G1 output pin
P015 – General-purpose I/O port (3V pin)
42 D13 – O External bus · Data bit13 I/O pin
BOUT0 – Display digital B0 output pin
P016 – General-purpose I/O port (3V pin)
43 D14 – O External bus · Data bit14 I/O pin
BOUT1 – Display digital B1 output pin
P017 – General-purpose I/O port (3V pin)
44 O
D15 – External bus · Data bit15 I/O pin
P020 – General-purpose I/O port (3V pin)
45 O
WEX – External bus · Write enable output pin
P021 – General-purpose I/O port (3V pin)
46 O
CS0X – External bus · Chip select 0 output pin
P022 – General-purpose I/O port (3V pin)
47 O
CS1X – External bus · Chip select 1 output pin
P023 – General-purpose I/O port (3V pin)
48 O
REX – External bus · Read enable output pin
49 P024 – O General-purpose I/O port (3V pin)
50 P025 – O General-purpose I/O port (3V pin)
P026 – General-purpose I/O port (3V pin)
51 O
A00 – External bus · Address bit0 output pin
P027 – General-purpose I/O port (3V pin)
54 O
A01 – External bus · Address bit1 output pin
P030 – General-purpose I/O port (3V pin)
55 O
A02 – External bus · Address bit2 output pin
P031 – General-purpose I/O port (3V pin)
56 O
A03 – External bus · Address bit3 output pin

18 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P032 – General-purpose I/O port (3V pin)
57 O
A04 – External bus · Address bit4 output pin
P033 – General-purpose I/O port (3V pin)
58 O
A05 – External bus · Address bit5 output pin
P034 – General-purpose I/O port (3V pin)
59 O
A06 – External bus · Address bit6 output pin
P035 – General-purpose I/O port (3V pin)
60 O
A07 – External bus · Address bit7 output pin
P036 – General-purpose I/O port (3V pin)
61 O
A08 – External bus · Address bit8 output pin
P037 – General-purpose I/O port (3V pin)
62 O
A09 – External bus · Address bit9 output pin
P040 – General-purpose I/O port (3V pin)
63 O
A10 – External bus · Address bit10 output pin
P041 – General-purpose I/O port (3V pin)
64 O
A11 – External bus · Address bit11 output pin

P042 – General-purpose I/O port (3V pin)

65 O
A12 – External bus · Address bit12 output pin
P043 – General-purpose I/O port (3V pin)
66 O
A13 – External bus · Address bit13 output pin
P044 – General-purpose I/O port (3V pin)
67 O
A14 – External bus · Address bit14 output pin
P045 – General-purpose I/O port (3V pin)
68 O
A15 – External bus · Address bit15 output pin
P046 – General-purpose I/O port (3V pin)
69 O
A16 – External bus · Address bit16 output pin
P047 – General-purpose I/O port (3V pin)
70 O
A17 – External bus · Address bit17 output pin
P050 – General-purpose I/O port (3V pin)
74 O
A18 – External bus · Address bit18 output pin
P051 – General-purpose I/O port(3V pin)
75 O
A19 – External bus · Address bit19 output pin
P052 – General-purpose I/O port(3V pin)
76 O
A20 – External bus · Address bit20 output pin

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MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P053 – General-purpose I/O port(3V pin)
77 A21 – O External bus · Address bit21 output pin
SPI_DO – SPI data output pin
P054 – General-purpose I/O port (3V pin)
78 A22 – O External bus · Address bit22 output pin
SPI_DI – SPI data input pin

P055 – General-purpose I/O port (3V pin)

79 A23 – O External bus · Address bit23 output pin
SPI_SCK – SPI clock output pin
P056 – General-purpose I/O port (3V pin)
80 A24 – O External bus · Address bit24 output pin
SPI_XCS – SPI chip select output pin
P057 – General-purpose I/O port (3V pin)
81 O
RDY – External bus · Wait input pin
P060 – General-purpose I/O port
127 PWM1P0 – E SMC ch.0 output pin
AN8 – ADC Analog 8 input pin

P061 – General-purpose I/O port

128 PWM1M0 – E SMC ch.0 output pin
AN9 – ADC Analog 9 input pin
P062 – General-purpose I/O port
129 PWM2P0 – E SMC ch.0 output pin
AN10 – ADC Analog 10 input pin

P063 – General-purpose I/O port

130 PWM2M0 – E SMC ch.0 output pin
AN11 – ADC Analog 11 input pin
P064 – General-purpose I/O port
131 PWM1P1 – E SMC ch.1 output pin
AN12 – ADC Analog 12 input pin

P065 – General-purpose I/O port

132 PWM1M1 – E SMC ch.1 output pin
AN13 – ADC Analog 13 input pin

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 MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P066 – General-purpose I/O port
133 PWM2P1 – E SMC ch.1 output pin
AN14 – ADC Analog 14 input pin
P067 – General-purpose I/O port
134 PWM2M1 – E SMC ch.1 output pin
AN15 – ADC Analog 15 input pin
P070 – General-purpose I/O port
137 PWM1P2 – E SMC ch.2 output pin
AN16 – ADC Analog 16 input pin
P071 – General-purpose I/O port
138 PWM1M2 – E SMC ch.2 output pin
AN17 – ADC Analog 17 input pin
P072 – General-purpose I/O port
139 PWM2P2 – E SMC ch.2 output pin
AN18 – ADC Analog 18 input pin
P073 – General-purpose I/O port
140 PWM2M2 – E SMC ch.2 output pin
AN19 – ADC Analog 19 input pin
P074 – General-purpose I/O port
PWM1P3 – SMC ch.3 output pin
141 E
AN20 – ADC Analog 20 input pin
PPG12_1 – PPG ch.12 output pin (1)
P075 – General-purpose I/O port
PWM1M3 – SMC ch.3 output pin
142 AN21 – E ADC Analog 21 input pin
SIN7_1 – LIN-UART ch.7 serial data input pin
PPG13_1 – PPG ch.13 output pin (1)
P076 – General-purpose I/O port
PWM2P3 – SMC ch.3 output pin
143 AN22 – E ADC Analog 22 input pin
SOT7_1 – LIN-UART ch.7 serial data output pin
PPG14_1 – PPG ch.14 output pin (1)

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MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P077 – General-purpose I/O port
PWM2M3 – SMC ch.3 output pin

144 AN23 – E ADC Analog 23 input pin

SCK7_1 – LIN-UART ch.7 clock I/O pin
PPG15_1 – PPG ch.15 output pin (1)

P080 – General-purpose I/O port

PWM1P4 – SMC ch.4 output pin

147 AN24 – E ADC Analog 24 input pin
SIN6 – LIN-UART ch.6 serial data input pin

PPG16 – PPG ch.16 output pin

P081 – General-purpose I/O port

PWM1M4 – SMC ch.4 output pin

148 AN25 – E ADC Analog 25 input pin
SOT6 – LIN-UART ch.6 serial data output pin
PPG17 – PPG ch.17 output pin

P082 – General-purpose I/O port

PWM2P4 – SMC ch.4 output pin

149 AN26 – E ADC Analog 26 input pin

SCK6 – LIN-UART ch.6 clock I/O pin

PPG18 – PPG ch.18 output pin

P083 – General-purpose I/O port
PWM2M4 – SMC ch.4 output pin
150 AN27 – E ADC Analog 27 input pin
ICU0_2 – Input capture ch.0 input pin (2)
PPG19 – PPG ch.19 output pin
P084 – General-purpose I/O port

PWM1P5 – SMC ch.5 output pin

151 AN28 – E ADC Analog 28 input pin

ICU1_2 – Input capture ch.1 input pin (2)

PPG20 – PPG ch.20 output pin

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 MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P085 – General-purpose I/O port

PWM1M5 – SMC ch.5 output pin

152 AN29 – E ADC Analog 29 input pin

ICU2_2 – Input capture ch.2 input pin (2)

PPG21 – PPG ch.21 output pin

P086 – General-purpose I/O port
PWM2P5 – SMC ch.5 output pin

153 AN30 – E ADC Analog 30 input pin

ICU3_2 – Input capture ch.3 input pin (2)

PPG22 – PPG ch.22 output pin

P087 – General-purpose I/O port

PWM2M5 – SMC ch.5 output pin

154 AN31 – E ADC Analog 31 input pin
ICU4_2 – Input capture ch.4 input pin (2)
PPG23 – PPG ch.23 output pin
P090 – General-purpose I/O port
157 ADTG – A A/D convertor external trigger input pin
PPG0_2 – PPG ch.0 output pin (2)

P091 – General-purpose I/O port

SGA0 – Sound generator ch.0 SGA output pin

SIN2 – LIN-UART ch.2 serial data input pin
98 INT12 – C INT12 External interrupt input pin

TOT2_1 – Reload timer ch.2 output pin (1)

ICU2_1 – Input capture ch.2 input pin (1)

PPG6_1 – PPG ch.6 output pin (1)

P092 – General-purpose I/O port

SGO0 – Sound generator ch.0 SGO output pin

SCK2 – LIN-UART ch.2 clock I/O pin
99 INT13 – C INT13 External interrupt input pin

TOT3_1 – Reload timer ch.3 output pin (1)

ICU0_1 – Input capture ch.0 input pin (1)
PPG7_1 – PPG ch.7 output pin (1)

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MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P093 – General-purpose I/O port

SGA1 – Sound generator ch.1 SGA output pin

SOT2 – LIN-UART ch.2 serial data output pin
100 C
INT14 – INT14 External interrupt input pin
ICU3_1 – Input capture ch.3 input pin (1)
PPG8_1 – PPG ch.8 output pin (1)

P094 – General-purpose I/O port

SGO1 – Sound generator ch.1 SGO output pin

SIN3 – LIN-UART ch.3 serial data input pin
160 C
INT15 – INT15 External interrupt input pin
ICU1_1 – Input capture ch1 input pin (1)
PPG9_1 – PPG ch.9 output pin (1)
P095 – General-purpose I/O port
106 TX0 – A CAN transmission data0 output pin
PPG10_1 – PPG ch.10 output pin (1)

P096 – General-purpose I/O port

107 RX0 – A CAN reception data0 input pin

INT9 – INT9 External interrupt input pin

P097 – General-purpose I/O port

WOT – RTC overflow output pin

SOT3 – LIN-UART ch.3 serial data output pin

161 INT8 – C INT8 External interrupt input pin
TIN0 – Reload timer ch.0 event input pin
ICU4_1 – Input capture ch.4 input pin (1)

PPG0_1 – PPG ch.0 output pin (1)

P100 – General-purpose I/O port

SIN4_1 – LIN-UART ch.4 serial data input pin (1)

114 AN0 – C ADC Analog 0 input pin
TIN0_1 – Reload timer ch.0 event input pin (1)
PPG8 – PPG ch.8 output pin

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 MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P101 – General-purpose I/O port

SOT4_1 – LIN-UART ch.4 serial data output pin (1)

115 AN1 – C ADC Analog 1 input pin

TIN1_1 – Reload timer ch.1 event input pin (1)

PPG9 – PPG ch.9 output pin

P102 – General-purpose I/O port

SCK4_1 – LIN-UART ch.4 clock I/O pin (1)

116 AN2 – C ADC Analog 2 input pin
TIN2_1 – Reload timer ch.2 event input pin (1)

PPG10 – PPG ch.10 output pin

P103 – General-purpose I/O port

SIN5_1 – LIN-UART ch.5 serial data input pin (1)

117 AN3 – C ADC Analog 3 input pin
TIN3_1 – Reload timer ch.3 event input pin (1)
PPG1_1 – PPG ch.1 output pin (1)

P104 – General-purpose I/O port

SOT5_1 – LIN-UART ch.5 serial data output pin (1)

118 AN4 – C ADC Analog 4 input pin
TOT0_1 – Reload timer ch.0 output pin (1)

PPG2_1 – PPG ch.2 output pin (1)

P105 – General-purpose I/O port

SCK5_1 – LIN-UART ch.5 clock I/O pin (1)

119 AN5 – C ADC Analog 5 input pin
TOT1_1 – Reload timer ch.1 output pin (1)
PPG3_1 – PPG ch.3 output pin (1)

P106 – General-purpose I/O port

SGA4_1 – Sound generator ch.4 SGA output pin
120 C
AN6 – ADC Analog 6 input pin
PPG4_1 – PPG ch.4 output pin (1)

P107 – General-purpose I/O port

SGO4_1 – Sound generator ch.4 SGO output pin
121 C
AN7 – ADC Analog 7 input pin

PPG5_1 – PPG ch.5 output pin (1)

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MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P110 – General-purpose I/O port
101 TX1 – C CAN transmission data1 output pin

PPG1_2 – PPG ch.1 output pin (2)

P111 – General-purpose I/O port

RX1 – CAN reception data 1 input pin
102 C
INT10 – INT10 External interrupt input pin
PPG2_2 – PPG ch.2 output pin (2)
P112 – General-purpose I/O port
158 TX2 – C CAN transmission data 2 output pin
PPG3_2 – PPG ch.3 output pin (2)

P113 – General-purpose I/O port

RX2 – CAN reception data 2 input pin
159 C
INT11 – INT11 External interrupt input pin
PPG4_2 – PPG ch.4 output pin (2)

P114 – General-purpose I/O port

SGA2 – Sound generator ch.2 SGA output pin

SCK3 – LIN-UART ch.3 clock I/O pin

162 C
TRG3 – PPG trigger 3 input pin (ch.12 to ch.15)

TIN1 – Reload timer ch.1 event input pin

ICU5_1 – Input capture ch.5 input pin (1)

P115 – General-purpose I/O port

SGO2 – Sound generator ch.2 SGO output pin
163 C
SIN4 – LIN-UART ch.4 serial data input pin
TIN2 – Reload timer ch.2 event input pin

P116 – General-purpose I/O port

SGA3 – Sound generator ch.3 SGA output pin

164 C
SOT4 – LIN-UART ch.4 serial data output pin
TIN3 – Reload timer ch.3 event input pin
P117 – General-purpose I/O port

SGO3 – Sound generator ch.3 SGO output pin

165 SCK4 – C LIN-UART ch.4 clock I/O pin
TRG4 – PPG trigger 4 input pin (ch.16 to ch.19)
TOT0 – Reload timer ch.0 output pin

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 MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P120 – General-purpose I/O port
FRCK1 – Free-run timer 1 clock input pin
SIN5 – LIN-UART ch.5 serial data input pin
166 C
INT6 – INT6 External interrupt input pin
TOT1 – Reload timer ch.1 output pin
PPG5_2 – PPG ch.5 output pin (2)

P121 – General-purpose I/O port

FRCK0 – Free-run timer 0 clock input pin
SOT5 – LIN-UART ch.5 serial data output pin
167 C
INT7 – INT7 External interrupt input pin
TOT2 – Reload timer ch.2 output pin
PPG6_2 – PPG ch.6 output pin (2)

P122 – General-purpose I/O port

OCU0 – Output compare ch.0 output pin

168 SCK5 – C LIN-UART ch.5 clock I/O pin

TOT3 – Reload timer ch.3 output pin

PPG7_2 – PPG ch.7 output pin (2)

P123 – General-purpose I/O port

108 OCU1 – A Output compare ch.1 output pin

PPG8_2 – PPG ch.8 output pin (2)

P124 – General-purpose I/O port

OCU2 – Output compare ch.2 output pin
109 A
ICU5_2 – Input capture ch.5 input pin (2)
PPG9_2 – PPG ch.9 output pin (2)
P125 – General-purpose I/O port
OCU3 – Output compare ch.3 output pin
110 A
ICU0 – Input capture ch.0 input pin
PPG10_2 – PPG ch.10 output pin (2)
P126 – General-purpose I/O port
TRG0 – PPG trigger 0 input pin (ch.0 to ch.3)
90 A
SIN0 – Multi-UART ch.0 serial data input pin

INT1 – INT1 External interrupt input pin

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MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
P127 – General-purpose I/O port
91 K Multi-UART ch.0 serial data output pin / I2C ch.0 serial data
SOT0 – I/O pin
P130 – General-purpose I/O port

SCK0 – Multi-UART ch.0 clock I/O pin / I2C ch.0 clock I/O pin
92 INT0 – K INT0 External interrupt input pin
ICU1 – Input capture ch.1 input pin
TIOA0 – Base timer TIOA0 output pin

P131 – General-purpose I/O port

TRG1 – PPG trigger 1 input pin (ch.4 to ch.7)

SIN1 – Multi-UART ch.1 serial data input pin

93 A
INT4 – INT4 External interrupt input pin
ICU2 – Input capture ch.2 input pin
TIOA1 – Base timer TIOA1 I/O pin

P132 – General-purpose I/O port

Multi-UART ch.1 serial data output pin / I2C ch.1 serial data
SOT1 –
I/O pin
94 INT2 – K INT2 External interrupt input pin

ICU3 – Input capture ch.3 input pin

TIOB0 – Base timer TIOB0 input pin

P133 – General-purpose I/O port

TRG5 – PPG trigger 5 input pin ( ch.20 to ch.23)
PPG11_1 – PPG ch.11 output pin (1)
95 SCK1 – K Multi-UART ch.1 clock I/O pin / I2C ch.1 clock I/O pin
INT3 – INT3 External interrupt input pin
ICU4 – Input capture ch.4 input pin
TIOB1 – Base timer TIOB1 input pin
P134 – General-purpose I/O port
TRG2 – PPG trigger 2 input pin ( ch.8 to ch.11)

96 PPG1_3 – A PPG ch.1 output pin (3)

INT5 – INT5 External interrupt input pin

ICU5 – Input capture ch.5 input pin

103 DEBUGIF – G DEBUG I/F pin

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 MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
PA2 – General-purpose I/O port (3V pin)
176 RIN2 – O Capture R2 input pin (RGB mode)
VIN0 – Capture VIN0 input pin (656 mode)
PA3 – General-purpose I/O port (3V pin)
177 RIN3 – O Capture R3 input pin (RGB mode)
VIN1 – Capture VIN1 input pin (656 mode)
PA4 – General-purpose I/O port (3V pin)
178 RIN4 – O Capture R4 input pin (RGB mode)
VIN2 – Capture VIN2 input pin (656 mode)
PA5 – General-purpose I/O port (3V pin)
179 RIN5 – O Capture R5 input pin (RGB mode)
VIN3 – Capture VIN3 input pin (656 mode)

PA6 – General-purpose I/O port (3V pin)

180 RIN6 – O Capture R6 input pin (RGB mode)
VIN4 – Capture VIN4 input pin (656 mode)
PA7 – General-purpose I/O port (3V pin)

181 RIN7 – O Capture R7 input pin (RGB mode)

VIN5 – Capture VIN5 input pin (656 mode)

PB2 – General-purpose I/O port (3V pin)

182 GIN2 – O Capture G2 input pin (RGB mode)
VIN6 – Capture VIN6 input pin (656 mode)
PB3 – General-purpose I/O port (3V pin)
183 GIN3 – O Capture G3 input pin (RGB mode)
VIN7 – Capture VIN7 input pin (656 mode)
PB4 – General-purpose I/O port (3V pin)
184 O
GIN4 – Capture G4 input pin (RGB mode)
PB5 – General-purpose I/O port (3V pin)
185 O
GIN5 – Capture G5 input pin (RGB mode)
PB6 – General-purpose I/O port (3V pin)
186 O
GIN6 – Capture G6 input pin (RGB mode)
PB7 – General-purpose I/O port (3V pin)
187 O
GIN7 – Capture G7 input pin (RGB mode)
PC2 – General-purpose I/O port (3V pin)
190 O
BIN2 – Capture B2 input pin (RGB mode)

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MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
PC3 – General-purpose I/O port (3V pin)
191 O
BIN3 – Capture B3 input pin (RGB mode)
PC4 – General-purpose I/O port (3V pin)
192 O
BIN4 – Capture B4 input pin (RGB mode)
PC5 – General-purpose I/O port (3V pin)
193 O
BIN5 – Capture B5 input pin (RGB mode)
PC6 – General-purpose I/O port (3V pin)
194 O
BIN6 – Capture B6 input pin (RGB mode)
PC7 – General-purpose I/O port (3V pin)
195 O
BIN7 – Capture B7 input pin (RGB mode)
PD2 – General-purpose I/O port (3V pin)
2 O
ROUT2 – Display digital R2 output pin
PD3 – General-purpose I/O port (3V pin)
3 O
ROUT3 – Display digital R3 output pin
PD4 – General-purpose I/O port (3V pin)
4 O
ROUT4 – Display digital R4 output pin
PD5 – General-purpose I/O port (3V pin)
5 O
ROUT5 – Display digital R5 output pin
PD6 – General-purpose I/O port (3V pin)
6 O
ROUT6 – Display digital R6 output pin
PD7 – General-purpose I/O port (3V pin)
7 O
ROUT7 – Display digital R7 output pin
PE2 – General-purpose I/O port (3V pin)
8 O
GOUT2 – Display digital G2 output pin
PE3 – General-purpose I/O port (3V pin)
9 O
GOUT3 – Display digital G3 output pin
PE4 – General-purpose I/O port (3V pin)
10 O
GOUT4 – Display digital G4 output pin
PE5 – General-purpose I/O port (3V pin)
11 O
GOUT5 – Display digital G5 output pin
PE6 – General-purpose I/O port (3V pin)
12 O
GOUT6 – Display digital G6 output pin
PE7 – General-purpose I/O port (3V pin)
13 O
GOUT7 – Display digital G7 output pin

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 MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
PF2 – General-purpose I/O port (3V pin)
14 O
BOUT2 – Display digital B2 output pin
PF3 – General-purpose I/O port (3V pin)
15 O
BOUT3 – Display digital B3 output pin
PF4 – General-purpose I/O port (3V pin)
16 O
BOUT4 – Display digital B4 output pin
PF5 – General-purpose I/O port (3V pin)
17 O
BOUT5 – Display digital B5 output pin
PF6 – General-purpose I/O port (3V pin)
21 O
BOUT6 – Display digital B6 output pin

PF7 – General-purpose I/O port(3V pin)

22 O
BOUT7 – Display digital B7 output pin
PG0 – General-purpose I/O port (3V pin)

200 DCKIN – O Display reference clock input pin (for External sync)
CMDTRG – GDC command trigger input pin
PG1 – General-purpose I/O port (3V pin)
197 O
VSIN P Capture vertical sync signal input pin
PG2 – General-purpose I/O port (3V pin)
198 O
HSIN P Capture horizontal sync signal input pin
PG3 – General-purpose I/O port (3V pin)
199 O Display composite sync signal output pin, Graphics /
CSOUT –
Video switch (for External sync) output pin
PG4 – General-purpose I/O port (3V pin)
23 O
DCKOUT – Display reference clock output pin (for Internal sync)
PG5 – General-purpose I/O port (3V pin)
24 O Display vertical sync signal output pin (for Internal sync)/
VSYNC – Display vertical sync signal input pin (for External sync)
PG6 – General-purpose I/O port (3V pin)
25 O Display horizontal sync signal output pin (for Internal sync)/
HSYNC –
Display horizontal sync signal input pin (for External sync)
PG7 – General-purpose I/O port (3V pin)
26 O
DEOUT P Display enable display period output pin
PH3 – General-purpose I/O port (3V pin)
196 O
CCLK – For capture, capture clock input pin
204 REFOUT – T Clamp level output pin
203 AVR3 – S "L" side reference voltage for NTSC A/D converter pin

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MB91590 Series

I/O
Pin no. Pin Name Polarity circuit Function *2
types*1
205 VIN – S NTSC signal input pin
111 AVCC5 – – AD convertor analog power supply pin

201, 207 AVCC3 – – For NTSC, AD convertor analog power supply pin
112 AVRH5 – – AD convertor upper limit reference voltage pin
AVSS5/ AD convertor GND/ AD convertor lower limit reference
113 – –
AVRL5 voltage pin
202, 206 AVSS3 – – NTSC AD convertor GND pin
124 C_1 – – Built-in regulator capacitor connected pin 1
73 C_2 – – Built-in regulator capacitor connected pin 2
20 C_3 – – Built-in regulator capacitor connected pin 3
126,
136,146, DVCC – – SMC large current port power supply pin
156
125, 135,
DVSS – – SMC large current port GND pin
145, 155
89, 105,
VCC5 – – +5.0v power supply pin
122, 173
1, 18, 37,
53, 71, VCC3 – – +3.3v power supply pin
175, 189
19, 36,
52, 72,
82, 88,
VSS – – GND pin
104, 123,
174, 188,
208
*1: For the I/O circuit types, see “ I/O CIRCUIT TYPE”.
*2: For switching, see “I/O Port” of HARDWARE MANUAL.

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 MB91590 Series

 I/O CIRCUIT TYPE

Type Circuit Remarks
A Pull-up control
• General-purpose I/O port
• Output 1mA,2mA
• Pull-up resistor control 50kΩ
Digital output
• Pull-down resistor control 50kΩ
Digital output
• CMOS input
• Schmitt input
Pull-down control
• TTL input
• Automotive input
CMOS-hys input

Standby control

CMOS input

Standby control

Automotive input

Standby control

TTL input

Standby control

C Pull-up control
• Analog I/O, General-purpose I/O port
• Output 1mA,2mA
Digital output
• Pull-up resistor control 50kΩ
• Pull-down resistor control 50kΩ
Digital output
• CMOS input
• Schmitt input
Pull-down control
• TTL input
• Automotive input
CMOS-hys input

Standby control

CMOS input

Standby control

Automotive input

Standby control

TTL input

Standby control

Analog input

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MB91590 Series

Type Circuit Remarks

E Pull-up control
• Analog input, General-purpose I/O port
• Output 1mA,2mA,30mA (large current for SMC)
Digital output
• Pull-up resistor control 50kΩ
• Pull-down resistor control 50kΩ
Digital output
• CMOS input
• Schmitt input
Pull-down control
• TTL input
• Automotive input
CMOS-hys input

Stnadby control

CMOS input

Stnadby control

Automotive input

Stnadby control

TTL input

Stnadby control

Analog input

F1 • Schmitt input
• Pull-up resistor control 50kΩ (5V cont)

CMOS-hys input

F2 • Schmitt input
• Pull-down resistor control 50kΩ (5V cont)

CMOS-hys input

G • Open-drain I/O
• Output 25mA (NOD)
• TTL input

TTL input

J Automotive input

Automotive input

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 MB91590 Series

Type Circuit Remarks

K • Analog input, General-purpose I/O port
Pull-up control
• Output 1mA,2mA,3mA(I2C)
• Pull-up resistor control 50kΩ
Digital output • Pull-down resistor control 50kΩ
• CMOS input
Digital output • Schmitt input
• TTL input
• Automotive input
Pull-down control

CMOS-hys input

Standby control

CMOS input

Standby control

Automotive input

Standby control

TTL input

Standby control
Analog input

L Input Main oscillation I/O

Standby control

N Input Sub oscillation I/O

Standby control

O • Analog input, 3.3V General-purpose I/O port

Pull-up control
• Output 2mA,5mA,10mA and 20mA
• Pull-up resistor control 33kΩ
Digital output • Pull-down resistor control 33kΩ
• Schmitt input
Digital output • TTL input

Pull-down control

CMOS-hys input

Standby control

TTL input

Standby control

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Type Circuit Remarks

P • Mode I/O
• Schmitt input

Mode input

Control

S Analog input Analog input(3V)

T Analog output(3V)
Analog output

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 HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your FUJITSU SEMICONDUCTOR semiconductor devices.

1. Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

 Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.

 Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.

 Processing and Protection of Pins

These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.

(1) Preventing Over-Voltage and Over-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.

(2) Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.

Therefore, avoid this type of connection.

(3) Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.

Code: DS00-00004-1E

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 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:

(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include
attention to abnormal noise, surge levels, etc.

(2) Be sure that abnormal current flows do not occur during the power-on sequence.

 Observance of Safety Regulations and Standards

Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.

 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.

 Precautions Related to Usage of Devices

FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications
(computers, office automation and other office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.

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2. Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under FUJITSU SEMICONDUCTOR's recommended conditions.
For detailed information about mount conditions, contact your sales representative.

 Lead Insertion Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended
mounting conditions.

If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.

 Surface Mount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder
reflow method, and has established a ranking of mounting conditions for each product. Users are advised to
mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions.

 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.

 Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:

(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.

(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.

When you open Dry Package that recommends humidity 40% to 70% relative humidity.

(3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly

moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their
aluminum laminate bags for storage.

(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

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 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU
SEMICONDUCTOR recommended conditions for baking.

Condition: 125°C/24 h

 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:

(1) Maintain relative humidity in the working environment between 40% and 70%.

Use of an apparatus for ion generation may be needed to remove electricity.

(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.

(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).

Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize
shock loads is recommended.

(4) Ground all fixtures and instruments, or protect with anti-static measures.

(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.

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3. Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.

For reliable performance, do the following:

(1) Humidity

Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.

(2) Discharge of Static Electricity

When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation.
In such cases, use anti-static measures or processing to prevent discharges.

(3) Corrosive Gases, Dust, or Oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely
affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to
protect the devices.

(4) Radiation, Including Cosmic Radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users
should provide shielding as appropriate.

(5) Smoke, Flame

CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.

Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental
conditions should consult with sales representatives.

Please check the latest handling precautions at the following URL.

http://edevice.fujitsu.com/fj/handling-e.pdf

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 HANDLING DEVICES
This section explains the latch-up prevention and treatment of a pin.

 For latch-up prevention

If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding
the ratings is applied between VCC pin and VSS pin, a latch-up may occur in CMOS IC. If the latch-up
occurs, the power supply current increases excessively and device elements may be damaged by heat. Take
care to prevent any voltage from exceeding the maximum ratings in device application.

Also, the analog power supply (AVCC5, AVRH5), the NTSC power supply (AVCC3, AVR3), analog input
and power supply to high-current output buffer pins must not be exceed the digital power supply (VCC5 or
VCC3) when the power supply to the analog system and high-current output buffer pins is turned on or off.

In the correct power-on sequence of the microcontroller, turn on the digital power supply (VCC5), analog
power supplies (AVCC5, AVRH5), and the power supply of high-current output buffer pins (DVCC)
simultaneously. Or, turn on the digital power supply (VCC5), and then turn on analog power supplies
(AVCC5, AVRH5) and the power supply of high-current output buffer pins (DVCC).

In the correct power-on sequence of GDC, similarly turn on the digital power supply (VCC3) and the NTSC
analog power supply (AVCC3) simultaneously. Or, turn on the digital power supply (VCC3), and then turn
on the NTSC analog power supply (AVCC3).

 Treatment of unused pins

If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or
latch-up. Connect a 2kΩ resistor to each of unused pins for pull-up or pull-down processing.

Also, if I/O pins are not used, they must be set to the output state for opening or they must be set to the
input state and treated in the same way as for the input pins.

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 Power supply pins

The device is designed to ensure that if the device contains multiple VCC pin or VSS pin, the pins that
should be at the same potential are interconnected to prevent latch-up or other malfunctions. Further,
connect these pins to an external power supply or ground to reduce unwanted radiation, prevent strobe
signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc.
As shown in figure 1, all Vss power supply pins must be treated in the similar way. If multiple Vcc or Vss
systems are connected, the device cannot operate correctly even within the guaranteed operating range.

Figure 1 Power Supply Input Pins

Vcc
Vss

Vcc Vss
Vss

Vcc Vcc

Vss
Vss Vcc

The power supply pins should be connected to VCC pin and VSS pin of this device at the low impedance
from the power supply source.

In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin
is recommended to use as a bypass capacitor between theVCC pin and the VSS pin.

 Crystal oscillation circuit

An external noise to the X0 pin or X1 pin may cause a device malfunction. The printed circuit board must
be designed to lay out the X0 pin and the X1 pin, crystal oscillator (or ceramic resonator), and the bypass
capacitor to be grounded to the close position to the device.

The printed circuit board artwork is recommended to surround the X0 pin and X1 pin by ground circuits.

 Mode pins (MD2, MD1, MD0)

Connect the MD2, MD1and MD0 mode pin to the VCC pin or VSS pin directly. To prevent an erroneous
selection of test mode caused by the noise, reduce the pattern length between each mode pin and the VCC
pin or VSS pin on the printed circuit board. Also, use the low-impedance pin connection.

 During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to
have 50μs or longer (between 0.2V and 2.7V) during power-on.

 Notes during PLL clock operation

When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock
may continue to operate at the free running frequency of the self oscillator circuit built in the PLL clock.
This operation is not guaranteed.

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 Treatment of A/D converter power supply pins

Connect the pins to have AVCC5=AVRH5=VCC5 and AVSS5/AVRL5=VSS even if the A/D converter is
not used.

Also, similarly connect the pins of NTSC A/D converter power supply to have AVCC3=VCC3 and
AVSS3=VSS. At this time, open VIN/REFOUT.

 Notes on using external clock

An external clock is not supported. None of the external direct clock input can be used for both main clock
and sub clock.

 Power-on sequence of A/D converter analog inputs

Be sure to turn on the digital power supply (Vcc5) first, and then turn on the A/D converter power supplies
(AVcc5, AVRH5, AVRL5) and analog inputs (AN0 to AN31). Also, turn off the A/D converter power
supplies and analog inputs first, and then turn off the digital power supply (Vcc5). When the AVRH5 pin
voltage is turned on or off, it must not exceed AVCC5. Even if a common analog input pin is used as an
input port, its input voltage must not exceed AVcc5. (However, the analog power supply and digital power
supply can be turned on or off simultaneously.)

Be sure to similarly turn on the digital power supply (VCC3) first, and then turn on the A/D converter
power supply (AVCC3) for NTSC and NTSC inputs (VIN, AVR). Also, turn off the A/D converter power
supplies and analog inputs first, and then turn off the digital power supply (VCC3).

 Treatment of power supplies for high current output buffer pins (DVcc,
DVss)
Be sure to turn on the digital power supply (Vcc) first, and then turn on the power supplies for high current
output buffer pins (DVcc, DVss). Also, turn off the power supplies for high current output buffer pins first,
and then turn off the digital power supply (Vcc).

Even if the high current output buffer pins are used as general-purpose ports, the power supplies of high
current output buffer pins (DVcc, DVss) must be powered. (The power supplies of high current output
buffer pins and the digital power supplies can be turned on or off simultaneously. )

 Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to
assure the internal stabilization of the device. For the standard values, see the "Recommended Operating
Conditions" of the latest data sheet.

 Function switching of a multiplexed port

To switch between the port function and the multiplexed pin function, use the PFR (port function
register).

 Low-power consumption mode

To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off),
follow the procedure explained in the "Activating the sleep mode, watch mode, or stop mode" or the
"Activating the watch mode (power-off) or stop mode(power-off)" of " POWER CONSUMPTION
CONTROL".

Power supply for GDC can be turned off separately from the microcontroller.

Take the following notes when using a monitor debugger.

· Do not set a break point for the low-power consumption transition program.
· Do not execute an operation step for the low-power consumption transition program.

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 MB91590 Series

 Precautions when writing to registers including the status flag

When writing data in the register that has a status flag (especially, an interrupt request flag) to control
function, taking care not to clear its status flag erroneously must be followed.

The program must be written not to clear the flag to the status bit, and then to set the control bits to have the
desired value.

Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can
access to a single bit only.) By the Byte, Half-word, or Word access, data is written to the control bits and
status flag simultaneously. During this time, take care not to clear other bits (in this case, the bits of status
flag) erroneously.

Note: These points can be ignored because the bit instructions to a register which supports RMW are
already taken the points into consideration. Care must be taken when the bit instruction is used to a
register which does not support RMW.

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 BLOCK DIAGRAM

FR81S CPU Core

I/O

NTSC
clamp ADC Decoder
Camera Video
Frame buffer
capture Regulator

Power-on Reset MPU

Debug Interface
Pixel Instruction Data
FIFO CR oscillator
I/O ( Digital RGB)

XBS
Line Sprite Line
Buffer Engine Engine Wild register XBS Crossbar Switch
Display
External Controller
LCD RAM
Command
Bus Bridge RAM
Flash
decoder · Main Flash
AHB · WorkFlash 64KB
bus From Master

On chip bus
To Slave On chip bus layer 2
bridge
asynchro From Master
nous To Slave
On chip bus layer 1
type

SIG RLD DMA Ext.

BUS Bus master
Ext.bus I/F RAM ECC Control
(XBS -RAM) DMAC
Regi ster
Peripheral Bus
CAN (3ch)
Bridge Bus performance
I/O (Ext. bus) counter

External bus pin Bus bridge 16 32

(For GDC external memory)
Operation mode
RDY, A00-24,
WEX,REX, register
CS0X,CS1X,
D0-15
RAM ECC Backup
Control -RAM
MD0,MD1,MD2,P127
CANRX0-2, Asynchronous BUS
External CANTX0-2
bridge
FLASH (PCLK1 ↔ PCLK2)
memory
(For video) Asynchronous BUS
CAN Prescaler
bridge

32-bit Peripheral bus

RTC/WDT1 Calibration (PCLK1 ↔ PCLK2)

CRC

16-bit Peripheral bus

I/O port setting

SOT2-7,SIN2-7,
Lin-UART (6ch) Sound generator (5ch)
SGO0-4,SGA0-4
SCK2-7

SOT0-1,SIN0-1,
Multi-function serial interface (2ch)

16-bit Peripheral bus

SCK0-1

Free-run timer (2ch)

FRCK0-1

I/O Port
Input capture (6ch)
I/O Port

ICU0-5

Bus Bridge
OCU0-3 Output compare(4ch) (32-bit → 16-bit)

TIOA0-1,
Base-timer (2ch) External interrupt input (16ch)
INT0-15,

TIOB0-1 Input interception

inhibiting signal

TRG0-5,
PPG (24ch) Real time clock
PPG0-23 WOT

A/D converter Clock supervisor

ADTG, AN0-31

GDC external control

NMI NMIX

Stepping motor controller (6ch) Low-voltage detection (Int. power supply low-voltage detection)
PWM1M0-5,
PWM1P0-5, Low-voltage detection (Ext. power supply low-voltage detection)
PWM2M0-5
Clock control
(Clock setting, Main timer, Sub timer, PLL timer)
Reload timer (4ch)
TIN0-3,TOT0-3

Clock control (divide setting), RSTX

Reset control,
Low-power consumption
control
Watchdog timer (SW and HW)
Delay interrupt
Generation and clear of DMA transfer request
Interrupt controller
Interrupt request batch read

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 MEMORY MAP
 Memory map

MB91F599B/S,
MB91F599BH/S,
MB91F594B/S,
MB91F594BH/S
0000 0000H
I/O
0000 4000H Back up RAM (8KB)
0000 6000H
I/O
0001 0000H
RAM (64KB)

0002 0000H
Reserved

0003 0000H AHB

Access inhibit

0007 0000H

Flash memory
(1024+64) KB

0018 0000H
Access inhibit
0023 0000H
WorkFlash (64KB)
0024 0000H
Access inhibit
0040 0000H AHB
GDC control +
External area (96MB)

0640 0000H

8000 0000H Access inhibit

FFFF FFFFH

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 GDC memory map

MB91F599B/S,
MB91F599BH/S,
GDC Block MB91F594B/S,
MB91F594BH/S
0040 0000H 0000 0000H
Video RAM (800KB) I/O
004C 8000H 0000 4000H Back up RAM (8KB)
Reserved
0000 6000H
00C0 0000H Command RAM I/O
(8KB)
00C0 2000H Reserved 0001 0000H
00E0 0000H RAM (64KB)
Access prohibit

0230 0000H Reserved (636KB) 0002 0000H

0239 F000H Command (4KB) Reserved
023A 0000H Reserved (64KB)
023B 0000H SIG (4KB) 0003 0000H AHB
023B 1000H NTSC (4KB)
023B 2000H MCNT (4KB)
GDC I/O Access inhibit
023B 3000H MEMC (4KB)
023B 4000H HDMAC (4KB)
023B 5000H RLD (4KB)
023B 6000H Reserved (64KB) 0007 0000H
023B 7000H CMDSEQ (4KB)
023B 8000H SPRITE (32KB) Flash memory
023C 0000H GDC_Bridge (64KB) (1024+64) KB
023D 0000H Display (32KB)
023D 8000H Capture (32KB)
023E 0000H Reserved (64KB) 0018 0000H
Access inhibit
023F 0000H Draw (32KB)
023F 8000H Reserved (32KB) 0023 0000H
0240 0000H
WorkFlash (64KB)
External FLASH
(64MB)
0024 0000H
063F FFFCH
Access inhibit
0040 0000H AHB
GDC control +
External area
(96MB)
0640 0000H

8000 0000H Access inhibit

FFFF FFFFH

Note: The GDC area is executed mapping with the little endian.

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 Memory map

MB91F597B/S,
MB91F597BH/S,
MB91F592B/S,
MB91F592BH/S
0000 0000H
I/O
0000 4000H Back up RAM (8KB)
0000 6000H
I/O
0001 0000H
RAM (40KB)

0001 A000H
Reserved

0003 0000H AHB

Access inhibit

0007 0000H

Flash memory
(512+64) KB

0010 0000H
Access inhibit
0023 0000H
WorkFlash (64KB)
0024 0000H
Access inhibit
0040 0000H AHB
GDC control +
External area (96MB)

0640 0000H

8000 0000H Access inhibit

FFFF FFFFH

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 GDC memory map

MB91F597B/S,
MB91F597BH/S,
GDC Block MB91F592B/S,
MB91F592BH/S
0040 0000H 0000 0000H
Video RAM (800KB) I/O
004C 8000H 0000 4000H Back up RAM (8KB)
Reserved
0000 6000H
00C0 0000H Command RAM I/O
(8KB)
00C0 2000H Reserved 0001 0000H
00E0 0000H RAM (40KB)
Access inhibit

0230 0000H Reserved (636KB) 0001 A000H

0239 F000H Command( 4KB) Reserved
023A 0000H Reserved (64KB)
023B 0000H SIG (4KB) 0003 0000H AHB
023B 1000H NTSC (4KB)
023B 2000H MCNT (4KB)
GDC I/O Access inhibit
023B 3000H MEMC (4KB)
023B 4000H HDMAC (4KB)
023B 5000H RLD (4KB)
023B 6000H Reserved (64KB) 0007 0000H
023B 7000H CMDSEQ (4KB)
023B 8000H SPRITE (32KB) Flash memory
023C 0000H GDC_Bridge (64KB) (512+64) KB
023D 0000H Display (32KB)
023D 8000H Capture (32KB)
023E 0000H Reserved (64KB) 0010 0000H
Access inhibit
023F 0000H Draw (32KB)
023F 8000H Reserved (32KB) 0023 0000H
WorkFlash (64KB)
0240 0000H
External FLASH
(64MB)
0024 0000H
063F FFFCH
Access inhibit
0040 0000H AHB
GDC control +
External area
(96MB)
0640 0000H

8000 0000H Access inhibit

FFFF FFFFH

Note: The GDC area is executed mapping with the little endian.

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 Memory map

MB91F596B/S,
MB91F596BH/S,
MB91F591B/S,
MB91F591BH/S
0000 0000H
I/O
0000 4000H Back up RAM (8KB)
0000 6000H
I/O
0001 0000H
RAM (40KB)

0001 A000H
Reserved

0003 0000H AHB

Access inhibit

0007 0000H

Flash memory
(512+64) KB

0010 0000H
Access inhibit
0023 0000H
WorkFlash (64KB)
0024 0000H
Access inhibit
0040 0000H AHB
GDC control +
External area (96MB)

0640 0000H

8000 0000H Access inhibit

FFFF FFFFH

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 GDC memory map

MB91F596B/S,
MB91F596BH/S,
GDC Block MB91F591B/S,
MB91F591BH/S
0040 0000H 0000 0000H
Video RAM (260KB) I/O
0044 1000H 0000 4000H Back up RAM (8KB)
Reserved
0000 6000H
00C0 0000H Command RAM I/O
(8KB)
00C0 2000H Reserved 0001 0000H
00E0 0000H RAM (40KB)
Access prohibit

0230 0000H Reserved (636KB) 0001 A000H

0239 F000H Command (4KB) Reserved
023A 0000H Reserved (64KB)
023B 0000H SIG (4KB) 0003 0000H AHB
023B 1000H NTSC (4KB)
023B 2000H MCNT (4KB)
GDC I/O Access inhibit
023B 3000H MEMC (4KB)
023B 4000H HDMAC (4KB)
023B 5000H RLD (4KB)
023B 6000H Reserved (64KB) 0007 0000H
023B 7000H CMDSEQ (4KB)
023B 8000H SPRITE (32KB) Flash memory
023C 0000H GDC_Bridge (64KB) (512+64) KB
023D 0000H Display (32KB)
023D 8000H Capture (32KB)
023E 0000H Reserved (64KB) 0010 0000H
Access inhibit
023F 0000H Draw (32KB)
023F 8000H Reserved (32KB) 0023 0000H
WorkFlash (64KB)
0240 0000H
External FLASH
(64MB)
0024 0000H
063F FFFCH
Access inhibit
0040 0000H AHB
GDC control +
External area
(96MB)
0640 0000H

8000 0000H Access inhibit

FFFF FFFFH

Note: The GDC area is executed mapping with the little endian.

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 MB91590 Series

 I/O MAP

The following I/O map shows the relationship between memory space and registers for peripheral
resources.

• Legend of I/O Map

Read/Write attribute (R: Read W: Write)

Address offset value/ register name

Address Block
+0 +1 +2 +3
BT1TMR[R] H BT1TMCR[R/W]B,H,W
000090H
0000000000000000 00000000 00000000
BT1STC[R/W]
000094 H - - -
B00000000
Base timer 1
BT1PCSR/BT1PRLL[R /W] H BT1PDU T/BT1PRLH/BT1DTBF[R/W] H
000098 H
0000000000000000 0000000000000000
BTSEL[R/W] B BTSSSR[W] B,H
00009C H -
----000 0 -------- ------11
ADERH [R/W]B, H, W ADERL [R/W]B, H, W
0000A0 H
00000000 00000000 00000000 00000000
ADCS1 [R/W] B, H,W ADCS0 [R/W] B, H,W ADCR1 [R] B, H,W ADCR0 [R] B, H,W
0000A4 H A/D converter
00000000 00000000 ------XX XXXXX XXX
ADCT1 [R/W] B, H,W ADCT0 [R/W] B, H,W ADSCH [R/W] B, H,W ADECH [R/W] B, H,W
0000A8 H
00010000 00101100 ---00000 ---00000

Data access attribute

B: Byte
H: Half-word
W: Word
(Note)The access by the data
access attribute not described
is disabled.

Initial register value after reset

The initial register value after reset indicates as follows:

· "1": Initial value "1"

· "0": Initial value "0"
· "X": Initial value undefined
· "-": Reserved bit/Undefined bit
· "*": Initial value "0" or "1" according to the setting

Note: The access by the data access attribute not described is disabled.

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MB91590 Series

• I/O Map
Address offset value / Register name
Address Block
+0 +1 +2 +3
PDR00[R/W] PDR01[R/W] PDR02[R/W] PDR03[R/W]
000000H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PDR04[R/W] PDR05[R/W] PDR06[R/W] PDR07[R/W]
000004H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PDR08[R/W] PDR09[R/W] PDR10[R/W] PDR11[R/W]
000008H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Port data register
PDR12[R/W] PDR13[R/W]
00000CH B,H,W B,H,W ― ―
XXXXXXXX XX-XXXXX
PDRA[R/W] PDRB[R/W] PDRC[R/W] PDRD[R/W]
000010H B,H,W B,H,W B,H,W B,H,W
XXXXXX-- XXXXXX-- XXXXXX-- XXXXXX--
PDRE[R/W] PDRF[R/W] PDRG[R/W] PDRH[R/W]
000014H B,H,W B,H,W B,H,W B,H,W
XXXXXX-- XXXXXX-- XXXXXXXX ----X---
000018H
to ― ― ― ― Reserved
000028H
00002CH
to ― ― ― ― Reserved
000030H
000034H
to ― ― ― ― Reserved
000038H
WDTCR0[R/W] WDTCPR0[W] WDTCR1[R] WDTCPR1[W]
00003CH B,H,W B,H,W B,H,W B,H,W Watchdog timer [S]
-0--0000 00000000 ----0110 00000000

000040H ― ― ― ― Reserved

DICR [R/W]
000044H B ― ― ― Delay interrupt
XXXXXXX0
000048H
to ― ― ― ― Reserved
00005CH
TMRLRA0 [R/W] H TMR0 [R] H
000060H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 0
TMRLRB0 [R/W] H TMCSR0 [R/W] B, H,W
000064H
XXXXXXXX XXXXXXXX 00000000 0-000000
000068H
to ― ― ― ― Reserved
00007CH

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 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
BT0TMR [R] H BT0TMCR [R/W] H
000080H
0000000000000000 -0000000 00000000
BT0STC
000084H ― [R/W] B ― ―
0000-000 Base timer 0
BT0PCSR/BT0PRLL BT0PDUT/BT0PRLH/BT0DTBF
000088H [R/W] H [R/W] H
0000000000000000 0000000000000000
00008CH ― ― ― ―
BT1TMR [R] H BT1TMCR [R/W] H
000090H
0000000000000000 -0000000 00000000
BT1STC
000094H ― [R/W] B ― ―
Base timer 1
0000-000
BT1PCSR/BT1PRLL BT1PDUT/BT1PRLH/BT1DTBF
000098H [R/W] H [R/W] H
0000000000000000 0000000000000000
BTSEL01 BTSSSR
00009CH [R/W] B ― [W] B,H Base timer 0,1
----0000 -------- ------11
ADERH [R/W] B, H, W ADERL [R/W] B, H, W
0000A0H
00000000 00000000 00000000 00000000
ADCS1 ADCS0 ADCR1 ADCR0
0000A4H [R/W] B, H,W [R/W] B, H,W [R] B, H,W [R] B, H,W
A/D converter
0000000- 00000000 ------XX XXXXXXXX
ADCT1 [R/W] ADCT0 [R/W] ADSCH [R/W] ADECH [R/W]
0000A8H B, H,W B, H,W B, H,W B, H,W
00010000 00101100 ---00000 ---00000
0000ACH ― ― ― ― Reserved
SCR0/(IBCR0) SMR0 SSR0 ESCR0/(IBSR0)
0000B0H [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W Multi-UART0
0--00000 000-0000 0-000011 -0000000
RDR0/(TDR0)[R/W] B,H,W *1 BGR0 [R/W] H,W *1 : Byte access is
0000B4H possible only for
-------0 00000000 00000000 00000000
access to lower 8 bits
― / (ISMK0) ― / (ISBA0)
0000B8H [R/W] B,H,W [R/W] B,H,W ― ― *2 : Reserved
-------- *2 -------- *2 because I2C mode is
FCR10 [R/W] FCR00 [R/W] FBYTE20 FBYTE10 not set immediately
0000BCH B,H,W B,H,W [R/W] B,H,W [R/W] B,H,W after reset.
---00100 -0000000 00000000 00000000

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MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
SCR1/(IBCR1) SMR1 [R/W] SSR1 [R/W] ESCR1/(IBSR1)
0000C0H [R/W] B,H,W B,H,W B,H,W [R/W] B,H,W Multi-UART1
0--00000 000-0000 0-000011 -0000000
RDR1/(TDR1)[R/W] B,H,W *1 BGR1 [R/W] H,W *1 : Byte access is
0000C4H possible only for
-------0 00000000 00000000 00000000
access to lower 8 bits
― / (ISMK1) ― /( ISBA1)
0000C8H [R/W] B,H,W [R/W] B,H,W ― ― *2 : Reserved
-------- *2 -------- *2 because I2C mode is
FCR11 [R/W] FCR01[R/W] FBYTE21 FBYTE11[R/W] not set immediately
0000CCH B, H, W B, H, W [R/W] B,H,W B,H,W after reset.
---00100 -0000000 00000000 00000000
SCR2 [R/W] SMR2 [R/W] SSR2 [R/W] RDR2 /TDR2
0000D0H B, H, W B, H, W B, H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART2
ESCR2 [R/W] ECCR2 [R/W]
BGR2 [R/W] B, H, W
0000D4H B, H, W B, H, W
-0000000 00000000
00000X00 -0000-XX
SCR3 [R/W] SMR3 [R/W] SSR3 [R/W] RDR3 /TDR3
0000D8H B, H, W B, H, W B, H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART3
ESCR3 [R/W] ECCR3 [R/W]
BGR3 [R/W] B, H, W
0000DCH B, H, W B, H, W
-0000000 00000000
00000X00 -0000-XX
SCR4 [R/W] SMR4 [R/W] SSR4 [R/W] RDR4 /TDR4
0000E0H B, H, W B, H, W B, H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART4
ESCR4 [R/W] ECCR4 [R/W]
BGR4 [R/W] B, H, W
0000E4H B, H, W B, H, W
-0000000 00000000
00000X00 -0000-XX
SCR5 [R/W] SMR5 [R/W] SSR5 [R/W] RDR5 /TDR5
0000E8H B, H, W B, H, W B, H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART5
ESCR5 [R/W] ECCR5 [R/W]
BGR5 [R/W] B, H, W
0000ECH B, H, W B, H, W
-0000000 00000000
00000X00 -0000-XX
SCR6 [R/W] SMR6 [R/W] SSR6 [R/W] RDR6 /TDR6
0000F0H B, H, W B, H, W B, H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART6
ESCR6 [R/W] ECCR6 [R/W]
BGR6 [R/W] B, H, W
0000F4H B, H, W B, H, W
-0000000 00000000
00000X00 -0000-XX
SCR7 [R/W] SMR7 [R/W] SSR7 [R/W] RDR7 /TDR7
0000F8H B, H, W B, H, W B, H, W [R/W] B, H, W
00000000 00000000 00001000 00000000
LIN-UART7
ESCR7 [R/W] ECCR7 [R/W]
BGR7 [R/W] B, H, W
0000FCH B, H, W B, H, W
-0000000 00000000
00000X00 -0000-XX

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 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
TMRLRA1 [R/W] H TMR1 [R] H
000100H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 1
TMRLRB1 [R/W] H TMCSR1 [R/W] B, H,W
000104H
XXXXXXXX XXXXXXXX 00000000 0-000000
TMRLRA2 [R/W] H TMR2 [R] H
000108H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 2
TMRLRB2 [R/W] H TMCSR2 [R/W] B, H,W
00010CH
XXXXXXXX XXXXXXXX 00000000 0-000000
TMRLRA3 [R/W] H TMR3 [R] H
000110H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reload timer 3
TMRLRB3 [R/W] H TMCSR3 [R/W] B, H,W
000114H
XXXXXXXX XXXXXXXX 00000000 0-000000
000118H
to ― ― ― ― Reserved
000140H
GCN13 GCN23
PPG12,13,14,15
000144H [R/W] H ― [R/W] B
control
00110010 00010000 ----0000
GCN14 GCN24
PPG16,17,18,19
000148H [R/W] H ― [R/W] B
control
00110010 00010000 ----0000
GCN15 GCN25
PPG20,21,22,23
00014CH [R/W] H ― [R/W] B
control
00110010 00010000 ----0000
PTMR11 [R] H,W PCSR11 [W] H, W
000150H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG11
PDUT11 [W] H,W PCN11 [R/W] B, H,W
000154H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR12 [R] H,W PCSR12 [W] H,W
000158H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG12
PDUT12 [W] H,W PCN12 [R/W] B, H,W
00015CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR13 [R] H,W PCSR13 [W] H,W
000160H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG13
PDUT13 [W] H,W PCN13 [R/W] B, H,W
000164H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR14 [R] H,W PCSR14 [W] H,W
000168H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG14
PDUT14 [W] H,W PCN14 [R/W] B, H,W
00016CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR15 [R] H,W PCSR15 [W] H,W
000170H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG15
PDUT15 [W] H,W PCN15 [R/W] B, H,W
000174H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR16 [R] H,W PCSR16 [W] H, W
000178H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG16
PDUT16 [W] H,W PCN16 [R/W] B, H,W
00017CH
XXXXXXXX XXXXXXXX 0000000- 000000-0

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MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
PTMR17 [R] H,W PCSR17 [W] H,W
000180H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG17
PDUT17 [W] H,W PCN17 [R/W] B, H,W
000184H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR18 [R] H,W PCSR18 [W] H,W
000188H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG18
PDUT18 [W] H,W PCN18 [R/W] B, H,W
00018CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR19 [R] H,W PCSR19 [W] H,W
000190H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG19
PDUT19 [W] H,W PCN19 [R/W] B, H,W
000194H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR20 [R] H,W PCSR20 [W] H,W
000198H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG20
PDUT20 [W] H,W PCN20 [R/W] B, H,W
00019CH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR21 [R] H,W PCSR21 [W] H, W
0001A0H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG21
PDUT21 [W] H,W PCN21 [R/W] B, H,W
0001A4H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR22 [R] H,W PCSR22 [W] H,W
0001A8H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG22
PDUT22 [W] H,W PCN22 [R/W] B, H,W
0001ACH
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR23 [R] H,W PCSR23 [W] H,W
0001B0H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG23
PDUT23 [W] H,W PCN23 [R/W] B, H,W
0001B4H
XXXXXXXX XXXXXXXX 0000000- 000000-0
0001B8H
to ― ― ― ― Reserved
0001FCH
PWC20 [R/W] H,W PWC10 [R/W] H,W
000200H
------XX XXXXXXXX ------XX XXXXXXXX
PWS20 [R/W] PWS10 [R/W]
PWC0 [R/W] B
000204H ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC21 [R/W] H,W PWC11 [R/W] H,W Stepping motor
000208H
------XX XXXXXXXX ------XX XXXXXXXX controller
PWS21 [R/W] PWS11 [R/W]
PWC1 [R/W] B
00020CH ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC22 [R/W] H,W PWC12 [R/W] H,W
000210H
------XX XXXXXXXX ------XX XXXXXXXX

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 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
PWS22 [R/W] PWS12 [R/W]
PWC2 [R/W] B
000214H ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC23 [R/W] H,W PWC13 [R/W] H,W
000218H
------XX XXXXXXXX ------XX XXXXXXXX
PWS23 [R/W] PWS13 [R/W]
PWC3 [R/W] B
00021CH ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC24 [R/W] H,W PWC14 [R/W] H,W Stepping motor
000220H
------XX XXXXXXXX ------XX XXXXXXXX controller
PWS24 [R/W] PWS14 [R/W]
PWC4 [R/W] B
000224H ― B,H,W B,H,W
-00000--
-0000000 --000000
PWC25 [R/W] H,W PWC15 [R/W] H,W
000228H
------XX XXXXXXXX ------XX XXXXXXXX
PWS25 [R/W] PWS15 [R/W]
PWC5 [R/W] B
00022CH ― B,H,W B,H,W
-00000--
-0000000 --000000
000230H
to ― ― ― ― Reserved
00023CH
CPCLR0 [R/W] W
000240H
11111111 11111111 11111111 11111111
TCDT0 [R/W] W
000244H
00000000 00000000 00000000 00000000 Free-run timer 0
TCCSH0 TCCSL0
000248H [R/W]B, H, W [R/W]B, H, W ―
0-----00 -1-00000
CPCLR1 [R/W] W
00024CH
11111111 11111111 11111111 11111111
TCDT1 [R/W] W
000250H
00000000 00000000 00000000 00000000 Free-run timer 1
TCCSH1 TCCSL1
000254H [R/W]B, H, W [R/W]B, H, W ―
0-----00 -1-00000
000258H ― ― ― ― Reserved
GCN10 [R/W] H GCN20 [R/W] B
00025CH ― PPG0,1,2,3 control
00110010 00010000 ----0000
GCN11 [R/W] H GCN21 [R/W] B
000260H ― PPG4,5,6,7 control
00110010 00010000 ----0000
GCN12 [R/W] H GCN22 [R/W] B
000264H ― PPG8,9,10,11 control
00110010 00010000 ----0000

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MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
PPGDIV [R/W]
000268H ― ― ― B
------00
PTMR0 [R] H,W PCSR0 [W] H,W PPG0
00026CH
11111111 11111111 XXXXXXXX XXXXXXXX
PDUT0 [W] H,W PCN0 [R/W] B, H,W
000270H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR1 [R] H,W PCSR1 [W] H, W
000274H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG1
PDUT1 [W] H,W PCN1 [R/W] B, H,W
000278H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR2 [R] H,W PCSR2 [W] H,W
00027CH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG2
PDUT2 [W] H,W PCN2 [R/W] B, H,W
000280H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR3 [R] H,W PCSR3 [W] H,W
000284H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG3
PDUT3 [W] H,W PCN3 [R/W] B, H,W
000288H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR4 [R] H,W PCSR4 [W] H,W
00028CH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG4
PDUT4 [W] H,W PCN4 [R/W] B, H,W
000290H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR5 [R] H,W PCSR5 [W] H,W
000294H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG5
PDUT5 [W] H,W PCN5 [R/W] B, H,W
000298H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR6 [R] H,W PCSR6 [W] H,W
00029CH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG6
PDUT6 [W] H,W PCN6 [R/W] B, H,W
0002A0H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR7 [R] H,W PCSR7 [W] H,W
0002A4H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG7
PDUT7 [W] H,W PCN7 [R/W] B, H,W
0002A8H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR8 [R] H,W PCSR8 [W] H,W
0002ACH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG8
PDUT8 [W] H,W PCN8 [R/W] B, H,W
0002B0H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR9 [R] H,W PCSR9 [W] H,W
0002B4H
11111111 11111111 XXXXXXXX XXXXXXXX
PPG9
PDUT9 [W] H,W PCN9 [R/W] B, H,W
0002B8H
XXXXXXXX XXXXXXXX 0000000- 000000-0
PTMR10 [R] H,W PCSR10 [W] H,W
0002BCH
11111111 11111111 XXXXXXXX XXXXXXXX
PPG10
PDUT10 [W] H,W PCN10 [R/W] B, H,W
0002C0H
XXXXXXXX XXXXXXXX 0000000- 000000-0

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 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
IPCP0 [R] W
0002C4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP1 [R] W
0002C8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input Capture 0,1
ICFS01 [R/W] LSYNS0 [R/W] ICS01 [R/W]
0002CCH B, H, W ― B, H, W B, H, W
------00 --000000 00000000
IPCP2 [R] W
0002D0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP3 [R] W
0002D4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input Capture 2,3
ICFS23 [R/W] ICS23 [R/W]
0002D8H B, H, W ― ― B, H, W
------00 00000000
IPCP4 [R] W
0002DCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP5 [R] W
0002E0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input Capture 4,5
ICFS45 [R/W] ICS45 [R/W]
0002E4H B, H, W ― ― B, H, W
------00 00000000
OCCP0 [R/W] W
0002E8H
00000000 00000000 00000000 00000000
OCCP1 [R/W] W
0002ECH
00000000 00000000 00000000 00000000 Output compare 0,1
OCFS01 [R/W] OCSH01[R/W] OCSL01[R/W]
0002F0H B, H, W ― B, H, W B, H, W
------11 ---0--00 0000--00
OCCP2 [R/W] W
0002F4H
00000000 00000000 00000000 00000000
OCCP3 [R/W] W
0002F8H
00000000 00000000 00000000 00000000 Output compare 2,3
OCFS23 [R/W] OCSH23[R/W] OCSL23[R/W]
0002FCH B, H, W ― B, H, W B, H, W
------11 ---0--00 0000--00
000300H
to ― ― ― ― Reserved
00030CH

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MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
MPUCR [R/W] H
000310H ― ―
000000-0 ----0100
000314H ― ― ― ―
000318H ―

00031CH ― ― ―
DPVAR [R] W
000320H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DPVSR [R/W] H
000324H ― ―
-------- 00000--0
DEAR [R] W
000328H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DESR [R/W] H
00032CH ― ―
-------- 00000--0
PABR0 [R/W] W
000330H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR0 [R/W] H
000334H ― ―
000000-0 00000--0
PABR1 [R/W] W
000338H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR1 [R/W] H
00033CH ― ― MPU [S]
000000-0 00000--0
(Only the CPU can
PABR2 [R/W] W access this area)
000340H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR2 [R/W] H
000344H ― ―
000000-0 00000--0
PABR3 [R/W] W
000348H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR3 [R/W] H
00034CH ― ―
000000-0 00000--0
PABR4 [R/W] W
000350H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR4 [R/W] H
000354H ― ―
000000-0 00000--0
PABR5 [R/W] W
000358H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR5 [R/W] H
00035CH ― ―
000000-0 00000--0
PABR6 [R/W] W
000360H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR6 [R/W] H
000364H ― ―
000000-0 00000--0
PABR7 [R/W] W
000368H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000

62 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
MPU [S]
PACR7 [R/W] H
00036CH ― ― (Only the CPU can
000000-0 00000--0
access this area)
PABR8 [R/W] W
000370H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR8 [R/W] H
000374H ― ―
000000-0 00000--0
PABR9[R/W] W
000378H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
MPU [S]
PACR9 [R/W] H (Only product
00037CH ― ―
000000-0 00000--0 mounting MPU 12ch
PABR10 [R/W] W or 16ch)
000380H (Only the CPU can
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
access this area)
PACR10 [R/W] H
000384H ― ―
000000-0 00000--0
PABR11 [R/W] ,W
000388H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR11 [R/W] H
00038CH ― ―
000000-0 00000--0
PABR12 [R/W] W
000390H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR12 [R/W] H
000394H ― ―
000000-0 00000--0
PABR13 [R/W] W
000398H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR13 [R/W] H MPU [S]
00039CH ― ― (Only product
000000-0 00000--0
mounting MPU 16ch)
PABR14 [R/W]W (Only the CPU can
0003A0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 access this area)
PACR14 [R/W] H
0003A4H ― ―
000000-0 00000--0
PABR15 [R/W] W
0003A8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR15 [R/W] H
0003ACH ― ―
000000-0 00000--0
0003B0H
to ― ― ― ― Reserved [S]
0003FCH
ICSEL0[R/W] ICSEL1[R/W] ICSEL2[R/W] ICSEL3[R/W]
000400H B, H, W B, H, W B, H, W B, H, W
-----000 -----000 -------0 -------0
ICSEL4[R/W] ICSEL5[R/W] ICSEL6[R/W] ICSEL7[R/W] Generation and clear
000404H B, H, W B, H, W B, H, W B, H, W of DMA transfer
-------0 -------0 -----000 -----000 request
ICSEL8[R/W] ICSEL9[R/W] ICSEL10[R/W] ICSEL11[R/W]
000408H B, H, W B, H, W B, H, W B, H, W
------00 ------00 ------00 ------00

DS705-00010-2v0-E 63

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
ICSEL12[R/W] ICSEL13[R/W] ICSEL14[R/W] ICSEL15[R/W]
00040CH B, H, W B, H, W B, H, W B, H, W
------00 -------0 -------0 --------
ICSEL16[R/W] ICSEL17[R/W] ICSEL18[R/W] ICSEL19[R/W] Generation and clear
000410H B, H, W B, H, W B, H, W B, H, W of DMA transfer
-------- -------- -------- -----000 request
ICSEL20[R/W] ICSEL21[R/W] ICSEL22[R/W]
000414H B, H, W B, H, W B, H, W ―
-----000 ------00 ------00
IRPR0H[R] IRPR0L[R] IRPR1H[R] IRPR1L[R]
000418H B, H, W B, H, W B, H, W B, H, W
00------ 00------ 00------ 00------
IRPR2H[R] IRPR2L[R] IRPR3H[R] IRPR3L[R]
00041CH B, H, W B, H, W B, H, W B, H, W
00------ 00------ 000000-- 000000--
IRPR4H[R] IRPR4L[R] IRPR5H[R] IRPR5L[R]
Interrupt request
000420H B, H, W B, H, W B, H, W B, H, W
batch read register
0000---- 0000---- 0000---- 0-------
IRPR6H[R] IRPR6L[R] IRPR7H[R] IRPR7L[R]
000424H B, H, W B, H, W B, H, W B, H, W
00--0--- 000----- -00----- ------0-
IRPR8H[R] IRPR8L[R] IRPR9H[R] IRPR9L[R]
000428H B, H, W B, H, W B, H, W B, H, W
00------ 00------ 00------ 00------

00042CH ― ― ― ― Reserved

IRPR12H[R] IRPR12L[R] IRPR13H[R] IRPR13L[R]

000430H B, H, W B, H, W B, H, W B, H, W
00------ 00------ 000----- 00000--- Interrupt request
IRPR14H[R] IRPR14L[R] IRPR15H[R] batch read register
000434H B, H, W B, H, W B, H, W ―
00000000 00000000 000-----
000438H,
― ― ― ― Reserved
00043CH
ICR00 [R/W] ICR01 [R/W] ICR02 [R/W] ICR03 [R/W]
000440H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
ICR04 [R/W] ICR05 [R/W] ICR06 [R/W] ICR07 [R/W]
000444H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111 Interrupt controller
ICR08 [R/W] ICR09 [R/W] ICR10 [R/W] ICR11 [R/W] [S]
000448H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
ICR12 [R/W] ICR13 [R/W] ICR14 [R/W] ICR15 [R/W]
00044CH B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111

64 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
ICR16 [R/W] ICR17 [R/W] ICR18 [R/W] ICR19 [R/W]
000450H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
ICR20 [R/W] ICR21 [R/W] ICR22 [R/W] ICR23 [R/W]
000454H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
ICR24 [R/W] ICR25 [R/W] ICR26 [R/W] ICR27 [R/W]
000458H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
ICR28 [R/W] ICR29 [R/W] ICR30 [R/W] ICR31 [R/W]
00045CH B, H, W B, H, W B, H, W B, H, W Interrupt controller
---11111 ---11111 ---11111 ---11111 [S]
ICR32 [R/W] ICR33 [R/W] ICR34 [R/W] ICR35 [R/W]
000460H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
ICR36 [R/W] ICR37 [R/W] ICR38 [R/W] ICR39 [R/W]
000464H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
ICR40 [R/W] ICR41 [R/W] ICR42 [R/W] ICR43 [R/W]
000468H B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
ICR44 [R/W] ICR45 [R/W] ICR46 [R/W] ICR47 [R/W]
00046CH B, H, W B, H, W B, H, W B, H, W
---11111 ---11111 ---11111 ---11111
000470H
to ― ― ― ― Reserved [S]
00047CH
Reset control [S]
Power consumption
RSTRR [R] RSTCR [R/W] STBCR [R/W] control [S]
000480H B, H, W B, H, W B, H, W *3 ―
XXXX--XX 111----0 000---11 * 3:Writing to
STBCR by DMA is
disabled
000484H ― ― ― ― Reserved [S]
DIVR0 [R/W] DIVR1 [R/W] DIVR2 [R/W]
000488H B, H, W B, H, W B, H, W ― Clock control [S]
000----- 0001---- 0011----
00048CH ― ― ― ― Reserved [S]
IORR0[R/W] IORR1[R/W] IORR2[R/W] IORR3[R/W]
000490H B, H, W B, H, W B, H, W B, H, W
-0000000 -0000000 -0000000 -0000000
IORR4[R/W] IORR5[R/W] IORR6[R/W] IORR7[R/W]
DMA transfer request
000494H B, H, W B, H, W B, H, W B, H, W
from a peripheral [S]
-0000000 -0000000 -0000000 -0000000
IORR8[R/W] IORR9[R/W] IORR10[R/W] IORR11[R/W]
000498H B, H, W B, H, W B, H, W B, H, W
-0000000 -0000000 -0000000 -0000000

DS705-00010-2v0-E 65

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
IORR12[R/W] IORR13[R/W] IORR14[R/W] IORR15[R/W]
DMA transfer request
00049CH B, H, W B, H, W B, H, W B, H, W
from a peripheral [S]
-0000000 -0000000 -0000000 -0000000
0004A0H ― ― ― ― Reserved
CANPRE [R/W]
0004A4H B,H,W ― ― ― CAN prescaler
----0000
0004A8H ― ― ― ― Reserved
0004ACH ― ― ― ― Reserved
0004B0H ― ― ― ― Reserved
0004B4H ― ― ― ― Reserved
CUCR0 [R/W] B,H,W CUTD0 [R/W] B,H,W
0004B8H
-------- ---0--00 10000000 00000000
CUTR0 [R] B,H,W
0004BCH
-------- 00000000 00000000 00000000
RTC/WDT1
0004C0H ― ― ― ― calibration
(Calibration)
CUCR1 [R/W] B,H,W CUTD1[R/W] B,H,W
0004C4H
-------- ---0--00 11000011 01010000
CUTR1 [R] B,H,W
0004C8H
-------- 00000000 00000000 00000000
CRTR [R/W]
RC trimming
0004CCH B,H,W ― ― ―
setting register
01111111
0004D0H
to ― ― ― ― Reserved
0004DCH
0004E0H
to ― ― ― ― Reserved
00050CH
CSELR [R/W] CMONR [R] MTMCR [R/W] STMCR [R/W]
000510H B,H,W B,H,W B,H,W B,H,W
001---00 001---00 00001111 0000-111
Clock control [S]
CSTBR [R/W] PTMCR [R/W]
PLLCR [R/W] B,H,W
000514H B,H,W B,H,W
-------- 11110000
-0000000 00------
CPUAR [R/W]
000518H ― ― B,H,W ― Reset [S]
0----XXX
00051CH ― ― ― ― Reserved [S]
CCPSSELR CCPSDIVR
000520H [R/W] B,H,W ― ― [R/W] B,H,W
-------0 -000-000
Clock control 2
CCPLLFBR CCSSFBR0 CCSSFBR1
000524H ― [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W
-0000000 --000000 ---00000

66 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
CCSSCCR0 CCSSCCR1
000528H ― [R/W] B,H,W [R/W] H,W
----0000 000----- --------
CCCGRCR0 CCCGRCR1 CCCGRCR2
00052CH ― [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W
00----00 00000000 00000000
CCRTSELR CCPMUCR0 CCPMUCR1
Clock control 2
000530H [R/W] B,H,W ― [R/W] B,H,W [R/W] B,H,W
0------0 0-----00 0--00000

000534H ― ― ― ―

000538H ― ― ― ―

00053CH ― ― ― ―
000540H
to ― ― ― ― Reserved
00054CH
EIRR0 ENIR0 ELVR0
External interrupt
000550H [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W
(INT0 to INT7)
XXXXXXXX 00000000 00000000 00000000
EIRR1 ENIR1 ELVR1
External interrupt
000554H [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W
(INT8 to INT15)
XXXXXXXX 00000000 00000000 00000000
000558H ― ― ― ― Reserved
WTDR[R/W] H
00055CH ― ―
00000000 00000000
WTCRH WTCRM WTCRL
000560H ― [R/W] B [R/W] B,H [R/W] B,H
------00 00000000 ----00-0
WTBRH WTBRM WTBRL Real-time clock
000564H ― [R/W] B [R/W] B [R/W] B
--XXXXXX XXXXXXXX XXXXXXXX
WTHR WTMR WTSR
000568H [R/W] B,H [R/W] B,H [R/W] B ―
---00000 --000000 --000000
Clock supervisor
*4:An initial value is
CSVCR
different by part
[R/W] B
00056CH ― ― ― number.For details,
-001110-
refer to the CSVCR
-001010-*4
register in chapter
“Clock Supervisor”
000570H
to ― ― ― ― Reserved
00057CH

DS705-00010-2v0-E 67

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
REGSEL
000580H [R/W] B,H,W ― ― ― Regulator control
0110011-
LVD5R LVD5F LVD
000584H [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W ―
-------1 0-100--1 01000--0
Low-power detection
GLVD5R[R/W] GLVD5F[R/W] GLVD[R/W]
000588H B,H,W B,H,W B,H,W ―
0-01-0-X 0-0100-X 010000-X
00058CH ― ― ― ― Reserved
PMUSTR PMUCTLR PWRTMCTL
000590H [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W ―
0-----1X 0-00---- -----011
PMUINTF0 PMUINTF1 PMUINTF2
000594H [R/W] B,H,W [R/W] B,H,W [R/W] B,H,W ―
00000000 00000000 0000---- PMU
GSTR[R] GCTLR[R/W]
000598H B,H,W B,H,W ― ―
0------- 0000-111
00059CH ― ― ― ―
0005A0H
to ― ― ― ― Reserved
0005FCH
000600H
to ― ― ― ― Reserved[S]
00060CH
000610H
to ― ― ― ― Reserved[S]
00063CH
000640H
to ― ― ― ― Reserved[S]
00064CH
000650H
to ― ― ― ― Reserved[S]
00067CH
000680H
to ― ― ― ― Reserved[S]
00068CH
000690H
to ― ― ― ― Reserved[S]
0006BCH
0006C0H
to ― ― ― ― Reserved[S]
0006CCH
0006D0H
to ― ― ― ― Reserved
0006F0H

68 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
0006F4 H ― ― ― ― Reserved
0006F8H
to ― ― ― ― Reserved
00070CH
BPCCRA[R/W] BPCCRB[R/W] BPCCRC[R/W]
000710H B B B ―
00000000 00000000 00000000
BPCTRA[R/W] W
000714H Bus performance
00000000 00000000 00000000 00000000
counter
BPCTRB[R/W] W
000718H
00000000 00000000 00000000 00000000
BPCTRC[R/W] W
00071CH
00000000 00000000 00000000 00000000
000720H
to ― ― ― ― Reserved
0007F8H
BMODR[R]
0007FCH B, H, W ― ― ― Operation mode
XXXXXXXX
000800H
to ― ― ― ― Reserved [S]
00083CH
FCTLR[R/W] H FSTR[R/W] B Flash memory
000840H ―
-0--1000 0--0---- -----001 register [S]
000844H
to ― ― ― ― Reserved [S]
000854H
WREN[R/W] H
000858H ― ― Wild register [S]
00000000 00000000
00085CH
to ― ― ― ― Reserved [S]
00087CH
WRAR00[R/W] W
000880H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR00[R/W] W
000884H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01[R/W] W
000888H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR01[R/W] W
00088CH Wild register [S]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02[R/W] W
000890H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR02[R/W] W
000894H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03[R/W] W
000898H
-------- --XXXXXX XXXXXXXX XXXXXX--

DS705-00010-2v0-E 69

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
WRDR03[R/W] W
00089CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04[R/W] W
0008A0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR04[R/W] W
0008A4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05[R/W] W
0008A8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR05[R/W] W
0008ACH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06[R/W] W
0008B0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR06[R/W] W
0008B4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07[R/W] W
0008B8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR07[R/W] W
0008BCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08[R/W] W
0008C0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR08[R/W] W
0008C4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09[R/W] W
0008C8H Wild register [S]
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR09[R/W] W
0008CCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR10[R/W] W
0008D0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR10[R/W] W
0008D4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11[R/W] W
0008D8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR11[R/W] W
0008DCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12[R/W] W
0008E0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR12[R/W] W
0008E4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR13[R/W] W
0008E8H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR13[R/W] W
0008ECH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14[R/W] W
0008F0H
-------- --XXXXXX XXXXXXXX XXXXXX--
WRDR14[R/W] W
0008F4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

70 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
WRAR15[R/W] W
0008F8H
-------- --XXXXXX XXXXXXXX XXXXXX--
Wild register [S]
WRDR15[R/W] W
0008FCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000900H
to ― ― ― ― Reserved
000BF8H
UER [W] B,H,W
000BFCH ― ― OCDU
-------- -------X
DCCR0[R/W] W
000C00H
0----000 --00--00 00000000 0-000000
DCSR0[R/W] H DTCR0[R/W] H
000C04H
0------- -----000 00000000 00000000
DSAR0[R/W] W
000C08H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0[R/W] W
000C0CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR1[R/W] W
000C10H
0----000 --00--00 00000000 0-000000
DCSR1[R/W] H DTCR1[R/W] H
000C14H
0------- -----000 00000000 00000000
DSAR1[R/W] W
000C18H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1[R/W] W
000C1CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2[R/W] W
000C20H
0----000 --00--00 00000000 0-000000
DCSR2[R/W] H DTCR2[R/W] H
000C24H DMA controller [S]
0------- -----000 00000000 00000000
DSAR2[R/W] W
000C28H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2[R/W] W
000C2CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3[R/W] W
000C30H
0----000 --00--00 00000000 0-000000
DCSR3[R/W] H DTCR3[R/W] H
000C34H
0------- -----000 00000000 00000000
DSAR3[R/W] W
000C38H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3[R/W] W
000C3CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4[R/W] W
000C40H
0----000 --00--00 00000000 0-000000
DCSR4[R/W] H DTCR4[R/W] H
000C44H
0------- -----000 00000000 00000000
DSAR4[R/W] W
000C48H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DS705-00010-2v0-E 71

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
DDAR4[R/W] W
000C4CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5[R/W] W
000C50H
0----000 --00--00 00000000 0-000000
DCSR5[R/W] H DTCR5[R/W] H
000C54H
0------- -----000 00000000 00000000
DSAR5[R/W] W
000C58H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5[R/W] W
000C5CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR6[R/W] W
000C60H
0----000 --00--00 00000000 0-000000
DCSR6[R/W] H DTCR6[R/W] H
000C64H
0------- -----000 00000000 00000000
DSAR6[R/W] W
000C68H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6[R/W] W
000C6CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7[R/W] W
000C70H
0----000 --00--00 00000000 0-000000
DCSR7[R/W] H DTCR7[R/W] H
000C74H
0------- -----000 00000000 00000000
DSAR7[R/W] W
000C78H DMA controller [S]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7[R/W] W
000C7CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR8[R/W] W
000C80H
0----000 --00--00 00000000 0-000000
DCSR8[R/W] H DTCR8[R/W] H
000C84H
0------- -----000 00000000 00000000
DSAR8[R/W] W
000C88H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR8[R/W] W
000C8CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR9[R/W] W
000C90H
0----000 --00--00 00000000 0-000000
DCSR9[R/W] H DTCR9[R/W] H
000C94H
0------- -----000 00000000 00000000
DSAR9[R/W] W
000C98H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR9[R/W] W
000C9CH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR10[R/W] W
000CA0H
0----000 --00--00 00000000 0-000000
DCSR10[R/W] H DTCR10[R/W] H
000CA4H
0------- -----000 00000000 00000000

72 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
DSAR10[R/W] W
000CA8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR10[R/W] W
000CACH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR11[R/W] W
000CB0H
0----000 --00--00 00000000 0-000000
DCSR11[R/W] H DTCR11[R/W] H
000CB4H
0------- -----000 00000000 00000000
DSAR11[R/W] W
000CB8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR11[R/W] W
000CBCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR12[R/W] W
000CC0H
0----000 --00--00 00000000 0-000000
DCSR12[R/W] H DTCR12[R/W] H
000CC4H
0------- -----000 00000000 00000000
DSAR12[R/W] W
000CC8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR12[R/W] W
000CCCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR13[R/W] W
000CD0H
0----000 --00--00 00000000 0-000000
DMA controller [S]
DCSR13[R/W] H DTCR13[R/W] H
000CD4H
0------- -----000 00000000 00000000
DSAR13[R/W] W
000CD8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR13[R/W] W
000CDCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR14[R/W] W
000CE0H
0----000 --00--00 00000000 0-000000
DCSR14[R/W] H DTCR14[R/W] H
000CE4H
0------- -----000 00000000 00000000
DSAR14[R/W] W
000CE8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR14[R/W] W
000CECH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR15[R/W] W
000CF0H
0----000 --00--00 00000000 0-000000
DCSR15[R/W] H DTCR15[R/W] H
000CF4H
0------- -----000 00000000 00000000
DSAR15[R/W] W
000CF8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR15[R/W] W
000CFCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DS705-00010-2v0-E 73

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
000D00H
to ― ― ― ― Reserved [S]
000DF0H
DNMIR[R/W] B DILVR[R/W] B
000DF4H ― ―
0------0 ---11111
DMA controller [S]
DMACR[R/W] W
000DF8H
0------- -------- 0------- --------
000DFCH ― ― ― ― Reserved [S]
DDR00[R/W] DDR01[R/W] DDR02[R/W] DDR03[R/W]
000E00H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
DDR04[R/W] DDR05[R/W] DDR06[R/W] DDR07[R/W]
000E04H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
DDR08[R/W] DDR09[R/W] DDR10[R/W] DDR11[R/W]
000E08H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000 Data direction
DDR12[R/W] DDR13[R/W] register
000E0CH B,H,W B,H,W ― ―
00000000 00-00000
DDRA[R/W] DDRB[R/W] DDRC[R/W] DDRD[R/W]
000E10H B,H,W B,H,W B,H,W B,H,W
000000-- 000000-- 000000-- 000000--
DDRE[R/W] DDRF[R/W] DDRG[R/W] DDRH[R/W]
000E14H B,H,W B,H,W B,H,W B,H,W
000000-- 000000-- 00000000 ----0---
000E18H
to ― ― ― ― Reserved
000E1CH
PFR00[R/W] PFR01[R/W] PFR02[R/W] PFR03[R/W]
000E20H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000
PFR04[R/W] PFR05[R/W] PFR06[R/W] PFR07[R/W]
000E24H B,H,W B,H,W B,H,W B,H,W
00000000 -0000000 00000000 00000000
PFR08[R/W] PFR09[R/W] PFR10[R/W] PFR11[R/W]
000E28H B,H,W B,H,W B,H,W B,H,W
00000000 0-000000 00000000 00000000
Port function register
PFR12[R/W] PFR13[R/W]
000E2CH B,H,W B,H,W ― ―
0-000000 ---00000
PFRA[R/W] PFRB[R/W] PFRC[R/W] PFRD[R/W]
000E30H B,H,W B,H,W B,H,W B,H,W
-------- -------- -------- 000000--
PFRE[R/W] PFRF[R/W] PFRG[R/W] PFRH[R/W]
000E34H B,H,W B,H,W B,H,W B,H,W
000000-- 000000-- 00000--- --------

74 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
000E38H
to ― ― ― ― Reserved
000E3CH
PDDR00[R] PDDR01[R] PDDR02[R] PDDR03[R]
000E40H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PDDR04[R] PDDR05[R] PDDR06[R] PDDR07[R]
000E44H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PDDR08[R] PDDR09[R] PDDR10[R] PDDR11[R]
000E48H B,H,W B,H,W B,H,W B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input data direct read
PDDR12[R] PDDR13[R] register
000E4CH B,H,W B,H,W ― ―
XXXXXXXX XX-XXXXX
PDDRA[R] PDDRB[R] PDDRC[R] PDDRD[R]
000E50H B,H,W B,H,W B,H,W B,H,W
XXXXXX-- XXXXXX-- XXXXXX-- XXXXXX--
PDDRE[R] PDDRF[R] PDDRG[R] PDDRH[R]
000E54H B,H,W B,H,W B,H,W B,H,W
XXXXXX-- XXXXXX-- XXXXXXXX ----X---
000E58H
to ― ― ― ― Reserved
000E5CH
EPFR00[R/W] EPFR01[R/W] EPFR02[R/W] EPFR03[R/W]
000E60H B,H,W B,H,W B,H,W B,H,W
00000000 ----0000 ---00000 ---00000
EPFR04[R/W] EPFR05[R/W] EPFR06[R/W] EPFR07[R/W]
000E64H B,H,W B,H,W B,H,W B,H,W
---00000 ---00000 ---00000 ---00000
EPFR08[R/W] EPFR09[R/W] EPFR10[R/W] EPFR11[R/W]
000E68H B,H,W B,H,W B,H,W B,H,W
---00000 ---00000 -0000000 --000000
EPFR12[R/W] EPFR13[R/W] EPFR14[R/W] EPFR15[R/W]
000E6CH B,H,W B,H,W B,H,W B,H,W
--000000 --000000 --000000 -0000000 Extended port
EPFR16[R/W] EPFR17[R/W] EPFR18[R/W] EPFR19[R/W] function register
000E70H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 10000000 11111111
EPFR20[R/W] EPFR21[R/W] EPFR22[R/W] EPFR23[R/W]
000E74H B,H,W B,H,W B,H,W B,H,W
-1111111 00000000 00000000 00000000
EPFR24[R/W] EPFR25[R/W] EPFR26[R/W] EPFR27[R/W]
000E78H B,H,W B,H,W B,H,W B,H,W
-----000 -----000 ----0000 ---00000
EPFR28[R/W] EPFR29[R/W] EPFR30[R/W] EPFR31[R/W]
000E7CH B,H,W B,H,W B,H,W B,H,W
------00 00000000 00000000 00000000

DS705-00010-2v0-E 75

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
EPFR32[R/W] EPFR33[R/W] EPFR34[R/W] EPFR35[R/W]
Extended port
000E80H B,H,W B,H,W B,H,W B,H,W
function register
00000000 ---00000 ---00000 ---00000
EPFR36[R/W] EPFR37[R/W] EPFR38[R/W] EPFR39[R/W]
000E84H B,H,W B,H,W B,H,W B,H,W
---00000 00000000 ---00000 00000000
EPFR40[R/W] EPFR41[R/W] EPFR42[R/W] EPFR43[R/W]
000E88H B,H,W B,H,W B,H,W B,H,W
--000000 -----000 ------00 00000000
EPFR44[R/W] EPFR45[R/W] EPFR46[R/W] EPFR47[R/W]
Extended port
000E8CH B,H,W B,H,W B,H,W B,H,W
function register
00000000 00000000 --000000 -------0
EPFR48[R/W] EPFR49[R/W] EPFR50[R/W] EPFR51[R/W]
000E90H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 ---00000
EPFR52[R/W] EPFR53[R/W] EPFR54[R/W] EPFR55[R/W]
000E94H B,H,W B,H,W B,H,W B,H,W
-----000 ---00000 ----0000 ------01
000E98H
to ― ― ― ― Reserved
000E9CH
PPCR00[R/W] PPCR01[R/W] PPCR02[R/W] PPCR03[R/W]
000EA0H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111
PPCR04[R/W] PPCR05[R/W] PPCR06[R/W] PPCR07[R/W]
000EA4H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111
PPCR08[R/W] PPCR09[R/W] PPCR10[R/W] PPCR11[R/W]
000EA8H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111 Port pull-up/down
PPCR12[R/W] PPCR13[R/W] control register
000EACH B,H,W B,H,W ― ―
11111111 11-11111
PPCRA[R/W] PPCRB[R/W] PPCRC[R/W] PPCRD[R/W]
000EB0H B,H,W B,H,W B,H,W B,H,W
111111-- 111111-- 111111-- 111111--
PPCRE[R/W] PPCRF[R/W] PPCRG[R/W] PPCRH[R/W]
000EB4H B,H,W B,H,W B,H,W B,H,W
111111-- 111111-- 11111111 ----1---
000EB8H
to ― ― ― ― Reserved
000EBCH
PPER00[R/W] PPER01[R/W] PPER02[R/W] PPER03[R/W]
000EC0H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000 Port pull-up/down
PPER04[R/W] PPER05[R/W] PPER06[R/W] PPER07[R/W] enable register
000EC4H B,H,W B,H,W B,H,W B,H,W
00000000 00000000 00000000 00000000

76 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
PPER08[R/W] PPER09[R/W] PPER10[R/W] PPER11[R/W]
Port pull-up/down
000EC8H B,H,W B,H,W B,H,W B,H,W
enable register
00000000 00000000 00000000 00000000
PPER12[R/W] PPER13[R/W]
000ECCH B,H,W B,H,W ― ―
00000000 00-00000
PPERA[R/W] PPERB[R/W] PPERC[R/W] PPERD[R/W]
Port pull-up/down
000ED0H B,H,W B,H,W B,H,W B,H,W
enable register
000000-- 000000-- 000000-- 000000--
PPERE[R/W] PPERF[R/W] PPERG[R/W] PPERH[R/W]
000ED4H B,H,W B,H,W B,H,W B,H,W
000000-- 000000-- 00000000 ----0---
000ED8H
to ― ― ― ― Reserved
000EDCH
PILR00[R/W] PILR01[R/W] PILR02[R/W] PILR03[R/W]
000EE0H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111
PILR04[R/W] PILR05[R/W] PILR06[R/W] PILR07[R/W]
000EE4H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111
PILR08[R/W] PILR09[R/W] PILR10[R/W] PILR11[R/W]
000EE8H B,H,W B,H,W B,H,W B,H,W
11111111 11111111 11111111 11111111 Port input level
PILR12[R/W] PILR13[R/W] selection register
000EECH B,H,W B,H,W ― ―
11111111 11-11111
PILRA[R/W] PILRB[R/W] PILRC[R/W] PILRD[R/W]
000EF0H B,H,W B,H,W B,H,W B,H,W
111111-- 111111-- 111111-- 111111--
PILRE[R/W] PILRF[R/W] PILRG[R/W] PILRH[R/W]
000EF4H B,H,W B,H,W B,H,W B,H,W
111111-- 111111-- 11111111 ----1---
000EF8H
to ― ― ― ― Reserved
000EFCH
000F00H ― ― ― ―
EPILR06[R/W] EPILR07[R/W]
000F04H ― ― B,H,W B,H,W
00000000 00000000
EPILR08[R/W] EPILR09[R/W] EPILR10[R/W] EPILR11[R/W] Extended Port input
000F08H B,H,W B,H,W B,H,W B,H,W level selection
00000000 00000000 00000000 00000000 register
EPILR12[R/W] EPILR13[R/W]
000F0CH B,H,W B,H,W ― ―
00000000 00-00000
000F10H ― ― ― ―

DS705-00010-2v0-E 77

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
Extended Port input
000F14H ― ― ― ― level selection
register
000F18H
to ― ― ― ― Reserved
000F1CH
000F20H ― ― ― ―
PODR06[R/W] PODR07[R/W]
000F24H ― ― B,H,W B,H,W
00000000 00000000
PODR08[R/W] PODR09[R/W] PODR10[R/W] PODR11[R/W]
000F28H B,H,W B,H,W B,H,W B,H,W
Port output drive
00000000 00000000 00000000 00000000 register
PODR12[R/W] PODR13[R/W]
000F2CH B,H,W B,H,W ― ―
00000000 00-00000
000F30H ― ― ― ―

000F34H ― ― ― ―
EPODR06[R/W] EPODR07[R/W] EPODR08[R/W]
000F38H B,H,W B,H,W B,H,W ―
00000000 00000000 00000000 Extended Port output
EPODRGD EPODRGF drive register
000F3CH [R/W]B,H,W [R/W]B,H,W ― ―
----1010 --101010
PORTEN [R/W]
Port input enable
000F40H B,H,W ― ― ―
register
-------0
000F44H
to ― ― ― ― Reserved
000F4CH
GPLLCR[R/W] PTIMCR[R/W] PEDIVCR[R/W]
000F50H ― B,H,W B,H,W B,H,W
0------0 ----1111 -000-000
PDIVCR[R/W] SDIVCR0[R/W] SDIVCR1[R/W]
000F54H ― B,H,W B,H,W B,H,W
-0000000 --000000 ---00000
SSSCR0[R/W] SSSCR1[R/W]
000F58H ― B,H,W H,W GDC control register
----0000 000----- --------
PGRCR0[R/W] PGRCR1[R/W] PGRCR2[R/W]
000F5CH ― B,H,W B,H,W B,H,W
00----00 00000000 00000000
SGRCR0[R/W] SGRCR1[R/W] SGRCR2[R/W]
000F60H ― B,H,W B,H,W B,H,W
00----00 00000000 00000000

78 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
GDCTRGR GDCSWPR
GDCCR[R/W]
[R/W] [R/W]
000F64H ― B,H,W GDC control register
B,H,W B,H,W
--000001
0000--00 ---00101
000F68H
to ― ― ― ― Reserved
000F9CH
CPCLR2 [R/W] W
000FA0H
11111111 11111111 11111111 11111111
TCDT2 [R/W] W Dedicated LSYN
000FA4H
00000000 00000000 00000000 00000000 input capture
TCCSH2 [R/W] TCCSL2 [R/W] free-run timer 2
000FA8H B, H, W B, H, W ―
0-----00 -1-00000
CPCLR3 [R/W] W
000FACH
11111111 11111111 11111111 11111111
TCDT3 [R/W] W Dedicated LSYN
000FB0H
00000000 00000000 00000000 00000000 input capture
TCCSH3 [R/W] TCCSL3 [R/W] free-run timer 3
000FB4H B, H, W B, H, W ―
0-----00 -1-00000
000FB8H
to ― ― ― ― Reserved
000FCCH
IPCP6 [R] W
000FD0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP7 [R] W
000FD4H Dedicated LSYN
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
input capture 6,7
ICFS67 [R/W] LSYNS1 [R/W] ICS67 [R/W]
000FD8H B, H, W ― B,H,W B, H, W
------00 ------00 00000000
000FDCH
to ― ― ― ― Reserved
000FFCH
SACR [R/W] PICD [R/W] Synchronous/asynchr
001000H B,H,W B,H,W ― ― onous switching
-------0 ----0011 control
001004H
to ― ― ― ― Reserved
00103CH
SGDER0[R/W]
SGCR0[R/W] B,H,W
001040H ― B,H,W
-0000-0- 000--000
00000000
SGFR0[R/W] SGNR0[R/W]
SGAR0[R/W] B,H,W
001044H B,H,W B,H,W Sound generator 0
00000000 00000000
00000000 00000000
SGTCR0[R/W] SGIDR0[R/W]
SGPCR0[R/W] B,H,W
001048H B,H,W B,H,W
00000000 11111111
00000000 00000000

DS705-00010-2v0-E 79

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
SGDMAR0[W] B,H,W
00104CH Sound generator 0
00000000 00000000 00000000 00000000
001050H
to ― ― ― ― Reserved
00105CH
SGDER1[R/W]
SGCR1[R/W] B,H,W
001060H ― B,H,W
-0000-0- 000--000
00000000
SGFR1[R/W] SGNR1[R/W]
SGAR1[R/W] B,H,W
001064H B,H,W B,H,W
00000000 00000000
00000000 00000000 Sound generator 1
SGTCR1[R/W] SGIDR1[R/W]
SGPCR1[R/W] B,H,W
001068H B,H,W B,H,W
00000000 11111111
00000000 00000000
SGDMAR1[W] B,H,W
00106CH
00000000 00000000 00000000 00000000
001070H
to ― ― ― ― Reserved
00107CH
SGDER2[R/W]
SGCR2[R/W] B,H,W
001080H ― B,H,W
-0000-0- 000--000
00000000
SGFR2[R/W] SGNR2[R/W]
SGAR2[R/W] B,H,W
001084H B,H,W B,H,W
00000000 00000000
00000000 00000000 Sound generator 2
SGTCR2[R/W] SGIDR2[R/W]
SGPCR2[R/W] B,H,W
001088H B,H,W B,H,W
00000000 11111111
00000000 00000000
SGDMAR2[W] B,H,W
00108CH
00000000 00000000 00000000 00000000
001090H
to ― ― ― ― Reserved
00109CH
SGDER3[R/W]
SGCR3[R/W] B,H,W
0010A0H ― B,H,W
-0000-0- 000—000
00000000
SGFR3[R/W] SGNR3[R/W]
SGAR3[R/W] B,H,W
0010A4H B,H,W B,H,W
00000000 00000000
00000000 00000000 Sound generator 3
SGTCR3[R/W] SGIDR3[R/W]
SGPCR3[R/W] B,H,W
0010A8H B,H,W B,H,W
00000000 11111111
00000000 00000000
SGDMAR3[W] B,H,W
0010ACH
00000000 00000000 00000000 00000000
0010B0H
to ― ― ― ― Reserved
0010BCH

80 DS705-00010-2v0-E

FUJITSU SEMICONDUCTOR CONFIDENTIAL

 MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
SGDER4[R/W]
SGCR4[R/W] B,H,W
0010C0H ― B,H,W
-0000-0- 000--000
00000000
SGFR4[R/W] SGNR4[R/W]
SGAR4[R/W] B,H,W
0010C4H B,H,W B,H,W
00000000 00000000
00000000 00000000 Sound generator 4
SGTCR4[R/W] SGIDR4[R/W]
SGPCR4[R/W] B,H,W
0010C8H B,H,W B,H,W
00000000 11111111
00000000 00000000
SGDMAR4[W] B,H,W
0010CCH
00000000 00000000 00000000 00000000
0010D0H
to ― ― ― ― Reserved
00112CH
CRCCR[R/W]
001130H ― ― ― B,H,W
-0000000
CRCINIT[R/W] B,H,W
001134H CRC arithmetic
1111111 1111111 1111111 1111111
operation
CRCIN[R/W] B,H,W
001138H
00000000 00000000 00000000 00000000
CRCR[R] B,H,W
00113CH
1111111 1111111 1111111 1111111
001140H
to ― ― ― ― Reserved
0013FCH
001400H
to ― ― ― ― Reserved (3KB)
001FFCH
CTRLR0 [R/W] B,H,W STATR0[R/W] B,H,W
002000H
-------- 000-0001 -------- 00000000
ERRCNT0
BTR0[R/W] B,H,W
002004H [R] B,H,W
-0100011 00000001
00000000 00000000
INTR0
TESTR0[R/W] B,H,W
002008H [R] B,H,W
-------- X00000--
00000000 00000000
BRPER0
00200CH [R/W] B,H,W ― CAN0
-------- ----0000 (64msg)
IF1CREQ0 IF1CMSK0
002010H [R/W] B,H,W [R/W] B,H,W
0------- 00000001 -------- 00000000
IF1MSK20 IF1MSK10
002014H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF1ARB20 IF1ARB10
002018H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000

DS705-00010-2v0-E 81

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB91590 Series

Address offset value / Register name

Address Block
+0 +1 +2 +3
IF1MCTR0
00201CH [R/W] B,H,W ―
00000000 0---0000
IF1DTA10
IF1DTA20[R/W] B,H,W
002020H [R/W] B,H,W
00000000 00000000
00000000 00000000
IF1DTB10 IF1DTB20
002024H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002028H,
Reserved
00202CH
002030H,
Reserved (IF1 data mirror)
002034H
002038H,
Reserved
00203CH
IF2CREQ0 IF2CMSK0
002040H [R/W] B,H,W [R/W] B,H,W
0------- 00000001 -------- 00000000
IF2MSK20 IF2MSK10
002044H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF2ARB20 IF2ARB10
002048H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000 CAN0
IF2MCTR0 (64msg)
00204CH [R/W] B,H,W ―
00000000 0---0000
IF2DTA10 IF2DTA20
002050H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF2DTB10 IF2DTB20
002054H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002058H,
Reserved
00205CH
002060H,
Reserved (IF2 data mirror)
002064H
002068H
to Reserved
00207CH
TREQR20 TREQR10
002080H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
TREQR40 TREQR30
002084H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000

002088H ― ―

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Address offset value / Register name

Address Block
+0 +1 +2 +3
00208CH ― ―

NEWDT20 NEWDT10
002090H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
NEWDT40 NEWDT30
002094H [R] B,H,W [R]B,H,W
00000000 00000000 00000000 00000000

002098H ― ―

00209CH ― ―

INTPND20 INTPND10
0020A0H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
INTPND40 INTPND30
CAN0
0020A4H [R] B,H,W [R] B,H,W
(64msg)
00000000 00000000 00000000 00000000

0020A8 H ― ―

0020ACH ― ―

MSGVAL20 MSGVAL10
0020B0H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000
MSGVAL40 MSGVAL30
0020B4H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000

0020B8H ― ―

0020BCH ― ―

0020C0H
to Reserved
0020FCH
CTRLR1
STATR1[R/W] B,H,W
002100H [R/W] B,H,W
-------- 00000000
-------- 000-0001
ERRCNT1
BTR1[R/W] B,H,W
002104H [R] B,H,W
-0100011 00000001
00000000 00000000
INTR1
TESTR1[R/W] B,H,W CAN1
002108H [R] B,H,W
-------- X00000-- (32msg)
00000000 00000000
BRPER1
00210CH [R/W] B,H,W ―
-------- ----0000
IF1CREQ1 IF1CMSK1
002110H [R/W] B,H,W [R/W] B,H,W
0------- 00000001 -------- 00000000

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Address offset value / Register name

Address Block
+0 +1 +2 +3
IF1MSK21 IF1MSK11
002114H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF1ARB21 IF1ARB11
002118H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF1MCTR1
00211CH [R/W] B,H,W ―
00000000 0---0000
IF1DTA11 IF1DTA21
002120H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF1DTB11 IF1DTB21
002124H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002128H,
Reserved
00212CH
002130H,
Reserved (IF1 data mirror)
002134H
002138H,
Reserved
00213CH
IF2CREQ1 IF2CMSK1
002140H [R/W] B,H,W [R/W] B,H,W
0------- 00000001 -------- 00000000
CAN1
IF2MSK21 IF2MSK11 (32msg)
002144H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF2ARB21 IF2ARB11
002148H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF2MCTR1
00214CH [R/W] B,H,W ―
00000000 0---0000
IF2DTA11 IF2DTA21
002150H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF2DTB11 IF2DTB21
002154H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002158H,
Reserved
00215CH
002160H,
Reserved (IF2 data mirror)
002164H
002168H
to Reserved
00217CH
TREQR21 TREQR11
002180H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000

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Address offset value / Register name

Address Block
+0 +1 +2 +3
002184H ― ―

002188H ― ―

00218CH ― ―

NEWDT21 NEWDT11
002190H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000

002194H ― ―

002198H ― ―

00219CH ― ―

INTPND21 INTPND11
0021A0H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000 CAN1
(32msg)
0021A4H ― ―

0021A8H ― ―

0021ACH ― ―

MSGVAL21 MSGVAL11
0021B0H [R] B,H,W [R] B,H,W
00000000 00000000 00000000 00000000

0021B4H ― ―

0021B8H ― ―

0021BCH ― ―

0021C0H
to Reserved
0021FCH
CTRLR2
STATR2[R/W] B,H,W
002200H [R/W] B,H,W
-------- 00000000
-------- 000-0001
ERRCNT2[R] B,H,W BTR2[R/W] B,H,W
002204H
00000000 00000000 -0100011 00000001
INTR2[R] B,H,W TESTR2[R/W] B,H,W CAN2
002208H
00000000 00000000 -------- X00000-- (32msg)
BRPER2
00220CH [R/W] B,H,W ―
-------- ----0000
IF1CREQ2[R/W] B,H,W IF1CMSK2[R/W] B,H,W
002210H
0------- 00000001 -------- 00000000

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Address offset value / Register name

Address Block
+0 +1 +2 +3
IF1MSK22 IF1MSK12
002214H [R/W] B,H,W [R/W] B,H,W
11-11111 11111111 11111111 11111111
IF1ARB22 IF1ARB12
002218H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF1MCTR2[R/W] B,H,W
00221CH ―
00000000 0---0000
IF1DTA12 IF1DTA22
002220H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
IF1DTB12 IF1DTB22
002224H [R/W] B,H,W [R/W] B,H,W
00000000 00000000 00000000 00000000
002228 H,
Reserved
00222CH
002230 H,
Reserved (IF1 data mirror)
002234H
002238H,
Reserved
00223CH
IF2CREQ2[R/W] B,H,W IF2CMSK2[R/W] B,H,W
002240H
0------- 00000001 -------- 00000000
IF2MSK22
IF2MSK12[R/W] B,H,W
002244H [R/W] B,H,W CAN2
11111111 11111111
11-11111 11111111 (32msg)
IF2ARB22[R/W] B,H,W IF2ARB12[R/W] B,H,W
002248H
00000000 00000000 00000000 00000000
IF2MCTR2[R/W] B,H,W
00224CH ―
00000000 0---0000
IF2DTA12[R/W] B,H,W IF2DTA22[R/W] B,H,W
002250H
00000000 00000000 00000000 00000000
IF2DTB12[R/W] B,H,W IF2DTB22[R/W] B,H,W
002254H
00000000 00000000 00000000 00000000
002258H,
Reserved
00225CH
002260H,
Reserved (IF2 data mirror)
002264H
002268H
to Reserved
00227CH
TREQR22[R] B,H,W TREQR12[R] B,H,W
002280H
00000000 00000000 00000000 00000000

002284H ― ―

002288H ― ―

00228CH ― ―

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Address offset value / Register name

Address Block
+0 +1 +2 +3
NEWDT22[R] B,H,W NEWDT12[R] B,H,W
002290 H
00000000 00000000 00000000 00000000

002294H ― ―

002298H ― ―

00229CH ― ―

INTPND22[R] B,H,W INTPND12[R] B,H,W

0022A0H
00000000 00000000 00000000 00000000

0022A4H ― ―
CAN2
0022A8H ― ― (32msg)

0022ACH ― ―

MSGVAL22[R] B,H,W MSGVAL12[R] B,H,W

0022B0H
00000000 00000000 00000000 00000000

0022B4H ― ―

0022B8H ― ―

0022BCH ― ―

0022C0H
to ― ― ― ― Reserved
0022FCH
DFSTR
DFCTLR[R/W]B,H,W
002300H ― [R/W] B,H,W
-0------ --------
-----001

002304H ― ― ― ― WorkFlash

FLIFCTLR FLIFFER1 FLIFFER2

002308H [R/W] B,H,W ― [R/W] B,H,W [R/W] B,H,W
---0--00 -------- --------
00230CH
to ― ― ― ― Reserved
0023FCH
SEEARX[R] B,H,W DEEARX[R] B,H,W
002400H
--000000 00000000 --000000 00000000
EECSRX XBS RAM
EFEARX[R/W] B,H,W
002404H [R/W] B,H,W ― ECC control register
--000000 00000000
----0000
EFECRX[R/W] B,H,W
002408H ―
-------0 00000000 00000000
00240CH
to ― ― ― ― Reserved
002FFCH

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Address offset value / Register name

Address Block
+0 +1 +2 +3
SEEARA[R] B,H,W DEEARA[R] B,H,W
003000H
-----000 00000000 -----000 00000000
EECSRA
EFEARA[R/W] B,H,W Backup RAM
003004H [R/W] B,H,W ―
-----000 00000000 ECC control register
----0000
EFECRA[R/W] B,H,W
003008H ―
-------0 00000000 00000000
00300CH
to ― ― ― ― Reserved
003FFCH
004000H
to Backup RAM Backup RAM area
005FFCH
006000H
to ― ― ― ― Reserved
00EFFCH
00F000H
to ― ― ― ― Reserved [S]
00FEFCH
DSUCR [R/W] B,H,W
00FF00H ― ― OCDU [S]
-------- -------0
00FF04H
to ― ― ― ― Reserved [S]
00FF0CH
PCSR [R/W] B,H,W
00FF10H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
PSSR [R/W] B,H,W
00FF14H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18H
to ― ― ― ― Reserved [S]
00FFF4H
EDIR1 [R] B,H,W
00FFF8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
EDIR0 [R] B,H,W
00FFFCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]: It is a system register. The illegal instruction exception (data access error) is generated in these registers
in the user mode when reading and writing to it.

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 INTERRUPT VECTOR TABLE

This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers.

 Interrupt vector
Interrupt
number Default
Interrupt
Interrupt factor
Deci Hexa- level
Offset address for RN*1
TBR
mal decimal
Reset 0 00 - 3FCH 000FFFFCH -
System reserved 1 01 - 3F8H 000FFFF8H -
System reserved 2 02 - 3F4H 000FFFF4H -
System reserved 3 03 - 3F0H 000FFFF0H -
System reserved 4 04 - 3ECH 000FFFECH -
FPU exception 5 05 - 3E8H 000FFFE8H -
Exception of instruction access protection
6 06 - 3E4H 000FFFE4H -
violation
Exception of data access protection violation 7 07 - 3E0H 000FFFE0H -
Data access error interrupt 8 08 - 3DCH 000FFFDCH -
INTE instruction 9 09 - 3D8H 000FFFD8H -
Instruction break 10 0A - 3D4H 000FFFD4H -
System Reserved 11 0B - 3D0H 000FFFD0H -
System Reserved 12 0C - 3CCH 000FFFCCH -
System Reserved 13 0D - 3C8H 000FFFC8H -
Exception of invalid instruction 14 0E - 3C4H 000FFFC4H -
NMI request/
15 (FH)
XBS RAM double-bit error generation/ 15 0F 3C0H 000FFFC0H -
Fixed
Backup RAM double-bit error generation
External interrupt 0-7 16 10 ICR00 3BCH 000FFFBCH 0
External interrupt 8-15 17 11 ICR01 3B8H 000FFFB8H 1
Reload timer 0/1 18 12 ICR02 3B4H 000FFFB4H 2
Reload timer 2/3 19 13 ICR03 3B0H 000FFFB0H 3

Multi-function serial interface ch.0(reception

completed)/ 20 14 ICR04 3ACH 000FFFACH 4 *2
Multi-function serial interface ch.0(status)

Multi-function serial interface

21 15 ICR05 3A8H 000FFFA8H 5
ch.0(transmission completed)

Multi-function serial interface ch.1(reception

completed)/ 22 16 ICR06 3A4H 000FFFA4H 6*2
Multi-function serial interface ch.1(status)
Multi-function serial interface
23 17 ICR07 3A0H 000FFFA0H 7
ch.1(transmission completed)
LIN-UART2(reception completed) 24 18 ICR08 39CH 000FFF9CH 8

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Interrupt
number Default
Interrupt
Interrupt factor level
Offset address for RN*1
Deci Hexa- TBR
mal decimal
LIN-UART2(transmission completed) 25 19 ICR09 398H 000FFF98H 9
LIN-UART3(reception completed) 26 1A ICR10 394H 000FFF94H 10
LIN-UART3(transmission completed) 27 1B ICR11 390H 000FFF90H 11
LIN-UART4(reception completed) 28 1C ICR12 38CH 000FFF8CH 12
LIN-UART4(transmission completed) 29 1D ICR13 388H 000FFF88H 13
LIN-UART5(reception completed) 30 1E ICR14 384H 000FFF84H 14
LIN-UART5(transmission completed) 31 1F ICR15 380H 000FFF80H 15
LIN-UART6(reception completed) 32 20 ICR16 37CH 000FFF7CH 16
LIN-UART6(transmission completed) 33 21 ICR17 378H 000FFF78H 17
CAN0 34 22 ICR18 374H 000FFF74H -
CAN1 35 23 ICR19 370H 000FFF70H -
CAN2 36 24 ICR20 36CH 000FFF6CH -
Real time clock 37 25 ICR21 368H 000FFF68H -
Sound generator 0 /
38 26 ICR22 364H 000FFF64H 22
LIN-UART7(reception completed)
Sound generator 1 /
39 27 ICR23 360H 000FFF60H 23
LIN-UART7(transmission completed)
PPG0/1/10/11/20/21 40 28 ICR24 35CH 000FFF5CH 24
PPG2/3/12/13/22/23 41 29 ICR25 358H 000FFF58H 25
PPG4/5/14/15 42 2A ICR26 354H 000FFF54H 26
PPG6/7/16/17 43 2B ICR27 350H 000FFF50H 27
PPG8/9/18/19 44 2C ICR28 34CH 000FFF4CH 28
GDC / GDC_ALM 45 2D ICR29 348H 000FFF48H 29
Main timer/Sub timer/PLL timer 46 2E ICR30 344H 000FFF44H 30
Clock calibration unit
47 2F ICR31 340H 000FFF40H 31*3
(Sub oscillation) / Sound generator 4
A/D converter 48 30 ICR32 33CH 000FFF3CH 32
Clock calibration Unit
49 31 ICR33 338H 000FFF38H 33*3
( CR oscillation)
Free-run timer 0/2 50 32 ICR34 334H 000FFF34H -
Free-run timer 1/3 51 33 ICR35 330H 000FFF30H -
ICU0/6(fetching) 52 34 ICR36 32CH 000FFF2CH 36
ICU1/7(fetching) 53 35 ICR37 328H 000FFF28H 37
ICU2(fetching) 54 36 ICR38 324H 000FFF24H 38
ICU3(fetching) 55 37 ICR39 320H 000FFF20H 39
ICU4(fetching) 56 38 ICR40 31CH 000FFF1CH 40
ICU5(fetching) 57 39 ICR41 318H 000FFF18H 41
OCU0/1(match) 58 3A ICR42 314H 000FFF14H 42
OCU2/3(match) 59 3B ICR43 310H 000FFF10H 43
Base timer 0 IRQ0 /
Base timer 0 IRQ1 / 60 3C ICR44 30CH 000FFF0CH 44
Sound generator 2

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Interrupt
number Default
Interrupt
Interrupt factor Deci Hexa- level
Offset address for RN*1
TBR
mal decimal
Base timer 1 IRQ0 /
Base timer 1 IRQ1/
Sound generator3 / 61 3D ICR45 308H 000FFF08H 45*4
XBS RAM single bit error generation /
Backup RAM single bit error generation
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3E ICR46 304H 000FFF04H -
Delay interrupt 63 3F ICR47 300H 000FFF00H -
System Reserved
64 40 - 2FCH 000FFEFCH -
(Used for REALOSTM*5.)
System Reserved
65 41 - 2F8H 000FFEF8H -
(Used for REALOS.)
66 42 2F4H 000FFEF4H
Used with the INT instruction. | | - | | -
255 FF 000H 000FFC00H
*1: Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which
no RN (Resource Number) is assigned.
*2: The status of the multi function serial interface does not support a DMA transfer request caused by I2C
reception.
*3: The clock calibration unit does not support a DMA transfer caused by an interrupt.
*4: No support for a DMA transfer caused by an interrupt because of the RAM ECC bit error.
*5: REALOS is a trademark of Fujitsu Semiconductor Limited, Japan.

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 ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings

Rating
Parameter Symbol Unit Remarks
Min Max
VCC5 Vss-0.3 Vss+6.0 V
Power supply voltage*1,*2 VCC3 Vss-0.3 Vss+4.0 V Vcc3 ≤ Vcc5
DVCC Vss-0.3 Vss+6.0 V DVcc ≤ Vcc5
AVRH5 ≤ AVcc5 ≤
AVCC5 Vss-0.3 Vss+6.0 V
Analog power supply Vcc5
voltage*1,*2 AVR3 ≤ AVcc3 ≤
AVCC3 Vss-0.3 Vss+4.0 V
Vcc3
AVRH5 Vss-0.3 Vss+6.0 V AVRH5 ≤ AVcc5
Analog reference voltage*1
AVR3 Vss-0.3 Vss+4.0 V AVR3 ≤ AVcc3
5V pins other than
VI1 Vss-0.3 Vcc5+0.3 V
SMC multiplied pins
Input voltage*1
VI2 Vss-0.3 Vcc3+0.3 V 3.3V dedicated pin
VI3 Vss-0.3 Vcc5+0.3 V SMC shared pin
VIA5 Vss-0.3 Vcc5+0.3 V
Analog pin input voltage*1
VIA3 Vss-0.3 Vcc3+0.3 V
5V pins other than
VO1 Vss-0.3 Vcc5+0.3 V
SMC multiplied pins
Output voltage*1
VO2 Vss-0.3 Vcc3+0.3 V 3.3V dedicated pin
VO3 Vss-0.3 Vcc5+0.3 V SMC shared pin
Maximum clamp current ICLAMP – 4 mA *9
Total maximum clamp current Σ|ICLAMP | – 20 mA *9
When setting to
IOL1 – 7 mA
2mA*6
"L" level maximum output When setting to
IOL2 – 40 mA
current *3 30mA*7
When setting to
IOL3 – 30 mA
20mA*8
When setting to
IOLAV1 – 2 mA
2mA*6
"L" level average output When setting to
IOLAV2 – 30 mA
current *4 30mA*7
When setting to
IOLAV3 – 20 mA
20mA*8
ΣIOL1 – 50 mA *6
"L" level total output
ΣIOL2 – 250 mA *7
current *5
ΣIOL3 – 50 mA *8
When setting to
IOH1 – -7 mA
2mA*6
"H" level maximum output When setting to
IOH2 – -40 mA
current *3 30mA*7
When setting to
IOH3 – -30 mA
20mA*8
When setting to
IOHAV1 – -2 mA
2mA*6
"H" level average output When setting to
IOHAV2 – -30 mA
current *4 30mA*7
When setting to
IOHAV3 – -20 mA
20mA*8

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Rating
Parameter Symbol Unit Remarks
Min Max
ΣIOH1 – -50 mA *6
"H" level total output
ΣIOH2 – -250 mA *7
current *5
ΣIOH3 – -50 mA *8
– 1250 mW LQFP product
Power consumption PD
– 2500 mW HQFP product
Operating temperature TA -40 +105 °C
Storage temperature Tstg -55 +150 °C
*1: These parameters are based on the condition that VSS=AVSS=DVSS=0.0V
*2: Caution must be taken that AVCC5 and DVCC do not exceed VCC5.Similarly,AVCC3 must not exceed VCC3.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: Outputs other than p60-p87 and 3V pin.
*7: Output of P60-P87 pins.
*8: Output of 3V pin.
*9: · Corresponding pins: all general-purpose ports except P90/ADTG.(Except for the dedicated analog port)
· Use within recommended operating conditions.
· Use at DC voltage (current).
· The + B signal should always be applied by connecting a limiting resistor between the + B signal and the
microcontroller.
· The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input.
· Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+ B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting
other devices.
· Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is
supplied through the pin, the microcontroller may operate incompletely.
· Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on
reset may not function in the power supply voltage.
· Do not leave + B input pins open.

Sample recommended circuit

MB91590 series

Protective diode
Limiting resistor current

+B input (12 to 16V)

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

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2. Recommended operating conditions

(VSS=DVSS=AVSS=0.0V)
Value
Parameter Symbol Unit Remarks
Min Max
VCC5 4.5 5.5 V
DVCC 4.5 5.5 V
AVCC5 4.5 5.5 V Recommended operation guarantee range
VCC3 3.0 3.6 V
Power supply AVCC3 3.0 3.6 V
voltage VCC5 3.5 5.5 V
DVCC 3.5 5.5 V
AVCC5 3.5 5.5 V Operation guarantee range
VCC3 2.7 3.6 V
AVCC3 2.7 3.6 V
Use a ceramic capacitor or a capacitor that has
4.7
Smoothing the similar frequency characteristics. Use a
CS (tolerance within µF
capacitor* capacitor with a capacitance greater than CS as
±50%)
the smoothing capacitor on the VCC pin.
Operating
TA -40 +105 °C
temperature
*: Refer to the following diagram for details on the connection of smoothing capacitor CS.

 C Pin Connection Diagram

C_3

C_1 C_2

CS VSS DVSS AVSS CS CS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the electrical characteristics of the device are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact
sales representatives beforehand.

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3. DC characteristics
(TA:Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)

Sym Value
Parameter Pin name Conditions Unit Remarks
bol Min Typ Max
P060 to P067 CMOS input level is 0.7 VCC5+
VIH1 – V
P070 to P077 selected VCC5 0.3
P080 to P087 CMOS hysteresis 0.7 VCC5+
VIH2 – V
P090 to P097 input level is selected VCC5 0.3
P100 to P107 Automotive 0.8 VCC5+
VIH3 – V
P110 to P117 input level is selected VCC5 0.3
P120 to P127 TTL VCC5+
VIH4 P130 to P137 2.0 – V
input level is selected 0.3
RSTX,NMIX, 0.7 VCC5+
VIH5 – – V
MD2 VCC5 0.3
0.7 VCC5+
VIH7 MD0,MD1 – – V
VCC5 0.3
VCC5+
"H" level VIH8 DEBUGIF – 2.0 – V
0.3
input voltage P000 to P007
P010 to P017
P020 to P027 CMOS hysteresis 0.7 VCC3+
VIH10 P030 to P037 – V
input level is selected VCC3 0.3
P040 to P047
P050 to P057
PA2 to PA7 3.3V dedicated
PB2 to PB7 pin
PC2 to PC7
PD2 to PD7 TTL VCC3+
VIH11 PE2 to PE7 2.0 – V
input level is selected 0.3
PF2 to PF7
PG0 to PG7
PH3

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(TA:Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)

Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Typ Max
P060 to P067
P070 to P077 VCC5 = 4.5V VCC5-
VOH1 – VCC5 V
P080 to P087 IOH = -1.0mA 0.5
P090 to P097
P100 to P107
P110 to P117 VCC5 = 4.5V VCC5-
VOH2 – VCC5 V
P120 to P127 IOH = -2.0mA 0.5
P130 to P137
P060 to P067
DVCC = 4.5V DVCC-
VOH3 P070 to P077 – DVCC V SMC shared pin
IOH = -30.0mA 0.5
P080 to P087
P000 to P007
"H" level VCC3 = 3.0V
VOH4 P010 to P017
output voltage IOH = -2.0mA
P020 to P027
P030 to P037
P040 to P047 VCC3 = 3.0V
VOH5 P050 to P057 IOH = -5.0mA
PA2 to PA7 VCC3- 3.3V dedicated
– VCC3 V
PB2 to PB7 0.5 pin
PC2 to PC7 VCC3 = 3.0V
VOH6
PD2 to PD7 IOH = -10.0mA
PE2 to PE7
PF2 to PF7 VCC3 = 3.0V
VOH7 PG0 to PG7 IOH = -20.0mA
PH3

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(TA:Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)

Sym Value
Parameter Pin name Conditions Unit Remarks
bol Min Typ Max

P060 to P067 CMOS input Vss- 0.3×

VIL1 – V
P070 to P077 level is selected 0.3 VCC5
P080 to P087
CMOS hysteresis Vss- 0.3×
VIL2 P090 to P097 – V
Input level is selected 0.3 VCC5
P100 to P107
Automotive Vss- 0.5×
VIL3 P110 to P117 – V
input level is selected 0.3 VCC5
P120 to P127
P130 to P137 TTL Vss-
VIL4 – 0.8 V
input level is selected 0.3
RSTX,NMIX, Vss- 0.3×
VIL5 – – V
MD2 0.3 VCC5
Vss- 0.3×
VIL7 MD0,MD1 – – V
0.3 VCC5
"L" level Vss-
VIL8 DEBUGIF – – 0.8 V
input voltage 0.3
P000 to P007
P010 to P017
P020 to P027
CMOS hysteresis Vss- 0.3×
VIL10 P030 to P037 – V
input level is selected 0.3 VCC3
P040 to P047
P050 to P057
PA2 to PA7 3.3V dedicated
PB2 to PB7 pin
PC2 to PC7
PD2 to PD7
TTL Vss-
VIL11 PE2 to PE7 – 0.8 V
input level is selected 0.3
PF2 to PF7
PG0 to PG7
PH3

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(TA:Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)

Sym Value
Parameter Pin name Conditions Unit Remarks
bol Min Typ Max
P060 to P067
P070 to P077 VCC5 = 4.5V
VOL1 0 – 0.4 V
P080 to P087 IOL = 1.0mA
P090 to P097
P100 to P107
P110 to P117 VCC5 = 4.5V
VOL2 0 – 0.4 V
P120 to P127 IOL = 2.0mA
P130 to P137
P060 to P067
DVCC = 4.5V
VOL3 P070 to P077 0 – 0.55 V SMC shared pin
IOL = 30.0mA
P080 to P087
P127
P130 VCC5 = 4.5V I2C shared pin
VOL4 0 – 0.4 V
P132 IOL = 3.0mA (I2C is selected)
P133
"L" level
VCC5 = 2.7V
output voltage VOL5 DEBUGIF 0 – 0.25 V
IOL = 25.0mA
P000 to P007
P010 to P017 VCC3 = 3.0V
VOL6
P020 to P027 IOL = 2.0mA
P030 to P037
P040 to P047 VCC3 = 3.0V
VOL7 P050 to P057 IOL = 5.0mA
PA2 to PA7 3.3V dedicated
0 – 0.4 V
PB2 to PB7 pin
PC2 to PC7 VCC3 = 3.0V
VOL8
PD2 to PD7 IOL = 10.0mA
PE2 to PE7
PF2 to PF7 VCC3 = 3.0V
VOL9 PG0 to PG7 IOL = 20.0mA
PH3

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(TA:Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)

Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Typ Max
VCC=DVCC=
Input leak current IIL All input pins AVCC=5.5V -5 – +5 µA
VSS<VI<VCC
RUP1 RSTX,NMIX – 25 – 100 kΩ
Pull-up
All 5V port
RUP2 resistance is 25 – 100 kΩ
input pins
Pull-up resistance selected
Pull-up
All 3V port
RUP3 resistance is 17 – 66 kΩ
input pins
selected
RDOWN1 MD2 – 25 – 100 kΩ
Pull-down
All 5V port
RDOWN2 resistance is 25 – 100 kΩ
Pull-down input pins
selected
resistance
Pull-down
All 3V port
RDOWN3 resistance is 17 – 66 kΩ
input pins
selected
Other than VCC3,
VCC5, VSS,
DVCC, DVSS,
AVCC3,AVSS3,
CIN1 AVCC5,AVSS5, – – 5 15 pF
C1,C2,C3,
Input capacitance
P060 to P067,
P070 to P077,
P080 to P087
P060 to P067,
When using
CIN2 P070 to P077, – 15 45 pF
SMC
P080 to P087

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(TA:Recommended operating conditions, VCC=5.0V±10%, VCC3=3.3V±10%, VSS=DVSS=AVSS=0.0V)

Sym Pin Value

Parameter Conditions Unit Remarks
bol name Min Typ Max
At normal operation
FCP=128MHz, – 80 120 mA
Fcpp=32MHz
At normal operation
FCP=80MHz, – 60 100 mA
Fcpp=40MHz
ICC5
At FLASH write
FCP=128MHz, – 95 135 mA *3
Fcpp=32MHz
At FLASH erase
FCP=128MHz, – 95 135 mA *3
Fcpp=32MHz
At sleep mode
ICCS5 FCP=128MHz, – 25 65 mA
VCC5 Fcpp=32MHz
At bus sleep mode
ICCBS5 FCP=128MHz, – 15 55 mA
Fcpp=32MHz
Power When using external
supply – 650 1800
At RTC mode, clock*1, TA=+25°C
current ICCT5 µA
4 MHz source oscillation When using crystal
– 800 1950
TA=+25°C
When using external
When RTC mode – 130 230 µA
clock*1, TA=+25°C
ICCTS5 shutdown,
When using crystal
4 MHz source oscillation – 280 380 µA
TA=+25°C
ICCH5 At stop mode – 250 1400 µA TA=+25°C
When stop mode
ICCHS5 – 100 200 µA TA=+25°C
shutdown
When GDC normal
operation
– 100 200 mA
FgdC=81MHz,
ICC3 VCC3 FgdC-IF=108MHz,
When GDC operation stop – 2 100 mA
When GDC side regulator
– 70 200 µA
stop
When NTSC operates – 30 60 mA At AVR3=AVss3
IA3 AVCC3
When NTSC stop – 5 10 mA At AVR3=AVss3

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(TA:Recommended operating conditions, VCC=5.0V ± 10%, VCC3=3.3V±10%, VSS=DVSS=AVSS=0.0V)

Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Typ Max
PWM1Pn, DVcc=4.5V
High current output
PWM1Mn, IOH=30.0mA
drive capacity
ΔVOH3 PWM2Pn, Maximum – – 90 mV *2
Phase-to-phase
PWM2Mn, deviation of
deviation1
n=0 to 5 VOH3
PWM1Pn, Vcc=4.5V
High current output
PWM1Mn, IOL=30.0mA
drive capacity
ΔVOL3 PWM2Pn, Maximum – – 90 mV *2
Phase-to-phase
PWM2Mn, deviation of
deviation2
n=0 to 5 VOL2
*1: The power supply current value when the external clock is supplied from the X1 pin. Note that the power
supply current value when using the external clock is different from that using the oscillator.
*2: If PWM1P0/PWM1M0/PWM2P0/PWM2M0 of ch.0 is turned on simultaneously, the maximum deviation of
VOH3 / VOL3 for each pin is defined. Same for other channels.
*3: This product contains both program flash and WorkFlash. This parameter is defined when only one of them
is in the write/erase state.

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4. AC Characteristics
(1) Main Clock Timing
(TA:Recommended operating conditions, VCC5=5.0V ± 10%, VSS=DVSS=AVSS=0.0V)

Pin Cond Value

Parameter Symbol Unit Remarks
name itions Min Typ Max
Source oscillation clock
FC X0,X1 – 4 – MHz
frequency
Source oscillation clock –
tCYL X0,X1 – 250 – ns –
cycle time
Internal operating clock FCP – 2 – 128 MHz CPU clock
frequency* FCPP – – 2 – 40 MHz Peripheral bus clock
Internal operating clock tCP – – 7.8125 – 500 ns CPU clock
cycle time* tCPP – – 25 – 500 ns Peripheral bus clock
FCP=80MHz
CAN PLL jitter
tPJ – – -10 – +10 ns (4MHzMultiplied by
(when lock)
20)
Built-in CR oscillation
FCCR – – 50 100 200 kHz
frequency
*: The maximum / minimum value is defined when using the main clock and PLL clock.

 X0,X1 clock timing

tCYL

X0

 CAN PLL jitter

Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.

PLL output

t1 t2 t3 tn-1 tn

Ideal clock
Slow

t3
t2
Deviation time t1 tn-1
tn

Fast

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(1-2) Sub clock timing(products without s-suffix)

(TA:Recommended operating conditions, VCC5=5.0V ± 10%, VSS=DVSS=AVSS=0.0V)

Pin Value
Parameter Symbol Conditions Unit Remarks
name Min Typ Max
Source oscillation clock
FCL X0A,X1A – 32.768 – kHz
frequency
–
Source oscillation clock
tLCYL X0A,X1A – 30.52 – µs
cycle time

 X0A,X1A clock timing

tLCYL

X0A

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 Guaranteed operation range(5V operating microcontroller section)

Internal operation clock frequency vs. Power supply voltage

Recommended guaranteed
operation range

Guaranteed
operation range
5.5
Power supply voltage VCC5 (V)

4.5
3.5

PLL guaranteed operation

range

2 4 128

Internal operation clock frequency FCP (MHz)

Note: The CPU will be reset at the power supply voltage 4V±0.3V or less.

Oscillation clock frequency vs. Internal operation clock frequency

Internal operation clock frequency
PLL clock
Main Multipli Multipli
Multipli Multipli Multipli Multipli
Clock ... ed by ed by
ed by 1 ed by 2 ed by 3 ed by 4
20 32
Oscillation
clock 4MHz 2MHz 4MHz 8MHz 12MHz 16MHz ... 80MHz 128MHz
frequency

 Example of oscillation circuit

X0 X1

R=0Ω
4MHz

C1=10pF C2=10pF

Note: As to the product with its clock supervisor’s initial value is “ON”, when the oscillator is unable
to start within 20ms from the stop state the clock supervisor will detect the oscillation stop. As
a result, the CPU moves to the fail safe operation.
Design your print circuit board so that the oscillator can start oscillation within 20ms.

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AC characteristics are specified by the following measurement reference voltage values.

 Input Signal Waveform  Output Signal Waveform

Hysteresis Input Pin (Automotive) Output Pin
0.8Vcc5 2.4V
0.5Vcc5 0.8V

Hysteresis Input Pin (CMOS Normal)

0.7Vcc5
0.3Vcc5

Hysteresis Input Pin (CMOS Hysteresis)

0.7Vcc5
0.3Vcc5

TTL Input Pin

2.0V
0.8V

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(2) Reset Input

(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Con Value
Sym Pin
Parameter ditio Unit Remarks
bol name Min Max
ns
When normal
10 – µs
operation
Reset input time Oscillation time of oscillator*+
– ms At Stop mode
tRSTL RSTX – 100μs
100μs – µs At RTC mode
Width for reset
1μs – µs
input removal
*: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred μs and several ms, and for an external clock, the time is 0 ms.

tRSTL

RSTX
0.2Vcc5 0.2Vcc5

 At Stop mode
tRSTL

RSTX
0.2 VCC5 0.2 VCC5

90% of
amplitude
X0

Internal operation
clock 100 μs
Oscillation time Oscillation stabilization
of oscillator waiting time

Instruction
Internal reset execution

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(3) Power-on Conditions

(TA: Recommended operating conditions, VSS=0.0V)

Pin Value
Parameter Symbol Conditions Unit Remarks
name Min Typ Max
When turning on
Level detection
– VCC5 – 2.1 2.3 2.5 V power for
voltage
microcontroller
Level detection During voltage
– VCC5 – – – 125 mV
hysteresis width drop
Level detection time – – – – – 30 us *1
VCC5 = at level
Slope detection
– VCC5 detection release – – 4 mV/µs *2
undetected standard
level time
Power off time tOFF VCC5 – 50 – – ms *3
*1: If the fluctuation of the power supply is faster than the low voltage detection time, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope
detection. This is the standard when the power supply fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss.

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(4) Multi-function Serial

(4-1) UART timing
Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=0, SCR: SPI=0
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Con Value
Sym
Parameter Pin name ditio Unit Remarks
bol Min Max
ns

Serial clock cycle time tSCYC SCK0,SCK1 4tCPP – ns

SCK ↓ → SCK0,SCK1 Internal shift clock mode:

tSLOVI -30 +30 ns CL=50pF(When drive
SOT delay time SOT0,SOT1
– capability is 2mA or more.)
Valid SIN → CL=20pF(When drive
tIVSHI 34 – ns
SCK ↑setup time SCK0,SCK1 capability is 1mA)
SCK ↑ → SIN0,SIN1
tSHIXI 0 – ns
Valid SIN hold time

Serial clock "H"pulse width tSHSL tCPP+10 – ns

SCK0,SCK1
Serial clock "L" pulse width tSLSH 2tCPP-10 – ns

SCK ↓ → SCK0,SCK1
tSLOVE – 33 ns
SOT delay time SOT0,SOT1 External shift clock mode:
CL=50pF(When drive
Valid SIN →
tIVSHE – 10 – ns capability is 2mA or more.)
SCK ↑setup time SCK0,SCK1 CL=20pF(When drive
SCK ↑ → SIN0,SIN1 capability is 1mA)
tSHIXE 20 – ns
Valid SIN hold time

SCK fall time tF SCK0,SCK1 – 5 ns

SCK rise time tR SCK0,SCK1 – 5 ns

Notes:  AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.
 The maximum bard rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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• Internal shift clock mode

tSCYC
2.4V
SCKx
0.8V 0.8V
tSLOVI

2.4V
SOTx
0.8V
tIVSHI tSHIXI
VIH VIH
SINx VIL VIL

• External shift clock mode

tSLSH tSHSL

VIH VIH VIH

SCKx
VIL VIL VIL

tF tSLOVE tR
2.4V
SOTx
0.8V

tIVSHE tSHIXE
VIH VIH
SINx VIL VIL

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Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=1, SCR: SPI=0
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)

Sym Cond Value

Parameter Pin name Unit Remarks
bol itions Min Max

Serial clock cycle time tSCYC SCK0,SCK1 4tCPP – ns

SCK ↑ → SCK0,SCK1 Internal shift clock mode:

tSHOVI -30 +30 ns CL=50pF(When drive
SOT delay time SOT0,SOT1
– capability is 2mA or more.)
Valid SIN → CL=20pF(When drive
tIVSLI 34 – ns
SCK ↓setup time SCK0,SCK1 capability is 1mA)
SCK ↓ → SIN0,SIN1
tSLIXI 0 – ns
Valid SIN hold time
Serial clock "H" pulse
tSHSL tCPP+10 – ns
width
SCK0,SCK1
Serial clock "L"pulse
tSLSH 2tCPP-10 – ns
width
SCK ↑ → SCK0,SCK1
tSHOVE – 33 ns
SOT delay time SOT0,SOT1 External shift clock mode:
CL=50pF(When drive
Valid SIN →
tIVSLE – 10 – ns capability is 2mA or more.)
SCK ↓setup time SCK0,SCK1 CL=20pF(When drive
SCK↓ → SIN0,SIN1 capability is 1mA)
tSLIXE 20 – ns
Valid SIN hold time

SCK fall time tF SCK0,SCK1 – 5 ns

SCK rise time tR SCK0,SCK1 – 5 ns

Notes:  AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.
 The maximum bard rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

tSCYC

2.4V 2.4V
SCKx
0.8V
tSHOVI

2.4V
SOTx 0.8V
tIVSLI tSLIXI

VIH VIH
SINx
VIL VIL

 External shift clock mode

tSLSH
tSHSL
VIH VIH VIH
SCKx
VIL VIL VIL

tR tSHOVE tF
2.4V
SOTx
0.8V

tIVSLE tSLIXE
VIH VIH
SINx VIL VIL

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Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=0, SCR: SPI=1
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit
Min Min

Serial clock cycle time tSCYC SCK0,SCK1 4tCPP – ns

SCK↑→SOT SCK0,SCK1,
tSHOVI -30 +30 ns
delay time SOT0,SOT1 Internal shift clock mode
CL=50pF(When drive capability is
Valid SIN→SCK↓
tIVSLI 2mA or more.) 34 – ns
setup time SCK0,SCK1, CL=20pF(When drive capability is
SCK↓→ SIN0,SIN1 1mA)
tSLIXI 0 – ns
Valid SIN hold time
SOT→SCK↓ SCK0,SCK1,
tSOVLI 2tCPP-30 – ns
delay time SOT0,SOT1
Serial clock "H" pulse
tSHSL tCPP+10 – ns
width
SCK0,SCK1
Serial clock "L" pulse
tSLSH 2tCPP-10 – ns
width
SCK↑→SOT SCK0,SCK1,
tSHOVE – 33 ns
delay time SOT0,SOT1 External shift clock mode
CL=50pF(When drive capability is
Valid SIN→SCK↓
tIVSLE 2mA or more.) 10 – ns
setup time SCK0,SCK1, CL=20pF(When drive capability is
SCK↓→ SIN0,SIN1 1mA)
tSLIXE 20 – ns
Valid SIN hold time

SCK fall time tF SCK0,SCK1 – 5 ns

SCK rise time tR SCK0,SCK1 – 5 ns

Notes:  AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.
 The maximum bard rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

tSCYC

2.4V
SCKx
0.8V tSHOVI 0.8V
tSOVLI

2.4V 2.4V
SOTx
0.8V 0.8V
tIVSLI tSLIXI

VIH VIH
SINx VIL VIL

 External shift clock mode

tSLSH tSHSL

VIH VIH VIH

SCKx
VIL VIL VIL

* tF tR tSHOVE
2.4V 2.4V
SOTx
0.8V 0.8V
tIVSLE tSLIXE

VIH VIH
SINx VIL VIL

*: Changes when writing to TDR register

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Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=1, SCR: SPI=1
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit
Min Min

Serial clock cycle time tSCYC SCK0,SCK1 4tCPP – ns

SCK↓→SOT SCK0,SCK1,
tSLOVI -30 +30 ns
delay time SOT0,SOT1 Internal shift clock mode
CL=50pF(When drive capability is
Valid SIN→SCK↑
tIVSHI 2mA or more.) 34 – ns
setup time SCK0,SCK1, CL=20pF(When drive capability is
SCK↑→ SIN0,SIN1 1mA)
tSHIXI 0 – ns
Valid SIN hold time
SOT→SCK↑ SCK0,SCK1,
tSOVHI 2tCPP-30 – ns
delay time SOT0,SOT1
Serial clock "H"pulse
tSHSL tCPP+10 – ns
width
SCK0,SCK1
Serial clock "L" pulse
tSLSH 2tCPP-10 – ns
width
SCK↓→SOT SCK0,SCK1,
tSLOVE – 33 ns
delay time SOT0,SOT1 External shift clock mode
CL=50pF(When drive capability is
Valid SIN→SCK↑
tIVSHE 2mA or more.) 10 – ns
setup time SCK0,SCK1, CL=20pF(When drive capability is
SCK↑→ SIN0,SIN1 1mA)
tSHIXE 20 – ns
Valid SIN hold time

SCK fall time tF SCK0,SCK1 – 5 ns

SCK rise time tR SCK0,SCK1 – 5 ns

Notes:  AC characteristic in CLK synchronized mode.

 CL is the load capacitance applied to pins during testing.
 The maximum bard rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

tSCYC

2.4V 2.4V
SCKx
0.8V
tSOVHI
tSLOVI

2.4V 2.4V
SOTx
0.8V 0.8V
tIVSHI tSHIXI

VIH VIH
SINx VIL VIL

 External shift clock mode

tSHSL tSLSH
tR tF
VIH VIH VIH
SCKx
VIL VIL VIL

tSLOVE
*
2.4V 2.4V
SOTx
0.8V 0.8V
tIVSHE tSHIXE

VIH VIH
SINx VIL VIL

*: Changes when writing to TDR register

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(4-2)External clock (EXT = 1): asynchronous only

(TA: Recommended operating conditions, VCC5=5.0V±10%, VSS=AVSS=0.0V)

Value
Pin
Parameter Symbol Conditions Unit
name
Min Max

Serial clock "H" pulse width tSHSL CL=50pF tCPP+10 - ns

(When drive capability is
Serial clock "L" pulse width tSLSH SCK0, 2mA or more.) tCPP+10 - ns
SCK fall time tF SCK1 CL=20pF - 5 ns
(When drive capability is
SCK rise time tR 1mA) - 5 ns

tR tF
tSHSL tSLSH
SCK VIH VIH VIH
VIL VIL VIL

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(4-3) I2C timing

(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)

Standard High-speed
Sym mode mode*3 Rem
Parameter Pin name Conditions Unit
bol arks
Min Max Min Max
SCL clock frequency fSCL SCK0,SCK1, 0 100 0 400 kHz
SOT0,SOT1,
Repeat "start"
(SDA)
condition hold time tHDSTA 4.0 – 0.6 – μs
SCK0,SCK1,
SDA ↓ → SCL ↓
(SCL)
Period of "L" for SCL SCK0,SCK1,
tLOW 4.7 – 1.3 – μs
clock (SCL)
Period of "H" for SCL SCK0,SCK1,
tHIGH 4.0 – 0.6 – μs
clock (SCL)
CL=50pF
Repeat "start"
SCK0,SCK1, (When drive
condition setup time tSUSTA capability is 4.7 – 0.6 – μs
(SCL)
SCL ↑ → SDA ↓ 2mA or more.)
SOT0,SOT1, CL=20pF
Data hold time (SDA)
tHDDAT (When drive 0 3.45*2 0 0.9*3 μs
SCL ↓ → SDA ↓ ↑ SCK0,SCK1, capability is
(SCL) 1mA)
SOT0,SOT1, R = (VP/IOL) *1
Data setup time (SDA)
tSUDAT 250 – 100 – ns
SDA ↓ ↑ → SCL ↑ SCK0,SCK1,
(SCL)
SOT0,SOT1,
"Stop" condition setup
(SDA)
time tSUSTO 4.0 – 0.6 – μs
SCK0,SCK1,
SCL ↑ → SDA ↑
(SCL)
Bus-free time between
"stop" condition and tBUF – 4.7 – 1.3 – μs
"start" condition

Noise filter tSP – – 2tCPP*4 – 2tCPP*4 – ns

*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines,
respectively.
Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCPP is the peripheral clock cycle time. Adjust the clock of the bus in the surrounding to 8MHz or more when
use I2C.

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SDA

tSUDAT tSUSTA
tLOW tBUF

SCL

tHDSTA tHDDAT tHIGH tHDSTA tSP tSUSTO

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(5)LIN-UART timing
 Bit setting: ESCR: SCES=0, ECCR: SCDE=0
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Con Value
Sym
Parameter Pin name ditio Unit Remarks
bol Min Max
ns
SCK2,SCK3,
Serial clock cycle time tSCYC SCK4,SCK5, 5tCPP – ns
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK ↓ → SCK6,SCK7,
tSLOVI -50 +50 ns
SOT delay time SOT2,SOT3, Internal shift clock
SOT4,SOT5, – mode:
SOT6,SOT7 CL=80pF + 1 ∙ TTL
Valid SIN → SCK2,SCK3,
tIVSHI SCK4,SCK5, tCPP+80 – ns
SCK ↑setup time
SCK6,SCK7,
SCK ↑ → SIN2,SIN3,
tSHIXI SIN4,SIN5, 0 – ns
Valid SIN hold time
SIN6,SIN7
Serial clock "L" pulse
tSLSH SCK2,SCK3, 3tCPP-tR – ns
width
SCK4,SCK5,
Serial clock "H" pulse
tSHSL SCK6,SCK7 tCPP+10 – ns
width
SCK2,SCK3,
SCK4,SCK5,
SCK ↓ → SCK6,SCK7,
tSLOVE – 2tCPP+60 ns
SOT delay time SOT2,SOT3,
SOT4,SOT5,
External shift clock
SOT6,SOT7
– mode:
Valid SIN → SCK2,SCK3,
CL=80pF + 1 ∙ TTL
tIVSHE SCK4,SCK5, 30 – ns
SCK ↑setup time
SCK6,SCK7,
SCK ↑ → SIN2,SIN3,
tSHIXE SIN4,SIN5, tCPP+30 – ns
Valid SIN hold time
SIN6,SIN7

SCK fall time tF SCK2,SCK3, – 10 ns

SCK4,SCK5,
SCK rise time tR SCK6,SCK7 – 40 ns

Notes:  CL is the load capacitance applied to pins during testing.

 The maximum bard rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

tSCYC

2.4V
SCKx
0.8V

tSLOVI
2.4V
SOTx
0.8V

tIVSHI tSHIXI
VIH VIH
SINx VIL
VIL

 External shift clock mode

tSLSH tSHSL
VIH VIH VIH
SCKx
VIL VIL
VIL
tR
tF tSLOVE
2.4V
SOTx
0.8V
tIVSHE tSHIXE
VIH VIH
SINx VIL VIL

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 Bit setting: ESCR: SCES=1, ECCR: SCDE=0

(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Con Value
Sym
Parameter Pin name ditio Unit Remarks
bol Min Max
ns
SCK2,SCK3,
Serial clock cycle time tSCYC SCK4,SCK5, 5tCPP – ns
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK ↑ → SCK6,SCK7,
tSHOVI -50 +50 ns
SOT delay time SOT2,SOT3,
Internal shift clock mode:
SOT4,SOT5, –
CL=80pF+1 · TTL
SOT6,SOT7
Valid SIN → SCK2,SCK3,
tIVSLI SCK4,SCK5, tCPP+80 – ns
SCK ↓setup time
SCK6,SCK7,
SCK ↓ → SIN2,SIN3,
tSLIXI SIN4,SIN5, 0 – ns
Valid SIN hold time
SIN6,SIN7
Serial clock "H" pulse
tSHSL SCK2,SCK3, 3tCPP-tR – ns
width
SCK4,SCK5,
Serial clock "L" pulse
tSLSH SCK6,SCK7 tCPP+10 – ns
width
SCK2,SCK3,
SCK4,SCK5,
SCK ↑ → SCK6,SCK7,
tSHOVE – 2tCPP+60 ns
SOT delay time SOT2,SOT3,
SOT4,SOT5,
External shift clock
SOT6,SOT7
– mode:
Valid SIN → SCK2,SCK3,
CL=80pF+1 · TTL
tIVSLE 30 – ns
SCK ↓setup time SCK4,SCK5,
SCK6,SCK7,
SCK ↓ → SIN2,SIN3,
tSLIXE SIN4,SIN5, tCPP+30 – ns
Valid SIN hold time
SIN6,SIN7

SCK fall time tF SCK2,SCK3, – 10 ns

SCK4,SCK5,
SCK rise time tR SCK6,SCK7 – 40 ns

Notes:  CL is the load capacitance applied to pins during testing.

 The maximum bard rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

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 Internal shift clock mode

tSCYC

2.4V
SCKx
0.8V

tSHOVI
2.4V
SOTx
0.8V

tIVSLI tSLIXI

VIH VIH
SINx VIL
VIL

 External shift clock mode

tS H S L tS LS H

VIH VIH VIH

SCKx
VIL VIL VIL

tR tS LO V E tF
2 .4 V
SOTx
0 .8 V

tIV S LE tS LIX E

VIH VIH
S IN x VIL VIL

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 Bit setting: ESCR: SCES=0, ECCR: SCDE=1

(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)

Sym Conditi Value

Parameter Pin name Unit Remarks
bol ons Min Max
SCK2,SCK3,
Serial clock cycle time tSCYC SCK4,SCK5, 5tCPP – ns
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK ↑ → SCK6,SCK7,
tSHOVI -50 +50 ns
SOT delay time SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
Valid SIN→ SCK2,SCK3, Internal shift clock
tIVSLI SCK4,SCK5, – tCPP+80 – ns Mode:
SCK ↓ setup time
SCK6,SCK7, CL=80pF + 1 · TTL
SCK ↓ → SIN2,SIN3,
tSLIXI SIN4,SIN5, 0 – ns
Valid SIN hold time
SIN6,SIN7
SCK2,SCK3,
SCK4,SCK5,
SOT → SCK6,SCK7,
tSOVLI 3tCPP-70 – ns
SCK ↓ delay time SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
Notes:  CL is the load capacitance applied to pins during testing.
 The maximum bard rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

 Internal shift clock mode

tSCYC
2.4V
SCKx
0.8V tSHOVI 0.8V

t SOVLI

2.4V 2.4V
SOTx
0.8V 0.8V
t IVSLI t SLIXI
VIH VIH
SINx VIL VIL

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 Bit setting: ESCR: SCES=1, ECCR: SCDE=1

(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)

Sym Conditi Value

Parameter Pin name Unit Remarks
bol ons Min Max
SCK2,SCK3,
Serial clock cycle time tSCYC SCK4,SCK5, 5tCPP – ns
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK ↓ → SCK6,SCK7,
tSLOVI -50 +50 ns
SOT delay time SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
Valid SIN → SCK2,SCK3, Internal shift clock
tIVSHI SCK4,SCK5, – tCPP+80 – ns mode:
SCK ↑setup time
SCK6,SCK7, CL=80pF+1 · TTL
SCK ↑ → SIN2,SIN3,
tSHIXI SIN4,SIN5, 0 – ns
Valid SIN hold time
SIN6,SIN7
SCK2,SCK3,
SCK4,SCK5,
SOT → SCK6,SCK7,
tSOVHI 3tCPP-70 – ns
SCK ↑ delay time SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
Notes:  CL is the load capacitance applied to pins during testing.
 The maximum bard rate is limited by internal operation clock used and other parameters.
Refer to Hardware Manual for details.

 Internal shift clock mode

tSCYC
2.4V 2.4V
SCKx
0.8V

tSOVHI tSLOVI

2.4V 2.4V
SOTx
0.8V 0.8V
tIVSHI tSHIXI

VIH VIH
SINx VIL VIL

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(6) Timer input timing

(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Max
TIN0,TIN1,
TIN2,TIN3,
tTIWH
Input pulse width ICU0 to ICU5, – 4tCPP – ns
tTIWL
FRCK0,FRCK1,
TIOA,TIOB

 Timer input timing

TINx tTIWH tTIWL

ICUx
FRCK0, VIH VIH
FRCK1 VIL VIL
TIOA, TIOB

(7) Trigger input timing

(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Max
INT0 to
INT15, 5tCPP – ns
tTRGH ADTG,
Input pulse width –
tTRGL RX0,
RX1, 1 – μs At stop mode
RX2

 Trigger input timing

tTRGH tTRGL

INTx VIH VIH

ADTG
RXx VIL VIL

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(8) NMI input timing

(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)

Symb Pin Value

Parameter Conditions Unit Remarks
ol name Min Max
Input pulse width tNMIL NMIX – 4tCPP – ns

 NMIX input timing

tNMIL

NMIX VIH VIH

VIL VIL

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(9) Low voltage detection (External low-voltage detection)

(TA: Recommended operating conditions, VSS=AVSS=0.0V)

Pin Value
Parameter Symbol Conditions Unit Remarks
name Min Typ Max
Microcontroller
Power supply voltage VCC5 VCC5 – – – 5.5 V
unit
range
VCC3 VCC3 – – – 3.6 V GDC unit
When
power-supply
voltage falls at
VCC5 *1 3.9 4.1 4.3 V microcontroller
unit and detection
level is set
Detection voltage VDL initially
When
power-supply
voltage falls at
VCC3 *1 2.2 2.4 2.6 V
GDC unit and
detection level is
set initially
When
VCC5/
Hysteresis width VHYS – – – 125 mV power-supply
VCC3
voltage rises
Low voltage detection
Td – – – – 30 μs
time
Power supply voltage VCC5
– – -2 – 2 V/ms *2
fluctuation rate VCC3
*1: If the power supply voltage fluctuates within the time less than the low voltage detection time (Td), there is a
possibility that the low-voltage detection will occur or stop after the power supply voltage passes the
detection range.
*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation
of the power supply voltage within the limits of the power supply voltage fluctuation rate.

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(10) Low voltage detection (Internal low-voltage detection)

(TA: Recommended operating conditions, VSS=AVSS=0.0V)

Pin Value
Parameter Symbol Conditions Unit Remarks
name Min Typ Max
Power supply voltage
VRDP5 – – – 1.3 V
range
When
Detection voltage VRDL * 0.8 0.9 1.0 V power-supply
VCC
voltage falls
When
Hysteresis width VRHYS – – – 50 mV power-supply
voltage rises
Low voltage detection
Td – – – – 30 µs
time
*: If the fluctuation of the power supply is faster than the low voltage detection time(Td), there is a possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.

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(11) High current output slew rate

(TA: Recommended operating conditions, VCC5=AVCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Typ Max
P060 to P067,
Output rise /fall tR2 load capacitance
P070 to P077, – 15 – 100 ns
time tF2 85pF
P080 to P087

 Slew rate output timing

VH VH
VL VL VH=VOL2+0.9 (VOH2-VOL2)

+ +
VL=VOL2+0.1 (VOH2-VOL2)

tR2 tF2

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(12) Memory controller

(TA: Recommended operating conditions, VCC3=3.3V ± 10%, VSS=AVSS=0.0V)

Value
Parameter Symbol Pin name Conditions Unit Remarks
Min Max
MEM_XCS0
Chip Select delay time tcso – 18 ns
MEM_XCS1
Address delay time tao MEM_EA[24:0] – 18 ns
Data output delay time tdo – 18 ns
Data output → HiZ time tdoz – 18 ns
NOR Flash
tdsr 20 – ns
data setup time
NOR Flash MEM_ED[15:0] –
tdhr 0 – ns
data hold time
NOR Flash page Read
tdsp 20 – ns
data setup time
NOR Flash page Read
tdhp 0 – ns
data hold time
XRD delay time trdo MEM_XRD – 18 ns
XWR delay time twro MEM_XWR – 18 ns
Output delay is reference clock is an internal clock. The reference clock of MEM_RDY is an internal clock.

 NOR Flash read timing

Internal CLK

t cso t cso
MEM_XCS0
MEM_XCS1

t ao t ao
MEM_EA[24:0]

MEM_RDY

t rdo t rdo

MEM_XRD

t dsr t dhr

MEM_ED[15:0]

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 NOR Flash write timing

Internal CLK

t cso t cso
MEM_XCS0
MEM_XCS1
t ao t ao
MEM_EA[24:0]

MEM_RDY

twro t wro

MEM_XWR

t do t do tdo

MEM_ED[15:0] X

 NOR Flash Page read timing

Internal CLK

t cso t cso
MEM_XCS0
MEM_XCS1

t ao t ao t ao
MEM_EA[24:0]

MEM_RDY

t rdo

MEM_XRD

t dsp t dhp t dsp t dhp

MEM_ED[15:0]

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(13) GDC display signal

(13-1) Clock
AC timing of video interface clock signal
(TA: Recommended operating conditions, VCC3=3.3V ± 10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Unit Remarks
Min Max
DCLKI frequency Fdclki0 – 54 MHz
DCLKI "H"width Thdclki0 DCLKI 18 – ns
DCLKI "L"width Tldclki0 18 – ns
DCLK
DCLK frequency Tldclk0 – 54 MHz *1
(internal)
DCLKO frequency Fdclko0 DCLKO – 54 MHz *2
*1: The internal display clock of PLL synchronous mode is generated with internal PLL of display clock
prescaler.
*2: DCLKI or PLL internal display clock is output.

Apply only DCLKI synchronous mode. (reference clock= DCLKI)

 AC timing of video interface input signal
(TA: Recommended operating conditions, VCC3=3.3V ± 10%, VSS=AVSS=0.0V)
Value
Parameter Symbol Pin name Unit Remarks
Min Typ Max
HSYNC input setup time Tshsync0 4 – – ns
HSYNC(i)
HSYNC input hold time Thhsync0 1 – – ns
VSYNC input pulse width Twvsync0 VSYNC(i) 1 – – HSYNC

 Display input signal timing

DCLK In
1/Fdclkin Thdclkin Tldclkin

Twhsyncn

HSYNCn (i)
Tshsyncn Thhsyncn
Twvsyncn

VSYNCn (i)
Tsvsyncn Thvsyncn

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(13-2) AC Characteristics of Display Output Signal

 Clock Mode
There are multiple clock modes for display output clocks, as shown in Table 1. The AC timing parameters
vary depending on modes. The AC timing parameters are specified for each mode.

Table 1 Clock Mode for Display Output

Setting register bit field
DCM1 DCM3 Clock mode name
CKS DCKed DCKD DCKinv
0 0 0 0 Built-in PLL standard mode
0 0 0 1 Built-in PLL reverse edge mode
0 1 0 0 Cannot be used.
0 1 0 1
0 0 Other than 0 0 Built-in PLL delay mode
0 0 Other than 0 1 Built-in PLL reverse edge and delay mode
0 1 Other than 0 0 Built-in PLL both edge and delay mode
0 1 Other than 0 1
1 0 0 0 DCLKI input standard mode
1 0 0 1 DCLKI input reverse edge mode
1 1 0 0 Cannot be used.
1 1 0 1
1 0 Other than 0 0
1 0 Other than 0 1
1 1 Other than 0 0
1 1 Other than 0 1

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 AC Timing Parameters
This section describes parameters used for AC timing specifications. Select whether you use the DCLKO
reverse edge mode, depending on the use/non-use of delay mode.

When the delay mode is not used:

Use the DCLKO reverse edge mode when the external display device (TFT) receives the signal at the rising
edge of DCLKO.
Use the DCLKO standard mode when the external display device (TFT) receives the signal at the falling
edge of DCLKO.

When the delay mode is used:

Use the DCLKO standard mode when the external display device (TFT) receives the signal at the rising
edge of DCLKO.
Use the DCLKO reverse edge mode when the external display device (TFT) receives the signal at the
falling edge of DCLKO.

Note: Clock duty ratio when the clock frequency division ratio is even or odd

AC specifications use the half-cycle of the display output clock DCLKO as a parameter. In AC
specifications, the first half-cycle is indicated as tdcyc_f, and the second half-cycle is indicated as tdcyc_l.
Note that clock duty ratio will not be 50%:50% when the clock frequency division ratio (specified in SC
field of DCM1 register) is odd. If the clock frequency division ratio is odd, the first half-cycle tdcyc_f
becomes different from the second half-cycle tdcyc_l.

Figure 1 Clock duty ratio when the clock frequency division ratio is even or odd
 When the frequency division ratio is even

tdcyc
tdcyc_f tdcyc_l
DCLKO
(DCKinv=1)
tdcyc / 2 tdcyc / 2

 Example: When the frequency division ratio is odd (frequency division ratio = 3)

tdcyc
tdcyc_f tdcyc_l
DCLKO
(DCKinv=1)
tdcyc / 3 2×(tdcyc / 3)

When the clock frequency division ratio is 5, tdcyc_f : tdcyc_l will be 2:3.

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Built-in PLL reverse edge mode (DCM3.DCKinv=1)

Figure 2 shows the setup/hold definition when the external display device receives the signal at the
rising edge of DCLKO.

Figure 2 Built-in PLL Reverse Edge Mode Setup/Hold Definition

Use the clock mode of DCM3 register DCKinv=1

tdcyc
tdcyc_f tdcyc_l
DCLKO
(DCKinv=1)
tdosu tdohd
Data signal

Data signal:
ROUT7~0, GOUT7~0, BOUT7~0, HSYNC, VSYNC, CSOUT/GV, DEOUT

Built-in PLL standard mode (DCM3.DCKinv=0)

Figure 3 shows the setup/hold definition when the external display device receives the signal at the
falling edge of DCLKO.

 Figure 3 Built-in PLL Standard Mode Setup/Hold Definition

Use the clock mode of DCM3 register DCKinv=0

tdcyc
tdcyc_f tdcyc_l

DCLKO
(DCKinv=0)

tdosu tdohd
Data signal

Data signal:
ROUT7~0, GOUT7~0, BOUT7~0, HSYNC, VSYNC, CSOUT/GV, DEOUT

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Built-in PLL delay mode (DCM3.DCKinv=0)

Figure 4 shows the setup/hold definition when the external display device receives the signal at the
rising edge of DCLKO. (Example: When frequency division ratio = 4)

Figure 4 Built-in PLL Delay Mode Setup/Hold Definition

tdcyc

tpllcyc
DCLKO
(DCKinv=0)
(delay=0)
tdcyc_f tdcyc_l

DCLKO
(DCKinv=0)
(delay=3)

ROUT7-0 tdosu tdohd

GOUT7-0
BOUT7-0
HSYNC
VSYNC
DEOUT
CSOUT/GV

Built-in PLL reverse edge and delay mode (DCM3.DCKinv=1)

Figure 5 shows the setup/hold definition when the external display device receives the signal at the
falling edge of DCLKO. (Example: When frequency division ratio = 4)

 Figure 5 Built-in PLL Reverse Edge and Delay Mode Setup/Hold Definition

tdcyc

tpllcyc
DCLKO
(DCKinv=1)
(delay=0)

tdcyc_f tdcyc_l
DCLKO
(DCKinv=1)
(delay=3)

ROUT7-0 tdosu tdohd

GOUT7-0
BOUT7-0
HSYNC
VSYNC
DEOUT
CSOUT/GV

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Built-in PLL both edge and delay mode (DCM3.DCKinv=0)

Figure 6 shows the setup/hold definition when the external display device (TFT) receives the signal both
at the rising edge and the falling edge of DCLKO. (Example: When frequency division ratio = 4)
Although there are two sampling locations in both edge mode; one at the rising edge and the other at the
falling edge, the values of setup/hold definition are same.

Figure 6 Built-in PLL Both Edge and Delay Mode Setup/Hold Definition

tdcyc

tpllcyc
DCLKO
(delay=0)
tdcyc_f tdcyc_l

DCLKO
(delay=3)

ROUT7-0 tdosu tdohd tdosu tdohd

GOUT7-0
BOUT7-0
HSYNC
VSYNC
DEOUT
CSOUT/GV

Setup/Hold Definition in Delay Mode

The delay mode is a mode realized with DCLKO delay function, and it can provide delay to DCLKO signal
output itself. This can be used when both the following conditions are satisfied.

 The internal PLL is used to generate DCLKO (CKS field of DCM register = 0)
 The frequency division ratio to the internal PLL of DCLKO is 2 or more (SC field of DCM register > 0)

The delay value is set as the unit for internal PLL clock by DCKD field of DCM3 register. The meanings of
DCKD setting value are shown below.

When the internal PLL When the internal PLL frequency

frequency division ratio = 2 division ratio > 2
DCKD Delay DCKD Delay
000000 No additional delay 000000 No additional delay
000100 +1 PLL clock 000010 +2 PLL clock
000100 +3 PLL clock
000110 +4 PLL clock
: :
111110 +17 PLL clock

In delay mode, tdcyc_f and tdcyc_l are defined by the delay value above (e.g. "2" of "+2 PLL clock") as shown
below.

tdcyc_f = Delay value × tpllcyc

tdcyc_l = tdcyc – tdcyc_f

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DCLKI Input Standard Mode (DCM3.DCKinv=0)

Figure 7 shows the setup/hold definition when the external display device (TFT) receives the signal at
the falling edge of DCLKO.

Figure 7 DCLKI Input Standard Mode Setup/Hold Definition

Use the clock mode of DCM3 register DCKinv=0

tdcyc
tdcyc_f tdcyc_l
DCLKO
(DCKinv= 0)
tdosu tdohd

Data signal

Data signal:
ROUT7~0, GOUT7~0, BOUT7~0, HSYNC, VSYNC, CSOUT/GV, DEOUT

DCLKI Input Reverse Edge Mode (DCM3.DCKinv=1)

Figure 8 shows the setup/hold definition when the external display device (TFT) receives the signal at
the rising edge of DCLKO.

Figure 8 DCLKI Input Reverse Edge Mode Setup/Hold Definition

Use the clock mode of DCM3 register DCKinv=1

tdcyc
tdcyc_f tdcyc_l

DCLKO
(DCKinv=1)

tdosu tdohd

Data signal

Data signal:
ROUT7~0, GOUT7~0, BOUT7~0, HSYNC, VSYNC, CSOUT/GV, DEOUT

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 AC Timing Specifications

Parameter Symbol min.

Display clock cycle time tdcyc 18.5 ns

External load condition 50 pF

DCLKO Reference IO drive capability setting
Parameter Symbol
edge 10 mA 2 mA
Setup time tdosu tdcyc_f - 8.5ns tdcyc_f - 10.2ns
neg, pos *
Hold time tdohd tdcyc l - 1.7ns tdcyc_l - 3.3ns
*: DCLKO reference edge: This is the reference clock edge for setup time and hold time.
Pos = The external display device receives the signal at the rising edge of DCLKO.
Neg = The external display device receives the signal at the falling edge of DCLKO.

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(13-3) Video capture input

1/Fc i

CCLK

BIN7-2
GIN7-2 Tc is u Tc ih d
RIN7-2
HSIN
VSIN
VIN7-0

Value
Parameter Symbol Pin name Unit Remarks
Min Max
Capture input frequency Fci CCLK – 81.0 MHz
BIN7-2, GIN7-2,
Capture input setup time Tcisu 3.0 – ns
RIN7-2,
HSIN, VSIN,
Capture input hold time Tcihd 0.0 – ns
VIN7-0

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(14) GDC command trigger signal

Value
Parameter Symbol Pin name Unit Remarks
Min Max
Input trigger pulse width Ttrg CMDTRG 160 – ns

CMDTRG

Ttrg

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5. A/D Converter
(1) Electrical Characteristics
(TA: Recommended operating conditions, VCC5=AVCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Sym Value
Parameter Pin name Unit Remarks
bol Min Typ Max
Resolution – – – – 10 bit
Total error – – – – ±3 LSB
Non linearity error – – – – ±2.5 LSB
Differential linearity error – – – – ±1.9 LSB
AN0 to AVSS- AVSS+
Zero transition voltage VOT – V 1LSB=
AN31 1.5LSB 2.5LSB
(AVCC-AVSS) /
AN0 to AVRH5- AVRH5+
Full-scale transition voltage VFST – V 1024
AN31 3.5LSB 0.5LSB
Sampling time tSMP – 1.2 – – μs *1
Compare time tCMP – 1.8 – – μs *1
A/D conversion time tCNV – 3.0 – – μs *1
AN0 to VAVSS ≤
Analog port input current IAIN -5 – +5 μA
AN31 VAIN ≤ VAVCC
AN0 to
Analog input voltage VAIN AVSS – AVRH5 V
AN31
AVRH5 ≤
AVRH AVRH5 4.5 – 5.5 V
Reference voltage AVCC5
AVRL AVSS – 0.0 – V
IA – – 4.0 mA
AVCC
IAH – – 6.0 μA *2
Power supply current
IR – 600 900 μA
AVRH5
IRH – – 5 μA *2
AN0 to
Variation between channels – – – 4 LSB
AN31
*1: Time for each channel.
*2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped.

Note: Be sure to use the clock with a frequency between 8MHz and 17MHz for the ADC compare clock in order
to ensure its accuracy.

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(2) Definition of A/D Converter Terms

Resolution : Analog variation that is recognized by an A/D converter.

Non linearity error : Deviation of the actual conversion characteristics from a straight line that
connects the zero transition point ("00 0000 0000"← →"00 0000 0001") to the
full-scale transition point ("111111 1110" ← →"11 1111 1111").

Differential linearity : Deviation of the input voltage from the ideal value that is required to change the
error output code by LSB.

Total error : Difference between the actual value and the theoretical value. The total error
includes zero transition error, full-scale transition error, and non linearity error.

Total error

3FF

1.5 LSB
3FE Actual conversion
characteristics
3FD
{1 LSB × (N - 1) + 0.5 LSB}
Digital output

004 VNT
(Actually-measured value)
003
Actual conversion
002 characteristics
Ideal characteristics
001
0.5 LSB
AVSS AVRH5
Analog input

VNT - {1LSB} × (N - 1) + 0.5LSB}

Total error of digital output N = [LSB]
1LSB
AVRH5 - AVSS
1LSB (Ideal value) = [V]
1024

N: A/D converter digital output value.

VOT (Ideal value) = AVSS + 0.5 LSB[V]
VFST (Ideal value) = AVRH5 - 1.5 LSB[V]
VNT: Voltage at which the digital output changes from (N - 1) to N.

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Non linearity error Differential linearity error

Ideal
3FF characteristics
Actual conversion
3FE characteristics
{1 LSB × (N - 1) N+1 Actual conversion
+ VOT} characteristics
VFST
3FD (actual
measurement

Digital output
Digital output

value)
N
VNT (actual
004 measurement value)
V(N + 1) T
Actual conversion N-1 (actual measurement
003
characteristics value)
VNT
002 (actual measurement value)
Ideal characteristics Actual conversion
001 N-2
characteristics
VOT (actual measurement value)
AVSS AVRH5 AVSS AVRH5
(AVRL) Analog input (AVRL) Analog input

VNT - {1LSB} × (N - 1) + VOT

Linearity error of digital output N = [LSB]
1LSB

V(N + 1) T - VNT
Differential linearity error of digital output N = - 1 [LSB]
1LSB

VFST - VOT
1LSB = [V]
1022

VOT : Voltage at which the digital output changes from “000H” to “001 H”.
VFST : Voltage at which the digital output changes from “3FE H” to “3FF H”.

(3) Notes on Using A/D Converter

<About the output impedance of the analog input of external circuit>

· External impedance values of the external input of 4.2 kΩ or lower (sampling time = 1.2 μs@ machine
clock of 16 MHz) are recommended. When the external impedance is too high, the sampling time for
analog voltages may not be sufficient. In this case, it is recommended to connect the capacitor
(approx. 0.1 μF) to the analog input pin.

 Analog input circuit model

R
Comparator

Analog input C
During sampling: ON

R C
MB91590series 4.0kΩ (Max) 16.1pF (Max)

Note: Listed values must be considered as reference values.

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6. Flash memory
(1) Electrical Characteristics
Value
Parameter Unit Remarks
Min Typ Max
8 Kbyte sector*1,
– 200 800 ms excluding internal
preprogramming time
8 Kbyte sector*1,
– 300 1100 ms including internal
preprogramming time
Sector erase time
64 Kbyte sector*1,
– 400 2000 ms excluding internal
preprogramming time
64 Kbyte sector*1,
– 700 3700 ms including internal
preprogramming time
Exclusive of overhead time at
8-bit writing time – 9 288 µs
system level*1
Exclusive of overhead time at
16-bit writing time – 12 384 µs
system level*1
Exclusive of overhead time at
ECC writing time – 9 288 µs
system level*1
1,000 cycles/
20 years,
Temperature at writing/erasing
Erase cycle*2/ 10,000 cycles/
– – – Tj<+105°C,
Data retain time 10 years,
Average TA=+85°C*3
100,000 cycles/
5 years
*1: The guaranteed value for erasure up to 100,000 cycles.
*2: Number of erase cycles for each sector.
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).

(2) Notes

While the Flash memory is written, shutdown of the external power (Vcc5) is prohibited.
In the application system where Vcc5 might be shut down while writing, be sure to turn the power off by
using an external voltage detector.
To put it concretely, after the external power supply voltage falls below the detection
voltage (VDL*1), hold Vcc5 at 2.7V or more within the duration calculated by the following expression:

Td*1[µs] + (period of PCLK [µs] x 257) + 50 [µs]

*1: See “4.AC Characteristics (9) Low-voltage detection (External low-voltage detection) ”

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 ORDERING INFORMATION

Part number Package

MB91F591BPMC-GSE1
MB91F591BSPMC-GSE1
MB91F591BHPMC-GSE1
MB91F591BHSPMC-GSE1
MB91F592BPMC-GSE1
MB91F592BSPMC-GSE1 208-pin plastic LQFP
(FPT-208P-M06)
MB91F592BHPMC-GSE1
MB91F592BHSPMC-GSE1
MB91F594BPMC-GSE1
MB91F594BSPMC-GSE1
MB91F594BHPMC-GSE1
MB91F594BHSPMC-GSE1

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 PACKAGE DIMENSIONS
 Dimension of LQFP-208(FPT-208P-M06)
208-pin plastic LQFP Lead pitch 0.50 mm

Package width ×
28.0 × 28.0 mm
package length

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weight 2.55 g

Code
(FPT-208P-M06) P-LFQFP208-28×28-0.50
(Reference)

208-pin plastic LQFP Note 1) * : These dimensions do not include resin protrusion.
(FPT-208P-M06) Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

30.00±0.20(1.181±.008)SQ
* 28.00±0.10(1.102±.004)SQ
0.145±0.055
(.006±.002)
156 105

157 104

0.08(.003)

Details of "A" part

+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004

INDEX 0.10±0.05
0°~8° (.004±.002)
(Stand off)
208 53
"A"

LEAD No. 1 52 0.60±0.15 0.25(.010)

0.50(.020) (.024±.006)
0.22±0.05
0.08(.003) M
(.009±.002)

Dimensions in mm (inches).
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F208027S-c-3-5 Note: The values in parentheses are reference values.

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

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 Dimension of HQFP-208(FPT-208P-M04)(Under consideration)

208-pin plastic QFP Lead pitch 0.50 mm

Package width ×
28.0 mm × 28.0 mm
package length

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 3.95 mm MAX

Weight 5.71g

(FPT-208P-M04) Remark Low heat resistance type

208-pin plastic QFP Note 1) * : These dimensions do not include resin protrusion.
(FPT-208P-M04) Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

30.60±0.20(1.205±.008)SQ

+0.03
0.17 –0.08
+.001
156 105 .007 –.003

157 104

0.08(.003)

Details of "A" part

+0.20
3.75 –0.30
+.008 (Mounting height)
.148 –.012

+0.10
0.40 –0.15
+.004
INDEX 0°~8° .016 –.006
(Stand off)

208 53
"A"
0.50±0.20 0.25(.010)
(.020±.008)
LEAD No. 1 52
0.60±0.15
0.50(.020) (.024±.006)
0.22±0.05
0.08(.003) M
(.009±.002)

Dimensions in mm (inches).
C 2003-2010 FUJITSU SEMICONDUCTOR LIMITED F208020S-c-3-6 Note: The values in parentheses are reference values.

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

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 MAJOR CHANGES IN THIS EDITION

Page Section Page Change Results (See this data sheet for the detail.)
- - Contact the sales representative for the detail of changed parts.

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FUJITSU SEMICONDUCTOR LIMITED

Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/

For further information please contact:

North and South America Asia Pacific

FUJITSU SEMICONDUCTOR AMERICA, INC. FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
1250 E. Arques Avenue, M/S 333 151 Lorong Chuan,
Sunnyvale, CA 94085-5401, U.S.A. #05-08 New Tech Park 556741 Singapore
Tel: +1-408-737-5600 Fax: +1-408-737-5999 Tel : +65-6281-0770 Fax : +65-6281-0220
http://us.fujitsu.com/micro/ http://sg.fujitsu.com/semiconductor/

Europe FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.

FUJITSU SEMICONDUCTOR EUROPE GmbH 30F, Kerry Parkside, 1155 Fang Dian Road,
Pittlerstrasse 47, 63225 Langen, Germany Pudong District, Shanghai 201204, China
Tel: +49-6103-690-0 Fax: +49-6103-690-122 Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://emea.fujitsu.com/semiconductor/ http://cn.fujitsu.com/fss/

Korea FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.

FUJITSU SEMICONDUCTOR KOREA LTD. 10/F., World Commerce Centre, 11 Canton Road,
902 Kosmo Tower Building, 1002 Daechi-Dong, Tsimshatsui, Kowloon, Hong Kong
Gangnam-Gu, Seoul 135-280, Republic of Korea Tel : +852-2377-0226 Fax : +852-2376-3269
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://cn.fujitsu.com/fsp/
http://kr.fujitsu.com/fsk/

Specifications are subject to change without notice. For further information please contact each office.

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of
any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR
assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would
result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department

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