FUJITSU SEMICONDUCTOR

FR50
32-BIT MICROCONTROLLER
MB91F376GS
Datasheet

Release 1.2 28-Feb-2005

 Revision History

Revision Date Item

1.0 4-Jun-2004 First release

1.1 30-Jun-2004 Correct part number from MB91F376S to MB91F376GS

1.2 28-Feb-2005 Correct part number from MB91F376G to MB91F376GS in overview

FME / EMDC / Br + ALan - mb91f376s.fm 2 23-Mar-05

Table of Contents
1 MB91F376GS Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 MB91F376GS Block Structure . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Core Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Pin Assignment MB91F376GS . . . . . . . . . . . . . . . . . . . . . 12
1.5 I/O Pins and Their Functions . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Flash Memory Mode of MB91F376GS . . . . . . . . . . . . . . . 17
2 IO-Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Power-on-sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Handling of Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Emulation Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
A I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
B Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

FME / EMDC / Br+ALan - mb91f376g.fm 3 23-Mar-05

CHAPTER 1 MB91F376GS Overview
MB91F376GS (S= single clock) is a bondvariant of MB91F376G.

On MB91F376GS the RTC module is connected to the 4 MHz oscillator instead of the 32 KHz oscillator
as on MB91F376G.

The 32KHz oscillator pins have no function on MB91F376GS.

Please see the documentation for MB91F376G for details.

FME / EMDC / Br + ALan - mb91f376s.fm 4 23-Mar-05

1.1 MB91F376GS Block Structure
4 MHz Oscillator FR50 Watchdog
Clock Modulator Core Timer

User RAM
16 KB 32

Bit Search 32

Module Instruction
RAM 4KB
Boot ROM
2KB
32
Bus DMA
F-bus RAM Converter Controller
16 KB

Flash Memory
768 KB 32

R-Bus User Logic CAN

Adapter Bus Interface (2ch)

16
SIO Prescaler/ External
ADC (8 ch)
SIO (2ch) Interrupt (8 ch)

U-Timer/
UART (2ch)

Reload Alarm RTC

I2C Timer (6ch) Comparator

Power down Free Running

ICU (4 ch) OCU (2 ch)
Reset Counter (2 ch)

Voltage
regulator Sound Stepper Motor Prog. Pulse
Generator Control (4ch) Generator (8ch)

FME / EMDC / Br+ALan - mb91f376g.fm 5 23-Mar-05

1.2 Core Functionality

Function Feature Remarks

32-bit Fujitsu RISC Core
FR50 Core
FR30 software compatible
Setting of frequencies for CPU and
peripherals

Clock module Low power consumption modes:

(clock control, clock RTC mode: only the Real Time Clock
divider, PLLs) and the selected oscillator are active
(= STOP mode and bit 0 of STCR is set
to 0)
STOP mode: all internal circuits and the
oscillation circuits are halted
adjustable watchdog timer interval
Watchdog (between 220 and 226 system clock
cycles)

I-RAM 4 kB I-RAM
see remark below table
D-Bus RAM
RAM for user data see remark below table
16 kB
F-Bus RAM
RAM for data and code see remark below table
16 kB
sector architecture:

sector 0 :64 kB | sector 2: 64 kB

sector 1: 64 kB | sector 3: 64 kB
sector 4: 64 kB | sector 11: 64 kB Flash memory on F376G connected
sector 5: 64 kB | sector 12: 64 kB to F-Bus
sector 6: 64 kB | sector 13: 64 kB
sector 7: 32 kB | sector 14: 32 kB Minimum 10000 program/erase
sector 8: 8 kB | sector 15: 8 kB cycles
Flash Memory
sector 9: 8 kB | sector 16: 8 kB Minimum 10 years data retention
768 kB
sector 10:16 kB | sector 17: 16 kB
sector 0 :64 kB | sector 2: 64 kB
sector 1: 64 kB | sector 3: 64 kB Net read cycle time to the memory
| | is 50ns. For overall access time see
V V settings in Chapter 2.1
16 bit 16 bit

write access is 16 bit wide, read access

can be 16 or 32 bit wide
Boot ROM
2 kB

FME / EMDC / Br + ALan - mb91f376s.fm 6 23-Mar-05

 5 channels
up to 16 DMA sources can be used
DMA
transfer modes:
single/block, burst, continuous
8 external interrupt channels,
Interrupt Controller 38 internal interrupts,
16 programmable priority levels
Searches a word for the position of the
Bit Search Module first “1” and “0” change bit, starting from
the MSB. Performs the search in 1 cycle.
Fixed Reset Vector Hard wired reset and mode vector code start at 0F:4000H
Voltage Regulator Generates internal voltage of 3.3 V

Remark:

Set bit 9 (SYNCR) of TBCR to 1 to enable the synchronisation of the reset signal; a reset will be generated only
after all bus accesses have been done. This avoids that erroneous data are written into the RAMs during reset.

FME / EMDC / Br+ALan - mb91f376g.fm 7 23-Mar-05

1.3 Features

Function Feature Remarks

16-bit PWM Timer
16 bit down counter, cycle and duty set-
ting registers
interrupt at triggering, cycle or duty
match
can be triggered by software or reload
PPG for dimmer
timer
(8 channels)
PWM operation and one-shot operation

Clock disable

internal prescaler allows fRES/1, fRES/4,

required frequencies are 90-300 Hz
fRES/16, fRES/64 as counter clock
successive approximation, internal sam-
ple and hold circuit
10-bit resolution, 5 V operation,
(conversion time: 178 cycles of CLKP)
program selectable analogue input chan-
nels:
single conversion mode
continuous conversion mode
stop conversion mode
ADC
(8 channels)
interrupt at the end of a conversion can
be used to activate DMA transfer

activation by software or reload timer can

be selected

Prescaling is done internally

Clock disable
16-bit reload timer,
Basic Interval Timer
includes clock prescaler (fRES/21, fRES/23,
(6 channels)
fRES/25)
conforms to CAN specification version
2.0 A and B
automatic re-transmission in case of
error
automatic transmission responding to
remote frame
CAN prioritized 16 message buffers for data
CAN allows TSEG2 = RSJW setting
(2 channels) and IDs
supports multiple messages
flexible configuration of acceptance filter-
ing: full bit compare / full bit mask / two
partial bit masks
supports up to 1 Mb/s
Clock Disable

FME / EMDC / Br + ALan - mb91f376s.fm 8 23-Mar-05

 can be programmed to be edge sensitive
External Interrupt or level sensitive
(8 channels) interrupt masking and request pending
bits per channel
I2C-1 master or slave transmission Only I2C-1 or I2C-2 can be used, not
for standard mode arbitration function both in parallel. Bit 0 of F362MD will
clock synchronization function be used to decide which module is
slave address and general call address connected to the SCL and SDA
detect function pads. By default it is I2C-1.
transfer direction detect function
start condition repeat generation and Multimaster operation is not possi-
detection function ble.
bus error detect function

compatible to I2C standard mode specifi-

cation (operation up to 100 kHz,
7 bit addressing)

includes clock divider functionality

Clock disable
I2C-2 master or slave transmission Only I2C-1 or I2C-2 can be used, not
for standard and fast arbitration function both in parallel. Bit 0 of F362MD will
mode clock synchronization function be used to decide which module is
slave address and general call address connected to the SCL and SDA
detect function pads. By default it is I2C-1.
transfer direction detect function
start condition repeat generation and SCL and SDA lines include optional
detection function noise filter. The noise filter allows
bus error detect function the suppression of spikes in the
range of 1 to 1.5 cycles of CLKP.
compatible to I2C standard and fast mode
specification (operation up to 400 kHz, Communication on the I2C bus
10 bit addressing) between other connected devices is
not possible if MB91F36xGB/366GA
includes clock divider functionality is not connected to the supply volt-
age.

Clock disable Multimaster operation is not possi-

ble.
rising edge, falling edge or rising & falling
16-bit Input Capture edge sensitive
(ICU) two 16-bit capture registers
(4 channels) signals an interrupt at external event
Clock disable
signals an interrupt when a match with
16-bit Output Compare
of 16-bit IO timer occurs
OCU
an output signal can be generated
(2 channels)
Clock disable

FME / EMDC / Br+ALan - mb91f376g.fm 9 23-Mar-05

 16-bit free running timer, signals an inter-
rupt when overflow or match with
Free running Timer compare register_0
(2 channels for ICU and includes prescaler (fRES/22, fRES/24, fRES/
OCU modules) 25, fRES/26)
timer data register has R/W access
Clock disable
monitors an external voltage
and generates an interrupt in case of a
voltage lower or higher than the defined
Alarm Comparator
thresholds
(OV/UV detection)
status is readable, interrupts can be uses external 4:1 voltage divider
masked separately
Clock disable
monitors Vdd and generates a reset if
Power down reset Vdd is less than a defined threshold volt- disabled in RTC and STOP modes
age
Serial IO
transfer can be started from MSB or LSB
Serial IO
supports internal clock synchronized supports positive and negative clock
SIO
transfer and external clock synchronized edge synchronization
Synchronous Serial
transfer
Interface
(2 channels)
prescaler for shift clock allows:
+
fRES/3, fRES/4, fRES/5, fRES/6, fRES/7,
SIO-Prescaler
fRES/8
(2 channels)
Clock disable
Sound Generator 8-bit PWM signal is mixed with tone fre-
(Buzzer) quency from 8-bit reload counter Target frequency to be programma-
PWM clock by internal prescaler: ble in the range of 300 Hz to 5 kHz
fRES/1, fRES/2, fRES/4, fRES/8
tone frequency: PWM frequency / 2 / fRES/1 and a reload value of 5 result
(reload value + 1) in 5.2 kHz at fRES = 16MHz,
fRES/4 and a reload value of 25
result in 300.48 Hz @ fRES = 16MHz
Clock disable
Stepper Motor Control four high current outputs for each chan-
(4 channels) nel target frequency: 16 kHz
two synchronized 8-bit PWMs per chan-
nel
internal prescaling for PMW clock:
fRES, fRES/2, fRES/4, fRES/5, fRES/6, fres/8

includes zero detection circuit

Clock disable

FME / EMDC / Br + ALan - mb91f376s.fm 10 23-Mar-05

 serial I/O port for performing asynchro-
UART
nous (start-stop synchronization) com-
(2 channel)
munication

full duplex, double buffering

supports multi-processor mode
variable data length (7/8 bit)
1 or 2 stop bits
error detection function (parity, framing,
overrun) polarity of the port signals for
interrupt function receive and transmit is programma-
NRZ type transfer format ble

baud rate generated by U-Timer

16-bit timer to generate the required

UART clock:
fRES/25,…,~fRES/221 (asynchr. mode)
U-Timer
(1 per UART)
Clock disable
facility to correct oscillation deviation
read/write accessible second/minute/
hour registers
can signal interrupts every second/ On MB91F376GS the RTC module
minute/hour/day is connected to the 4 MHz oscillator.
Real Time Clock (RTC)
internal clock divider and prescaler pro-
(Watch Timer)
vide exact 1s clock
this clock is based on the 4 MHz oscilla-
tor or if the subclock option is selected on
the 32 kHz subclock

Clock disable

FME / EMDC / Br+ALan - mb91f376g.fm 11 23-Mar-05

1.4 Pin Assignment MB91F376GS

MB91F376GS

NC

FME / EMDC / Br + ALan - mb91f376s.fm 12 23-Mar-05

1.5 I/O Pins and Their Functions
Table 1.5a Pinning

General Circuit
Pin No.
Pin Name I/O Purpose Type Function
QFP120
I/O Port
1 VDD
2 VSS
3 PJ4 I/O PJ4 A Digital IO-Port
4 PJ5 I/O PJ5 A Digital IO-Port
5 PJ6 I/O PJ6 A Digital IO-Port
6 PJ7 I/O PJ7 A Digital IO-Port
7 PI3 I/O PI3 A Digital IO-Port
8 VDD
9 VSS
10 SGO I/O PM0 A Sound Gen. SGO
11 SGA I/O PM1 A Sound Gen. SGA
12 SDA I/O PM2 Y I2C SDA
13 SCL I/O PM3 Y I2C SCL
14 VDD
15 VSS
16 AVRH R Analog Voltage Ref. high
17 AVCC Analog VCC
18 AVSS/AVRL Ana.Volt.Ref.low/An.VSS
19 AN0 I/O PH0 B ADC input
20 AN1 I/O PH1 B ADC input
21 AN2 I/O PH2 B ADC input
22 AN3 I/O PH3 B ADC input
23 AN4 I/O PH4 B ADC input
24 AN5 I/O PH5 B ADC input
25 AN6 I/O PH6 B ADC input
26 AN7 I/O PH7 B ADC input
27 N.C. not connected pin
28 N.C. not connected pin
29 ALARM I D Alarm Comparator Input
30 VSS
31 BOOT I/O P93 A BOOT pin
32 TESTX I E Test mode pin
33 CPUTESTX I E Test mode pin
34 VDD
35 X0 I H 4 MHz Oscillator Pin
36 X1 O H 4 MHz Oscillator Pin
37 VSS
38 MONCLK O G Clock output
39 INT0 I/O PK0 A Ext. Interrupt
40 INT1 I/O PK1 A Ext. Interrupt
41 INT2 I/O PK2 A Ext. Interrupt
42 INT3 I/O PK3 A Ext. Interrupt
43 INT4 I/O PK4 A Ext. Interrupt
44 INT5 I/O PK5 A Ext. Interrupt

FME / EMDC / Br+ALan - mb91f376g.fm 13 23-Mar-05

 Table 1.5a Pinning

General Circuit
Pin No.
Pin Name I/O Purpose Type Function
QFP120
I/O Port
45 INT6 I/O PK6 A Ext. Interrupt
46 INT7 I/O PK7 A Ext. Interrupt
47 VDD supply pin for internal voltage regulator
48 VCC3/C Capacitor pin for internal voltage reg.
49 VSS
50 IN0 I/O PL0 A ICU input
51 IN1 I/O PL1 A ICU input
52 IN2 I/O PL2 A ICU input
53 IN3 I/O PL3 A ICU input
54 OUT0 I/O PL4 A OCU Output
55 OUT1 I/O PL5 A OCU Output
56 VDD supply pin for internal voltage regulator
57 MD0 I T Mode Pin
58 MD1 I T Mode Pin
59 MD2 I T Mode Pin
60 INITX I U Initial
61 VDD supply pin for internal voltage regulator
62 VSS
63 SOT4 I/O PN0 A SIO output
64 SIN4 I/O PN1 A SIO input
65 SCK4 I/O PN2 A SIO clock
66 SIN3 I/O PN3 A SIO input
67 SOT3 I/O PN4 A SIO output
68 SCK3 I/O PN5 A SIO clock
69 VSS
70 OCPA0 I/O PO0 A PPG output
71 OCPA1 I/O PO1 A PPG output
72 OCPA2 I/O PO2 A PPG output
73 OCPA3 I/O PO3 A PPG output
74 OCPA4 I/O PO4 A PPG output
75 OCPA5 I/O PO5 A PPG output
76 OCPA6 I/O PO6 A PPG output
77 OCPA7 I/O PO7 A PPG output
78 TX0 I/O PP0 Q CAN TX output
79 RX0 I/O PP1 Q CAN RX output
80 TX1 I/O PP2 Q CAN TX output
81 RX1 I/O PP3 Q CAN RX output
82 VDD
83 VSS
84 SIN0 I/O PQ0 A UART input
85 SOT0 I/O PQ1 A UART output
86 SIN1 I/O PQ2 A UART input
87 SOT1 I/O PQ3 A UART output
88 PG0 I/O PG0 A Digital IO-Port
89 PG1 I/O PG1 A Digital IO-Port
90 PG2 I/O PG2 A Digital IO-Port
91 PG3 I/O PG3 A Digital IO-Port
FME / EMDC / Br + ALan - mb91f376s.fm 14 23-Mar-05
 Table 1.5a Pinning

General Circuit
Pin No.
Pin Name I/O Purpose Type Function
QFP120
I/O Port
92 PG4 I/O PG4 A Digital IO-Port
93 PG5 I/O PG5 A Digital IO-Port
94 VDD
95 HVSS SMC VSS
96 PWM1P0 I/O PR0 K SMC 0
97 PWM1M0 I/O PR1 K SMC 0
98 PWM2P0 I/O PR2 K SMC 0
99 PWM2M0 I/O PR3 M SMC 0
100 HVDD SMC VDD
101 PWM1P1 I/O PR4 K SMC 1
102 PWM1M1 I/O PR5 K SMC 1
103 PWM2P1 I/O PR6 K SMC 1
104 PWM2M1 I/O PR7 M SMC 1
105 HVSS SMC VSS
106 PWM1P2 I/O PS0 K SMC 2
107 PWM1M2 I/O PS1 K SMC 2
108 PWM2P2 I/O PS2 K SMC 2
109 PWM2M2 I/O PS3 M SMC 2
110 HVDD SMC VDD
111 PWM1P3 I/O PS4 K SMC 3
112 PWM1M3 I/O PS5 K SMC 3
113 PWM2P3 I/O PS6 K SMC 3
114 PWM2M3 I/O PS7 M SMC 3
115 HVSS
116 VDD
117 PJ0 I/O PJ0 A Digital IO-Port
118 PJ1 I/O PJ1 A Digital IO-Port
119 PJ2 I/O PJ2 A Digital IO-Port
120 PJ3 I/O PJ3 A Digital IO-Port

Remark: Pin 31 (BOOT) should be low by default (pull down resistor).

To avoid disturbances in case of reset/boot it should preferably only be used as output by any application.

FME / EMDC / Br+ALan - mb91f376g.fm 15 23-Mar-05

 Table 1.5b Circuit Types
Circuit
Description
Type
A I/O, IOH=4 mA / IOL=4 mA, CMOS Automotive Hysteresis Input, STOP control
B I/O, IOH=4 mA / IOL=4 mA, CMOS Automotive Hysteresis Input, Analog Input, STOP control
D Analog Input
E CMOS Hysteresis Input, 50K Pull-up
G Tristate Output, IOH=4 mA / IOL=4 mA
H 4 MHz Oscillator Pin
I 32KHz Oscillator Pin
K I/O, IOH=30 mA / IOL=30 mA, CMOS Automotive Hysteresis Input, STOP control, slew rate
improved for EMC (in SMC mode)
M I/O, IOH=30 mA / IOL=30 mA, CMOS Automotive Hysteresis Input, Analog Input, STOP control,
slew rate improved for EMC (in SMC mode)
Q I/O, IOH=4 mA / IOL=4 mA, CMOS Input, STOP control
R AVRH Input
T CMOS Input, can withstand VID for flash programming
U CMOS Hysteresis Input, 50K Pull-up, 3V and 5V input to core
Y I/O, IOH=3mA / IOL=3mA (I2C), CMOS Input, STOP control

FME / EMDC / Br + ALan - mb91f376s.fm 16 23-Mar-05

1.6 Flash Memory Mode of MB91F376GS

To enter the flash memory mode set mode pins MD0 to MD2 to “111”. Assert INITX for at least
500 ns to enter this mode.

The following tables show the pins which are required for the programming procedure and also
describe the states for the pins not used in flash memory mode. Most of the not used pins are
in their reset state (high-Z outputs, enabled inputs). To prevent misbehavior or damage these
pins must be tied to VDD or VSS through resistors - see following tables for details.
Aside from the functional pins described below all power pins should be connected to a power
supply in the specified range, capacitances should be connected to the VCC3C pin as recom-
mended.

Table 1: Flash Control Signals

MB91F376GS
MBM29LV800C Notes
Pin number Normal function Flash Memory mode
31 BOOT WE WE

32 TESTX BYTE BYTE

33 CPUTESTX TMODX pull up

38 MONCLK RY/BY RY/BY

39-46 INT0-INT7 D24 to D31 DQ8 to DQ15

50 IN0 CE CE

51 IN1 OE OE

52 IN2 D20 DQ4

53 IN3 D21 DQ5

54 OUT0 D22 DQ6

55 OUT1 D23 DQ7

57 MD0 VDA9 A9 (VID)

58 MD1 VDRS RESET (VID)

59 MD2 VDOE OE (VID)

60 INITX RESET RESET

91-93 PG3-PG5 A16-A18 A15-A17

88 PG0 A20 pull up

89 PG1 A19 A18

96 PWM1P0 A0 A-1

FME / EMDC / Br+ALan - mb91f376g.fm 17 23-Mar-05

 Table 1: Flash Control Signals

MB91F376GS
MBM29LV800C Notes
Pin number Normal function Flash Memory mode
97 PWM1M0 A1 A0

98 PWM2P0 A2 A1

99 PWM2M0 A3 A2

101 PWM1P1 A4 A3

102 PWM1M1 A5 A4

103 PWM2P1 A6 A5

104 PWM2M1 A7 A6

106 PWM1P2 A8 A7

107 PWM1M2 A9 A8
108 PWM2P2 A10 A9

109 PWM2M2 A11 A10

111 PWM1P3 A12 A11

112 PWM1M3 A13 A12

113 PWM2P3 A14 A13

114 PWM2M3 A15 A14

117 to 120 PJ0-PJ3 D16 to D19 DQ0 to DQ3

Table 2: Pins not used in Flash Memory Mode

MB91F376GS

Pin number Normal function Pin State Notes

35 X0 input pull up

36 X1 output leave open

66 SIN3 output leave open

67 SOT3 output leave open

68 SCK3 output leave open

29 ALARM input pull up

all other signals input pull up

FME / EMDC / Br + ALan - mb91f376s.fm 18 23-Mar-05

CHAPTER 2 IO-Map
see Appendix A.
The addresses shown in this table for CAN registers are based on the settings for CS7 done in the Boot ROM

CHAPTER 3 Interrupt Vector Table

see Appendix B

CHAPTER 4 Power-on-sequence
All VDD pins should be connected to the same potential. The analogue supply voltage (AVCC) must not be turned
on before the digital supply voltage.
Immediately after power on always execute INIT at the INITX pin (input a low level to the INITX pin). Hold this low
level at the INITX pin long enough so that after release of the low level at INITX and the passing of the built in
waiting time stable oscillation of the oscillation circuit is achieved. INITX must be pulled low for at least 8 cycles of
the 4 MHz oscillation clock.

CHAPTER 5 Handling of Unused Input Pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the de-
vice. Therefore they must be tied to VDD or VSS through resistors. In this case those resistors should be more
than 2 KOhm.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
The resistor of more than 2 KOhm is used to limit currents through the protection diodes. In case of voltages at the
unused pin of 0.3 V or more below VSS or 0.3 V or more above VDD currents which could cause latch-up will flow
through those diodes. It is possible to use one resistor to connect several pins to VDD or VSS. Care should be
taken not to connect pins from different supply voltage domains to one resistor.

FME / EMDC / Br+ALan - mb91f376g.fm 19 23-Mar-05

CHAPTER 6 Emulation Device
MB91FV360GA can be used as an emulation device for MB91F376GS. MB91F376GS uses the following
resources of MB91FV360G (see MB91FV360GA IO-Map):

• Reload Timer 0 - Reload Timer 5

• UART 0 / U-Timer 0 - UART 1 / U-Timer 1
• SIO 0 - SIO 1 and their Prescalers; when emulating DMA to/from the SIOs on MB91FV360GA the
restrictions given in DDI3200008 have to be observed
• I2C (100KHz and 400KHz)
• A/D Converter (channels 0 - 7)
• Input Capture 0 - Input Capture 3
• Output Compare 0 - Output Compare 1
• Free Running Counter 0 - Free Running Counter 1
• Stepper Motor Controllers 0 - 3
• Sound Generator
• Real Time Clock
• Programmable Pulse Generators: PWM Control 0 -1, PWM channels 0 - 7
• Power down reset
• Alarm Comparator
• CAN0 - CAN 1
• User RAM 16KB: address range: 03:C000-03:FFFF
• F-Bus RAM 16KB: address range: 04:0000-04:3FFF
• I-RAM 4KB: address range: 01:1000-01:1FFF

The complete size of the flash memory of 768K can only be emulated by using external emulation RAM.

The modified watchdog behaviour - no more clearing of the watchdog reset generation flag in case of DMA to D-
bus and I-Bus, instruction fetch from D-bus RAM and data operations on I-bus RAM - cannot be emulated on
MB91FV360GA.

FME / EMDC / Br + ALan - mb91f376s.fm 20 23-Mar-05

CHAPTER 7 Package
A QFP-120 package called FPT-120P-M21 (0.5 mm pin pitch) will be used for MB91F376GS.
The thermal resistance of this package is 30 degr. C/W when used on a multi-layer board with separate power
and ground planes.

Thermal resistance [degr. C/W]

theta-jc (junction to
theta-ja (junction to ambient)
case)

0 m/s 1 m/s 3 m/s

30 27 25 5

The maximum allowed ambient temperature is 85 degr. C, the maximum allowed junction temperature is 125
degr.C. Under these conditions a maximum power consumption of (125 degr. C - 85 degr. C) / 30 C/W = 1.33 W is
allowed. The user must make sure that the maximum ambient temperature is not exceeded.

For other details about the package see Fujitsu Semiconductor Package Data Book.

FME / EMDC / Br+ALan - mb91f376g.fm 21 23-Mar-05

CHAPTER 8 Electrical specification
See documentation for MB91F376G.

FME / EMDC / Br + ALan - mb91f376s.fm 22 23-Mar-05

Appendix A I/O Map

Table A lists the addresses for the registers used by the internal peripheral functions of
MB91F376GS.

• How to Read the I/O Map

Register
Internal
Address peripheral
+0 +1 +2 +3
000014H PDRG [R/W] PDRH [R/W] PDRI [R/W] Port data
—
XXXXXXXX XXXXXXXX ----XXXX register

Read/write attribute
Register initial value after a reset (bit initial values)
“1”: initial value “1”, “0”: initial value “0”,
“x”: initial value “X” (indeterminate),
“—” indicates non-existent bits
Register name (The register in column 1 is at location 4n, the register in
column 2 at 4n+1, and so on.)
Location of far left of register (+0). +1, +2, and +3 each increment the
location by one. When performing word access, the register in column 1 is
placed at the MSB end of the data.
Precautions:

• Do not use RMW instructions on registers containing write-only (W) bits.

RMW instructions(RMW:read-modify-write)
AND Rj, @Ri OR Rj, @Ri EOR Rj, @Ri
ANDH Rj, @Ri ORH Rj, @Ri EORH Rj, @Ri
ANDB Rj, @Ri ORB Rj, @Ri EORB Rj, @Ri
BANDL #u4, @Ri BORL #u4, @Ri BEORL #u4, @Ri
BANDH #u4, @Ri BORH #u4, @Ri BEORH #u4, @Ri

• The data in reserved areas and areas marked “” is indeterminate. Do not use those areas !

Register
Address Block
+0 +1 +2 +3

000000H Reserved T-unit

Port Data
000004H Reserved Register
000008H Reserved

00000CH Reserved

FME / EMDC / Br+ALan - mb91f376g.fm 23 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

000010H PDRG [R/W] PDRH [R/W] PDRI [R/W] PDRJ [R/W] R-bus
XXXXXXXX XXXXXXXX X---X--- XXXXXXXX Port Data
Register
000014H PDRK [R/W] PDRL [R/W] PDRM [R/W] PDRN [R/W]
XXXXXXXX XXXXXXXX - - - - XXXX - - XXXXXX

000018H PDRO [R/W] PDRP [R/W] PDRQ [R/W] PDRR [R/W]

XXXXXXXX ----XXXX - - XXXXX XXXXXXXX

00001CH PDRS [R/W]

XXXXXXXX

000020H Reserved
|
00003CH

000040H EIRR [R/W] ENIR [R/W] ELVR [R/W] Ext int/NMI

00000000 00000000 00000000 00000000

000044H DICR [R/W] HRCL [R/W] CLKR2 [R/W] reserved DLYI/I-unit

-------0 0 - - 11111 - - - - - - 000 RTC

000048H TMRLR0 [W] TMR0 [R] Reload Timer

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0

00004CH ________ TMCSR0 [R/W]

- - - - 0000 - - - 00000

000050H TMRLR1 [W] TMR1 [R] Reload Timer

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 1

000054H ________ TMCSR1 [R/W]

- - - - 0000 - - - 00000

000058H TMRLR2 [W] TMR2 [R] Reload Timer

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 2

00005CH ________ TMCSR2 [R/W]

- - - - 0000 - - - 00000

000060H SSR0 [R/W] SIDR0 [R/W] SCR0 [R/W] SMR0 [R/W] UART0
00001 - 00 XXXXXXXX 00000100 00 - - 0 - 0 -

000064H ULS0 [R/W]

- - - - 0000

000068H UTIM0/UTIMR0 [R/W] DRCL0 [W] UTIMC0 [R/W] U-TIMER 0

00000000 00000000 -------- 0 - - - 0 - 01

00006CH SSR1 [R/W] SIDR1 [R/W] SCR1 [R/W] SMR1 [R/W] UART1
00001 - 00 XXXXXXXX 00000100 00 - - 0 - 0 -

000070H ULS1 [R/W]

- - - - 0000

000074H UTIM1/UTIMR1 [R/W] DRCL1 [W] UTIMC1 [R/W] U-TIMER 1

00000000 00000000 -------- 0 - - - - - 01

000078H ________ Reserved

00007CH

FME / EMDC / Br + ALan - mb91f376s.fm 24 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

000080H ________ Reserved

000084H SMCS0 [R/W] SIO 0

00000010 - - - - 00-0
SES0 [R/W] SDR0 [R/W]
- - - - - - 00 00000000

000088H SMCS1 [R/W] SES1 [R/W] SDR1 [R/W] SIO 1

00000010 - - - - 00 - 0 - - - - - - 00 00000000

00008CH CDCR0 [R/W] Reserved CDCR1 [R/W] Reserved SIO 0/1

0 - - - 1111 0 - - - 1111 Prescaler

000090H Reserved

000094H IBCR [R/W] IBSR [R] IADR [R/W] ICCR [R/W] I2C (old)
00000000 00000000 -XXXXXXX - - 0XXXXX
-> new I2C
000098H IDAR [R/W] IDBL [R/W] from address
XXXXXXXX -------0 0x184

00009CH ADMD [R/W,W] ADCH [R/W] ADCS [R/W,W] A/D Converter

- - - -0000 00000000 0000 - - 00

0000A0H ADCD [R/W] ADBL [R/W]

000000XX XXXXXXXX -------0

0000A4H reserved

0000A8H

0000ACH IOTDBL0 [R/W] ICS01 [R/W] IOTDBL1 [R/W] ICS23 [R/W] Input Capture
- - - - - 000 00000000 - - - - - 000 00000000 0,1,2,3

0000B0H IPCP0 [R] IPCP1 [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0000B4H IPCP2 [R] IPCP3 [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0000B8H OCS01 [R/W] reserved Output Com-

- - - 0 - - 00 0000 - - 00 pare
0,1
0000BCH OCCP0 [R/W] OCCP1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0000C0H Reserved

0000C4H Reserved

0000C8H TCDT0 [R/W] ________ TCCS0 [R/W] Free Running

XXXXXXXX XXXXXXXX - 0000000 Counter 0 for
ICU/OCU

0000CCH TCDT1 [R/W] ________ TCCS1 [R/W] Free Running

XXXXXXXX XXXXXXXX - 0000000 Counter 1 for
ICU/OCU

0000D0H ZPD0 [R/W,R] PWC0 [R/W] ZPD1 [R/W,R] PWC1 [R/W] SMC 0,1
00000010 - - 000 - - 0 00000010 00000 - - 0
FME / EMDC / Br+ALan - mb91f376g.fm 25 23-Mar-05
 Register
Address Block
+0 +1 +2 +3

0000D4H ZPD2 [R/W,R] PWC2 [R/W] ZPD3 [R/W,R] PWC3 [R/W] SMC 2,3
00000010 - - 000 - - 0 00000010 00000 - - 0

0000D8H PWC20 [R/W] PWC10 [R/W] PWS20 [R/W] PWS10 [R/W] SMC 0
XXXXXXXX XXXXXXXX - 0000000 - - 000000

0000DCH PWC21 [R/W] PWC11 [R/W] PWS21 [R/W] PWS11 [R/W] SMC 1
XXXXXXXX XXXXXXXX - 0000000 - - 000000

0000E0H PWC22 [R/W] PWC12 [R/W] PWS22 [R/W] PWS12 [R/W] SMC 2
XXXXXXXX XXXXXXXX - 0000000 - - 000000

0000E4H PWC23 [R/W] PWC13 [R/W] PWS23 [R/W] PWS13 [R/W] SMC 3
XXXXXXXX XXXXXXXX - 0000000 - - 000000

0000E8H SMDBL0 [R/W] SMDBL1 [R/W] SMDBL2 [R/W] SMDBL3 [R/W] SMC 0,1,2,3
-------0 ------0 -------0 -------0

0000ECH SGDBL [R/W] SGCR [R/W] Sound

-------0 0 - - - - - 00 000 - - 000 generator

0000F0H SGAR [R/W] SGFR [R/W] SGTR [R/W] SGDR [R/W]

00000000 XXXXXXXX XXXXXXXX XXXXXXXX

0000F4H WTDBL [R/W] WTCR [R/W] Real Time

-------0 00000000 000 - 0000 Clock
(Watch Timer)
0000F8H WTBR [R/W]
- - XXXXXX XXXXXXXX XXXXXXXX

0000FCH WTHR [R/W] WTMR [R/W] WTSR [R/W]

- - - 00000 - - 000000 - - 000000

000100H TMRLR3 [W] TMR3 [R] Reload Timer

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 3

000104H ________ TMCSR3 [R/W]

- - - - XX - - - - - XXXXX

000108H TMRLR4 [W] TMR4 [R] Reload Timer

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 4

00010CH ________ TMCSR4 [R/W]

- - - - XX - - - - - XXXXX

000110H TMRLR5 [W] TMR5 [R] Reload Timer

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 5

000114H ________ TMCSR5 [R/W]

- - - - XX - - - - - XXXXX

000118H GCN10 [R/W] PDBL0 [R/W] GCN20 [R/W] PWM Control

00110010 00010000 - - - -0000 - - - - 0000 0

00011CH GCN11 [R/W] PDBL1 [R/W] GCN21 [R/W] PWM Control

00110010 00010000 - - - -0000 - - - - 0000 1

000120H PTMR0 [R] PCSR0 [W] PWM0

11111111 11111111 XXXXXXXX XXXXXXXX

000124H PDUT0 [W] PCNH0 [R/W] PCNL0 [R/W]

XXXXXXXX XXXXXXXX 0000000 - 000000 - 0
FME / EMDC / Br + ALan - mb91f376s.fm 26 23-Mar-05
 Register
Address Block
+0 +1 +2 +3

000128H PTMR1 [R] PCSR1 [W] PWM1

11111111 11111111 XXXXXXXX XXXXXXXX

00012CH PDUT1 [W] PCNH1 [R/W] PCNL1 [R/W]

XXXXXXXX XXXXXXXX 0000000 - 000000 - 0

000130H PTMR2 [R] PCSR2 [W] PWM2

11111111 11111111 XXXXXXXX XXXXXXXX

000134H PDUT2 [W] PCNH2 [R/W] PCNL2 [R/W]

XXXXXXXX XXXXXXXX 0000000 - 000000 - 0

000138H PTMR3 [R] PCSR3 [W] PWM3

11111111 11111111 XXXXXXXX XXXXXXXX

00013CH PDUT3 [W] PCNH3 [R/W] PCNL3 [R/W]

XXXXXXXX XXXXXXXX 0000000 - 000000 - 0

000140H PTMR4 [R] PCSR4 [W] PWM4

11111111 11111111 XXXXXXXX XXXXXXXX

000144H PDUT4 [W] PCNH4 [R/W] PCNL4 [R/W]

XXXXXXXX XXXXXXXX 0000000 - 000000 - 0

000148H PTMR5 [R] PCSR5 [W] PWM5

11111111 11111111 XXXXXXXX XXXXXXXX

00014CH PDUT5 [W] PCNH5 [R/W] PCNL5 [R/W]

XXXXXXXX XXXXXXXX 0000000 - 000000 - 0

000150H PTMR6 [R] PCSR6 [W] PWM6

11111111 11111111 XXXXXXXX XXXXXXXX

000154H PDUT 6 [W] PCNH6 [R/W] PCNL6 [R/W]

XXXXXXXX XXXXXXXX 0000000 - 000000 - 0

000158H PTMR7 [R] PCSR7 [W] PWM7

11111111 11111111 XXXXXXXX XXXXXXXX

00015CH PDUT7 [W] PCNH7 [R/W] PCNL7 [R/W]

XXXXXXXX XXXXXXXX 0000000 - 000000 - 0

000160H Reserved

000164H CMCR [R/W] CMPR [R/W] Clock Modula-

11111111 0000000 ----1001 1---0001 tion

000168H CMLS0 [R/W] CMLS1 [R/W]

01110111 1111111 01110111 1111111

00016CH CMLS2 [R/W] CMLS3 [R/W]

01110111 1111111 01110111 1111111

000170H CMLT0 [R/W] CMLT1 [R/W]

-----100 00000010 11110100 00000010

000174H CMLT2 [R/W] CMLT3 [R/W]

-----100 00000010 -----100 00000010

000178H CMAC [R/W] CMTS [R/W]

11111111 1111111 --000001 01111111

FME / EMDC / Br+ALan - mb91f376g.fm 27 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

00017CH PDRCR [R/W] Power down

- - - - - 000 reset

000180H ACCDBL[R/W] ACSR [R/W] Alarm compa-

-------0 - - - XXX00 rator

000184H IBCR2 [R/W] IBSR2 [R] ITBAH [R/W] ITBAL [R/W] I2C (new)
00000000 00000000 - - - - - - 00 00000000

000188H ITMKH [R/W] ITMKL [R/W] ISMK [R/W] ISBA [R/W]

00 - - - - 11 11111111 01111111 - 0000000 (*) old and
new I2C share
00018CH IDARH [-] IDAR2 [R/W] ICCR2 [R/W] IDBL2(*) [R/W]
this bit!
00000000 00000000 - 0011111 -------0

000190H CUCR [R/W] CUTD [R/W] not available

- - - - - - - - - - - 0 - -00 10000000 00000000 on
MB91F376GS
000194H CUTR1 [R] CUTR2 [R] S
-------- 00000000 00000000 00000000

000198H ----------------
| Reserved
0001F8H

0001FCH F362MD [R/W] F362

00000000 Mode Reg

FME / EMDC / Br + ALan - mb91f376s.fm 28 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

000200H DMACA0 [R/W] DMAC

00000000 0000XXXX XXXXXXXX XXXXXXXX

000204H DMACB0 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000208H DMACA1 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

00020CH DMACB1 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000210H DMACA2 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

000214H DMACB2 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000218H DMACA3 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

00021CH DMACB3 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000220H DMACA4 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

000224H DMACB4 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000228H ________
|
00023CH

000240H DMACR [R/W]

0--00000 -------- -------- --------

000244H ________ Reserved

|
0003ECH

0003F0H BSD0 [W] Bit Search

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Module

0003F4H BSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8H BSDC [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FCH BSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

FME / EMDC / Br+ALan - mb91f376g.fm 29 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

000400H DDRG [R/W] DDRH [R/W] DDRI [R/W] DDRJ [R/W] R-bus
00000000 00000000 ----0--- 00000000 Port Direction
Register
000404H DDRK [R/W] DDRL [R/W] DDRM [R/W] DDRN [R/W]
00000000 00000000 ----0000 --000000

000408H DDRO [R/W] DDRP [R/W] DDRQ [R/W] DDRR [R/W]

00000000 ----0000 --000000 00000000

00040CH DDRS [R/W]

00000000

000410H PFRG [R/W] PFRH [R/W] PFRI [R/W] PFRJ [R/W] R-bus
00000000 00000000 ----0--- 00000000 Port Function
Register
000414H PFRK [R/W] PFRL [R/W] PFRM [R/W] PFRN [R/W]
00000000 00000000 ----0000 --000000

000418H PFRO [R/W] PFRP [R/W] PFRQ [R/W] PFRR [R/W]

00000000 ----0000 --000000 00000000

00041CH PFRS [R/W]

00000000

000420H ________ Reserved

|
00043CH

FME / EMDC / Br + ALan - mb91f376s.fm 30 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

000440H ICR00 [R/W] ICR01 [R/W] ICR02 [R/W] ICR03 [R/W] Interrupt Con-
---11111 ---11111 ---11111 ---11111 trol
unit
000444H ICR04 [R/W] ICR05 [R/W] ICR06 [R/W] ICR07 [R/W]
---11111 ---11111 ---11111 ---11111

000448H ICR08 [R/W] ICR09 [R/W] ICR10 [R/W] ICR11 [R/W]

---11111 ---11111 ---11111 ---11111

00044CH ICR12 [R/W] ICR13 [R/W] ICR14 [R/W] ICR15 [R/W]

---11111 ---11111 ---11111 ---11111

000450H ICR16 [R/W] ICR17 [R/W] ICR18 [R/W] ICR19 [R/W]

---11111 ---11111 ---11111 ---11111

000454H ICR20 [R/W] ICR21 [R/W] ICR22 [R/W] ICR23 [R/W]

---11111 ---11111 ---11111 ---11111

000458H ICR24 [R/W] ICR25 [R/W] ICR26 [R/W] ICR27 [R/W]

---11111 ---11111 ---11111 ---11111

00045CH ICR28 [R/W] ICR29 [R/W] ICR30 [R/W] ICR31 [R/W]

---11111 ---11111 ---11111 ---11111

000460H ICR32 [R/W] ICR33 [R/W] ICR34 [R/W] ICR35 [R/W]

---11111 ---11111 ---11111 ---11111

000464H ICR36 [R/W] ICR37 [R/W] ICR38 [R/W] ICR39 [R/W]

---11111 ---11111 ---11111 ---11111

000468H ICR40 [R/W] ICR41 [R/W] ICR42 [R/W] ICR43 [R/W]

---11111 ---11111 ---11111 ---11111

00046CH ICR44 [R/W] ICR45 [R/W] ICR46 [R/W] ICR47 [R/W]

---11111 ---11111 ---11111 ---11111

000470H ________
|
00047CH

000480H RSRR [R/W] STCR [R/W] TBCR [R/W] CTBR [W] Clock Control
10000-00 00110011 X0000X00 XXXXXXXX unit

000484H CLKR [R/W] WPR [W] DIVR0 [R/W] DIVR1 [R/W]

00000000 XXXXXXXX 00000011 00000000

000488H ________ Reserved

|
00063CH

FME / EMDC / Br+ALan - mb91f376g.fm 31 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

000640H ASR0 [W] AMR0 [W] T-unit

00000000 00000000 11111000 11111111

000644H ASR1 [W] AMR1 [W]

00000000 00000000 00000000 00000000

000648H ASR2 [W] AMR2 [W]

00000000 00000000 00000000 00000000

00064CH ASR3 [W] AMR3 [W]

00000000 00000000 00000000 00000000

000650H ASR4 [W] AMR4 [W]

00000000 00000000 00000000 00000000

000654H ASR5 [W] AMR5 [W]

00000000 00000000 00000000 00000000

000658H ASR6 [W] AMR6 [W]

00000000 00000000 00000000 00000000

00065CH ASR7 [W] AMR7 [W]

00000000 00000000 00000000 00000000

000660H AMD0 [R/W] AMD1 [R/W] AMD2 [R/W] AMD3 [R/W]

-00XX111 -XXXXXXX --XXXXXX --XXXXXX

000664H AMD4 [R/W] AMD5 [R/W] AMD6 [R/W] AMD7 [R/W]

--XXXXXX --XXXXXX -XXXXXXX -XXXXXXX

000668H CSE ________ ________ ________

11000011

00066CH ________ ________

000670H CHE ________ ________

11111111

000674H ________ Reserved

|
0007F8H

0007FCH ________ MODR [W] ________ ________ Mode Regis-

XXXXXXXX ter

000800H ________ Reserved

|
000B6CH

FME / EMDC / Br + ALan - mb91f376s.fm 32 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

001000H DMASA0 [R/W] DMAC

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001004H DMADA0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001008H DMASA1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00100CH DMADA1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001010H DMASA2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001014H DMADA2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001018H DMASA3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00101CH DMADA3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001020H DMASA4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001024H DMADA4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001028H ________ Reserved

|
006FFCH

007000H FMCS [R/W] ________ ________ ________ Flash

0110X000 Memory
Control
007004H FMWT [R/W] ________ ________ ________ Register
-0010011

007008H ________ Reserved

|
010FFCH

011000H ________ I-RAM 4 kB

|
011FFCH

012000H ________ Reserved

|
03BFFCH

03C000H User RAM

| 16 kB
03FFFCH (D-Bus)

040000H Fast RAM

| 16 kB
043FFCH (F-Bus)

FME / EMDC / Br+ALan - mb91f376g.fm 33 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

044000H Boot ROM

| 2 kB
0447FCH (F-Bus)

044800H Sector 0 (partly) Sector 2 (partly) Flash Memory

| 56 KB 56 KB 768 K
05FFFCH
on F-Bus
060000H Sector 1 Sector 3
| 64 KB 64 KB
07FFFCH

080000H Sector 4 Sector 11

| 64 KB 64 KB
09FFFCH

0A0000H Sector 5 Sector 12

| 64 KB 64 KB
0BFFFC

0C0000H Sector 6 Sector 13

| 64 KB 64 KB
0DFFFC

0E0000H Sector 7 Sector 14

| 32 KB 32 KB
0EFFFC

0F0000H Sector 8 Sector 15

| 8 KB 8 KB
0F3FFCH

0F4000H Sector 9 Sector 16

| 8 KB 8 KB
0F7FFCH

0F8000H Sector 10 Sector 17

| 16 KB 16 KB
0FFFFCH
Fixed Mode and Reset Vector

100000H Sector 0 - mirrored Sector 2 - mirrored

| 64 KB 64 KB
11FFFCH

120000H Sector 1 - mirrored Sector 3 - mirrored

| 64 KB 64 KB
13FFFCH

FME / EMDC / Br + ALan - mb91f376s.fm 34 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

200000H BVALR0 [R/W] TREQR0 [R/W] CAN 0

00000000 00000000 00000000 00000000
Remark:
200004H TCANR0 [W] TCR0 [R/W] Address
00000000 00000000 00000000 00000000 range for CAN
0 to CAN 1
200008H RCR0 [R/W] RRTRR0 [R/W]
depends on
00000000 00000000 00000000 00000000
chip select
20000CH ROVRR0 [R/W] RIER0 [R/W] range. Men-
00000000 00000000 00000000 00000000 tioned
addresses are
200010H CSR0 [R/W] LEIR0 [R/W] default val-
00000000 00000001 000-0000 ues, deter-
mined by boot
200014H RTEC0 [R] BTR0 [R/W] ROM con-
00000000 00000000 -1111111 11111111 tents.
200018H IDER0 [R/W] TRTRR0 [R/W]
XXXXXXXX XXXXXXXX 00000000 00000000

20001CH RFWTR0 [R/W] TIER0 [R/W]

XXXXXXXX XXXXXXXX 00000000 00000000

200020H AMSR0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

200024H AMR00 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200028H AMR10 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20002CH GENERAL PURPOSE RAM [R/W]

|
200048H

20004CH IDR00 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200050H IDR10 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200054H IDR20 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200058H IDR30 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20005CH IDR40 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200060H IDR50 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200064H IDR60 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

FME / EMDC / Br+ALan - mb91f376g.fm 35 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

200068H IDR70 [R/W] CAN 0

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20006CH IDR80 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200070H IDR90 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200074H IDR100 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200078H IDR110 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20007CH IDR120 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200080H IDR130 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200084H IDR140 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200088H IDR150 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20008CH DLCR00 [R/W] DLCR10 [R/W]

-------- ----XXXX -------- ----XXXX

200090H DLCR20 [R/W] DLCR30 [R/W]

-------- ----XXXX -------- ----XXXX

200094H DLCR40 [R/W] DLCR50 [R/W]

-------- ----XXXX -------- ----XXXX

200098H DLCR60 [R/W] DLCR70 [R/W]

-------- ----XXXX -------- ----XXXX

20009CH DLCR80 [R/W] DLCR90 [R/W]

-------- ----XXXX -------- ----XXXX

2000A0H DLCR100 [R/W] DLCR110 [R/W]

-------- ----XXXX -------- ----XXXX

2000A4H DLCR120 [R/W] DLCR130 [R/W]

-------- ----XXXX -------- ----XXXX

2000A8H DLCR140 [R/W] DLCR150 [R/W]

-------- ----XXXX -------- ----XXXX

2000ACH DTR00 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000B4H DTR10 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

FME / EMDC / Br + ALan - mb91f376s.fm 36 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

2000BCH DTR20 [R/W] CAN 0

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000C4H DTR30 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000CCH DTR40 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000D4H DTR50 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000DCH DTR60 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000E4H DTR70 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000ECH DTR80 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000F4H DTR90 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2000FCH DTR100 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

200104H DTR110 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

20010CH DTR120 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

200114H DTR130 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

20011CH DTR140 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

200124H DTR150 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

20012CH CREG0 [R/W]

00000000 00000110

FME / EMDC / Br+ALan - mb91f376g.fm 37 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

200200H BVALR1 [R/W] TREQR1 [R/W] CAN 1

00000000 00000000 00000000 00000000
Remark:
200204H TCANR1 [W] TCR1 [R/W] Address
00000000 00000000 00000000 00000000 range for CAN
0 to CAN 1
200208H RCR1 [R/W] RRTRR1 [R/W]
depends on
00000000 00000000 00000000 00000000
chip select
20020CH ROVRR1 [R/W] RIER1 [R/W] range. Men-
00000000 00000000 00000000 00000000 tioned
addresses are
200210H CSR1 [R/W] LEIR1 [R/W] default val-
00000000 00000001 000-0000 ues, deter-
mined by boot
200214H RTEC1 [R] BTR1 [R/W] ROM con-
00000000 00000000 -1111111 11111111 tents.
200218H IDER1 [R/W] TRTRR1 [R/W]
XXXXXXXX XXXXXXXX 00000000 00000000

20021CH RFWTR1 [R/W] TIER1 [R/W]

XXXXXXXX XXXXXXXX 00000000 00000000

200220H AMSR1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

200224H AMR01 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200228H AMR11 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20022CH GENERAL PURPOSE RAM [R/W]

|
200248H

20024CH IDR01 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200250H IDR11 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200254H IDR21[R/W]
XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200258H IDR31 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX-

20025CH IDR41 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200260H IDR51 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200264H IDR61 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

FME / EMDC / Br + ALan - mb91f376s.fm 38 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

200268H IDR71 [R/W] CAN 1

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20026CH IDR81 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200270H IDR91 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200274H IDR101 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200278H IDR111 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20027CH IDR121 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXX---

200280H IDR131 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200284H IDR141 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

200288H IDR151 [R/W]

XXXXXXXX XXXXXXXX XXXXX--- XXXXXXXX

20028CH DLCR01 [R/W] DLCR11 [R/W]

-------- ----XXXX -------- ----XXXX

200290H DLCR21 [R/W] DLCR31 [R/W]

-------- ----XXXX -------- ----XXXX

200294H DLCR41 [R/W] DLCR51 [R/W]

-------- ----XXXX -------- ----XXXX

200298H DLCR61 [R/W] DLCR71 [R/W]

-------- ----XXXX -------- ----XXXX

20029CH DLCR81[R/W] DLCR91 [R/W]

-------- ----XXXX -------- ----XXXX

2002A0H DLCR101 [R/W] DLCR111 [R/W]

-------- ----XXXX -------- ----XXXX

2002A4H DLCR121 [R/W] DLCR131 [R/W]

-------- ----XXXX -------- ----XXXX

2002A8H DLCR141 [R/W] DLCR151 [R/W]

-------- ----XXXX -------- ----XXXX

2002ACH DTR01 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002B4H DTR11 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

FME / EMDC / Br+ALan - mb91f376g.fm 39 23-Mar-05

 Register
Address Block
+0 +1 +2 +3

2002BCH DTR21 [R/W] CAN 1

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002C4H DTR31 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002CCH DTR41 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002D4H DTR51 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002DCH DTR61 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002E4H DTR71 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002ECH DTR81 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002F4H DTR91 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

2002FCH DTR101 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

200304H DTR111 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

20030CH DTR121 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

200314H DTR131 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

20031CH DTR141 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

200324H DTR151 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

20032CH CREG1 [R/W]

00000000 00000110

FME / EMDC / Br + ALan - mb91f376s.fm 40 23-Mar-05

Appendix B Interrupt Vectors

This appendix lists the interrupt vector table.

The interrupt vector table lists the interrupt vectors and interrupt control registers
assigned to each MB91360 interrupt.

Interrupt number Interrupt level*1 Interrupt vector*2

Interrupt Hexa- Setting Register Default Vector
Decimal Offset RN
decimal Register address address

Reset *6 0 00 - - 0x3FC 0x000FFFFC

Mode vector *6 1 01 - - 0x3F8 0x000FFFF8

System reserved 2 02 - - 0x3F4 0x000FFFF4

System reserved 3 03 - - 0x3F0 0x000FFFF0

System reserved 4 04 - - 0x3EC 0x000FFFEC

System reserved 5 05 - - 0x3E8 0x000FFFE8

System reserved 6 06 - - 0x3E4 0x000FFFE4

Co-processor
7 07 - - 0x3E0 0x000FFFE0
fault trap *4

Co-processor
8 08 - - 0x3DC 0x000FFFDC
error trap *4

INTE instruction *4 9 09 - - 0x3D8 0x000FFFD8

Instruction break
10 0A - - 0x3D4 0x000FFFD4
exception *4

Operand break trap *4 11 0B - - 0x3D0 0x000FFFD0

Step trace trap *4 12 0C - - 0x3CC 0x000FFFCC

NMI interrupt(tool)*4 13 0D - - 0x3C8 0x000FFFC8

Undefined instruction
14 0E - - 0x3C4 0x000FFFC4
exception

NMI request 15 0F FH fixed 0x3C0 0x000FFFC0

External Interrupt 0 16 10 ICR00 0x440 0x3BC 0x000FFFBC 4

External Interrupt 1 17 11 ICR01 0x441 0x3B8 0x000FFFB8 5

External Interrupt 2 18 12 ICR02 0x442 0x3B4 0x000FFFB4 8

External Interrupt 3 19 13 ICR03 0x443 0x3B0 0x000FFFB0 9

External Interrupt 4 20 14 ICR04 0x444 0x3AC 0x000FFFAC

External Interrupt 5 21 15 ICR05 0x445 0x3A8 0x000FFFA8

External Interrupt 6 22 16 ICR06 0x446 0x3A4 0x000FFFA4

FME / EMDC / Br+ALan - mb91f376g.fm 41 23-Mar-05

 External Interrupt 7 23 17 ICR07 0x447 0x3A0 0x000FFFA0

Reload Timer 0 24 18 ICR08 0x448 0x39C 0x000FFF9C 6

Reload Timer 1 25 19 ICR09 0x449 0x398 0x000FFF98 7

Reload Timer 2 26 1A ICR10 0x44A 0x394 0x000FFF94

CAN 0 RX 27 1B ICR11 0x44B 0x390 0x000FFF90

CAN 0 TX/NS 28 1C ICR12 0x44C 0x38C 0x000FFF8C

CAN 1 RX 29 1D ICR13 0x44D 0x388 0x000FFF88

CAN 1 TX/NS 30 1E ICR14 0x44E 0x384 0x000FFF84

CAN 2 RX *7 31 1F ICR15 0x44F 0x380 0x000FFF80

CAN 2 TX/NS *7 32 20 ICR16 0x450 0x37C 0x000FFF7C

CAN 3 RX 5 33 21 ICR17 0x451 0x378 0x000FFF78

CAN 3 TX/NS 5 34 22 ICR18 0x452 0x374 0x000FFF74

PPG 0/1 35 23 ICR19 0x453 0x370 0x000FFF70

PPG 2/3 36 24 ICR20 0x454 0x36C 0x000FFF6C

PPG 4/5 37 25 ICR21 0x455 0x368 0x000FFF68

PPG 6/7 38 26 ICR22 0x456 0x364 0x000FFF64

Reload Timer 3 39 27 ICR23 0x457 0x360 0x000FFF60

Reload Timer 4 40 28 ICR24 0x458 0x35C 0x000FFF5C

Reload Timer 5 41 29 ICR25 0x459 0x358 0x000FFF58

ICU 0/1 42 2A ICR26 0x45A 0x354 0x000FFF54

OCU 0/1 43 2B ICR27 0x45B 0x350 0x000FFF50

ICU 2/3 44 2C ICR28 0x45C 0x34C 0x000FFF4C

OCU 2/3 *7 45 2D ICR29 0x45D 0x348 0x000FFF48

ADC 46 2E ICR30 0x45E 0x344 0x000FFF44 14

Timebase Overflow 47 2F ICR31 0x45F 0x340 0x000FFF40

Free Running
48 30 ICR32 0x460 0x33C 0x000FFF3C
Counter 0

Free Running
49 31 ICR33 0x461 0x338 0x000FFF38
Counter 1

SIO 0 50 32 ICR34 0x462 0x334 0x000FFF34 12

SIO 1 51 33 ICR35 0x463 0x330 0x000FFF30 15

Sound Generator 52 34 ICR36 0x464 0x32C 0x000FFF2C

UART 0 RX 53 35 ICR37 0x465 0x328 0x000FFF28 0

UART 0 TX 54 36 ICR38 0x466 0x324 0x000FFF24 1

UART 1 RX 55 37 ICR39 0x467 0x320 0x000FFF20 2

UART 1 TX 56 38 ICR40 0x468 0x31C 0x000FFF1C 3

FME / EMDC / Br + ALan - mb91f376s.fm 42 23-Mar-05

 UART 2 RX *7 57 39 ICR41 0x469 0x318 0x000FFF18 10

UART 2 TX *7 58 3A ICR42 0x46A 0x314 0x000FFF14 11

I2C 59 3B ICR43 0x46B 0x310 0x000FFF10 13

Alarm Comparator 60 3C ICR44 0x46C 0x30C 0x000FFF0C

RTC / Calibration
61 3D ICR45 0x46D 0x308 0x000FFF08
(Watch timer)

DMA 62 3E ICR46 0x46E 0x304 0x000FFF04

Delayed interrupt
63 3F ICR47 0x46F 0x300 0x000FFF00
activation bit

System reserved *3 64 40 - - 0x2FC 0x000FFEFC

System reserved *3 65 41 - - 0x2F8 0x000FFEF8

Security vector 66 42 0x2F4 0x000FFEF4

System reserved 67 43 (ICR51) 0x473 0x2F0 0x000FFEF0

System reserved 68 44 (ICR52) 0x474 0x2EC 0x000FFEEC

System reserved 69 45 (ICR53) 0x475 0x2E8 0x000FFEE8

System reserved 70 46 (ICR54) 0x476 0x2E4 0x000FFEE4

System reserved 71 47 (ICR55) 0x477 0x2E0 0x000FFEE0

System reserved 72 48 (ICR56) 0x478 0x2DC 0x000FFEDC

System reserved 73 49 (ICR57) 0x479 0x2D8 0x000FFED8

System reserved 74 4A (ICR58) 0x47A 0x2D4 0x000FFED4

System reserved 75 4B (ICR59) 0x47B 0x2D0 0x000FFED0

System reserved 76 4C (ICR60) 0x47C 0x2CC 0x000FFECC

System reserved 77 4D (ICR61) 0x47D 0x2C8 0x000FFEC8

System reserved 78 4E (ICR62) 0x47E 0x2C4 0x000FFEC4

System reserved 79 4F (ICR63) 0x47F 0x2C0 0x000FFEC0

80 50 0x2BC 0x000FFEBC
Used by the INT
to to - - to to
instruction.
255 FF 0x000 0x000FFC00

*1 The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is
provided for each interrupt request.
*2 The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table

base register value (TBR). The TBR specifies the top of the EIT vector table. The addresses listed in the table are
for the default TBR value (0x000FFC00). The TBR is initialized to this value by a reset.After execution of the inter-
nal boot ROM TBR is set to 0x00FFC00.
*3 Used by REALOS

*4 System reserved

*5 Only available on MB91V360/MB91FV360

*6 Mode and reset vector cannot be changed, for their contents see IO map

*7 Not available on MB91F376GS

FME / EMDC / Br+ALan - mb91f376g.fm 43 23-Mar-05

 Remarks:
The 1-Kbyte area from the address specified in TBR is the EIT vector area.
Each vector consists of four bytes. The following formula shows the relationship between the
vector number and vector address.
vctadr=TBR + vctofs

= TBR + (3FCH – 4 × vct)

vctadr:Vector address
vctofs:Vector offset
vct:Vector number

FME / EMDC / Br + ALan - mb91f376s.fm 44 23-Mar-05