Skill Development Course
Department of Electronics and Communication Engineering
II B.Tech – II Sem
VLSI Laboratory
(Using Tanner Tools )
UNIVERSITY COLLEGE OF ENGINEERING
ADIKAVI NANNAYA UNIVERSITY
Rajamahendravaram, East Godavari District, A.P - 533296
LIST OF EXPERIMENTS
1. Design & Implementation of CMOS Inverter using Tanner
2. Design & Implementation of AND and OR Logic Gates using Tanner
3. Design & Implementation of CMOS NAND and NOR Gate using Tanner
4. Design & Implementation of CMOS NOR Gate using Tanner
5. Design & Implementation of Half Adder and Full Adder using Tanner
6. Design & Implementation of Half Subtractor and Full Subtractor using Tanner
7. Design & Implementation of Differential Amplifier using Tanner
Tanner Tools
Steps to use Tanner tool:
i. SCHEMATIC (S-edit):
Start the tanner EDA by using the desktop shortcut or by using the
Start Programs tanner EDA tanner tool v13.0 S-edit.
[Type text]
[Type text]
[Type text]
[Type text]
iii) Layout (L-edit):
Start Programs tanner EDA tanner tool v13.0 L-edit
SCHEMATIC DIAGRAM:
Exp. No.: 1
DESIGN OF CMOS INVERTER USING TANNER
AIM
To design a CMOS inverter using the Schematic entry tool, Tanner and
verify its functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
CMOS Inverter consists of nMOS and pMOS transistor in series connected between
VDD and GND. The gate of the two transistors are shorted and connected to the input. When
the input to the inverter A = 0, nMOS transistor is OFF and pMOS transistor is ON. The
output is pull-up to VDD. When the input A = 1, nMOS transistor is ON and pMOS transistor
is OFF. The Output is Pull-down to GND.
ALGORITHM
1. Draw the schematic of CMOS Inverter using S-edit.
2. Perform Transient Analysis of the CMOS Inverter.
3. Obtain the output waveform from W-edit.
4. Obtain the spice code using T-edit.
Procedure:
Open S-Edit window.
Go to File New New design
Go to Cell New View
Add libraries file to the New Cell.
Instance the devices by using appropriate library files.
Save the design and setup the simulation.
Run design and observe waveforms.
Observe DC inputs and outputs by giving appropriate inputs.
CMOS Inverter
]
WAVEFORM
Transient Analysis
Dc analysis
OUTPUT
\
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "C:\Tanner\S-Edit\Module011.sp"
Including "C:\Tanner\TSpice70\models\ml2_125.md"
Device and node counts:
MOSFETs - 2 BJTs - 0 MESFETs - 0 Capacitors - Inductors - 0
MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0
Voltage sources - 2
VCVS - 0
CCVS - 0
V-control switch - 0
Macro devices - 0
Subcircuits - 0
Independent nodes - 1
Total nodes - 4
Current sources - 0
VCCS - 0
CCCS - 0
I- control switch - 0
Functional model instances - 0
Subcircuit instances - 0
Boundary nodes - 3
Parsing 0.01 seconds
Setup 0.00 seconds
DC operating point 0.00 seconds
Transient Analysis 0.04 seconds
Total 0.05 seconds
RESULT
Thus the design & simulation of a CMOS inverter has been carried out using S-Edit of
Tanner EDA Tools
Exp. No.: 2
DESIGN OF AND and OR GATES USING TANNER
THEORY:
AND GATE:
The AND gate performs logical multiplication which is most commonly known as the
AND junction. The operation of AND gate is such that the output is high only when
all its inputs are high and when any one of the inputs is low the output is low.
Y=a&b
OR GATE:
The OR gate performs logical addition which is most commonly known as the OR
junction. The operation of OR gate is such that the output is high only when any one
of its input is high and when both the inputs are low the output is low.
Y=a|b
AND Gate:
Truth table:
AND Gate
-
Input1 Input2 Output
-
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate:
Truth table:
OR Gate
-
Input1 Input2 Output
-
0 0 0
0 1 1
1 0 1
1 1 1
- -
Procedure:
Open S-Edit window.
Go to File New New design
Go to Cell New View
Add libraries file to the New Cell.
Instance the devices by using appropriate library files.
Save the design and setup the simulation.
Run design and observe waveforms.
Observe DC inputs and outputs by giving appropriate inputs.
OR Gate Circuit Diagram:
OR Gate Output wave:
AND Gate Circuit Diagram:
AND Gate Output wave:
RESULT
Thus the design & simulation of a CMOS OR and AND gates has been carried out using
S-Edit ofTanner EDA Tools
Exp. No.: 3
DESIGN OF CMOS NAND GATE USINGTANNER
AIM
To design a CMOS NAND gate using the Schematic entry tool, Tanner and verify
its functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
NAND gate are known as universal gates as any function can be implemented with
them
NAND functionality can be implemented by parallel combination of PMOS and series
combination of NMOS transistor. When any one of the inputs is zero, then the output will be
one and when both the inputs are one the output will be low.
ALGORITHM
CMOS NAND
1. Draw the schematic of CMOS NAND using S-edit.
2. Perform Transient Analysis of the CMOS NAND.
3. Obtain the output waveform from W-edit.
4. Obtain the spice code using T-edit.
Procedure:
Open S-Edit window.
Go to File New New design
Go to Cell New View
Add libraries file to the New Cell.
Instance the devices by using appropriate library files.
Save the design and setup the simulation.
Run design and observe waveforms.
Observe DC inputs and outputs by giving appropriate inputs.
CMOS NAND Ciruit:
WAVEFORM NAND
OUTPUT - NAND
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "F:\tanner\TSpice70\Module0.sp"
Including "F:\tanner\S-Edit\models\ml2_125.md"
Warning T-SPICE : DC sources have non-unique names. "vin".
Device and node counts:
MOSFETs - 4 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 3 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V- control switch - 0 I-control switch - 0
Macro devices - 0 Functional model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 2 Boundary nodes - 4
Total nodes - 6
*** 1 WARNING MESSAGES GENERATED
Parsing 0.00 seconds
Setup 0.00 seconds
DC operating point 0.01 seconds
Transient Analysis 0.03 seconds
-----------------------------------------
Total 0.04 seconds
Exp. No.: 4
DESIGN OF CMOS NOR GATE USINGTANNER
AIM
To design a CMOS NOR gate using the Schematic entry tool, Tannerand verify its
functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
NOR functionality can be implemented by parallel combination of NMOS and series
combination of PMOS transistor. When any one of the inputs is one, then the output will be
one and when both the inputs are zero the output will be low.
CMOS NOR
1. Draw the schematic of CMOS NOR using S-edit.
2. Perform Transient Analysis of the CMOS NOR.
3. Obtain the output waveform from W-edit.
4. Obtain the spice code using T-edit.
Procedure:
Open S-Edit window.
Go to File New New design
Go to Cell New View
Add libraries file to the New Cell.
Instance the devices by using appropriate library files.
Save the design and setup the simulation.
Run design and observe waveforms.
Observe DC inputs and outputs by giving appropriate inputs.
CMOS NOR Circuit
WAVEFORM NOR
OUTPUT – NOR
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "F:\tanner\TSpice70\Module0.sp"
Including "F:\tanner\S-Edit\models\ml2_125.md"
Warning T-SPICE : DC sources have non-unique names. "vin".
Device and node counts:
MOSFETs - 4 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 3 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V- control switch - 0 I-control switch - 0
Macro devices - 0 Functional model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 3 Boundary nodes - 4
Total nodes - 7
*** 1 WARNING MESSAGES GENERATED
Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.
Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been
exceeded.
Warning T-SPICE : The vrange voltage range limit should be set to at least 7.11984 for best
accuracy and performance.
Parsing 0.00 seconds
Setup 0.01 seconds
DC operating point 0.00 seconds
Transient Analysis 0.06 seconds
Total 0.07 seconds
RESULT
Thus the design & simulation of a CMOS NAND and NOR gates have been carried
out using S-Edit of Tanner EDA Tools
Exp. No.: 5 DESIGN OF CMOS DIFFERENTIAL AMPLIFIER USING
TANNER
AIM
To design a CMOS Differential Amplifier using the Schematic entry tool, Tanner
and verify its functioning.
APPARATUS REQUIRED:
1. Tanner tool
2. PC
THEORY:
A differential amplifier is a type of electronic amplifier that multiplies the difference
between two inputs by some constant factor (the differential gain). Many electronic
devices use differential amplifiers internally. The output of an ideal differential
amplifier is given by:
Where Vin+ and Vin- are the input voltages and Ac is the differential gain. In
practice, however, the gain is not quite equal for the two inputs. This means that if
Vin+ and Vin-are equal, the output will not be zero, as it would be in the ideal case. A
more realistic expression for the output of a differential amplifier thus includes a
second term.
Ac is called the common-mode gain of the amplifier. As differential amplifiers are
often used when it is desired to null out noise or bias-voltages that appear at both
inputs, a low common-mode gain is usually considered good.
The common-mode rejection ratio, usually defined as the ratio between differential-
mode gain and common-mode gain, indicates the ability of the amplifier to accurately
cancel voltages that are common to both inputs. Common-mode rejection ratio
(CMRR):
ALGORITHM
Draw the schematic of CMOS differential amplifier using S-edit.
Perform Transient Analysis of the CMOS Inverter.
Obtain the output waveform from W-edit.
Obtain the spice code using T-edit.
DIFFERENTIAL AMPLIFIER CIRCUIT:
WAVEFORM:
OUTPUT
TSPICE - Tanner SPICE
Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "C:\Tanner\S-Edit\Module0.sp"
Including "C:\Tanner\TSpice70\models\ml2_125.md"
Device and node counts:
MOSFETs - 5 BJTs - 0 MESFETs - 0 Capacitors - 0 Inductors - 0
MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 4
VCVS - 0
CCVS - 0
V-control switch - 0
Macro devices - 0
Subcircuits - 0
Independent nodes - 4
Total nodes - 9
Current sources - 0
VCCS - 0
CCCS - 0
I-control switch - 0
Functional model instances - 0
Subcircuit instances - 0
Boundary nodes - 5
Parsing 0.00 seconds
Setup 0.01 seconds
DC operating point 0.01 seconds
Transient Analysis 0.07 seconds
Total 0.09 seconds
RESULT
The design and simulation of Differential Amplifier has been performed using
Tanner EDA Tools.
Exp. No.: 6
DESIGN & ANALYSIS OF Half Adders
using Tanner
HALF ADDER
Aim:
a) To construct the Half Adder in Tanner EDA v13.1 and to do the Transient Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.
Tools used:
Tanner Tools v13.1
Schematic-Edit
Layout -Edit
Wave- Edit
Tanner Spice
Procedure:
Open S-Edit window.
Go to File New New design
Go to Cell New View
Add libraries file to the New Cell.
Instance the devices by using appropriate library files.
Save the design and setup the simulation.
Run design and observe waveforms.
Observe DC inputs and outputs by giving appropriate inputs.
Schematic Diagram:
Fig (a): Half Adder Schematic
Tanner Spice Code:
* SPICE export by: SEDIT 13.12
* Export time: Fri Apr 16 11:24:00 2010
* Design: adm705-1
* Cell: Cell2
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Documents and Settings\Administrator\Desktop\adm705-1
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools
v13.1\Libraries\Models\Generic_025.lib" TT
*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 --------
* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 --------
MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
.ends
.subckt NAND2C A B Out1 Out2 Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 --------
* Design: LogicGates / Cell: NAND2C / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NAND with complementary output.
* Date: 6/14/2007 1:47:11 AM
* Revision: 2
*-------- Devices: SPICE.ORDER > 0 --------
MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt XNOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 --------
* Design: LogicGates / Cell: XNOR2 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NOR
* Date: 7/18/2008 3:58:48 AM
* Revision: 4
*-------- Devices: SPICE.ORDER > 0 --------
MM3n 1 A 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM10n Out 1 5 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM9n 5 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM8n Out 1 4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM7n 4 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM4n 2 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM5p 3 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MM11p Out 1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM2p 1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MM1p 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
MM6p Out A 3 Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u
.ends
.subckt XOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 --------
* Design: LogicGates / Cell: XOR2 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NOR
* Date: 7/18/2008 1:30:51 AM
* Revision: 3
*-------- Devices: SPICE.ORDER == 0 --------
XXinv N_1 Out Gnd Vdd INV
XXxnor A B N_1 Gnd Vdd XNOR2
.ends
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 --------
XINV_1 N_1 carry Gnd Vdd INV
XNAND2C_1 In1 In2 N_1 N_2 Gnd Vdd NAND2C
XXOR2_1 In1 In2 sum Gnd Vdd XOR2
*-------- Devices: SPICE.ORDER > 0 --------
VVoltageSource_3 Vdd Gnd DC 5
VVoltageSource_1 In1 Gnd PULSE(0 5 0 5n 5n 50n 100n)
VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 25n 50n)
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(carry)
.PRINT TRAN V(sum)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVoltageSource_1 0 5 0.5 sweep lin source VVoltageSource_2 0 5 0.5
.print dc v(XINV_1,GND)
.print dc v(XXOR2_1,GND)
********* Simulation Settings - Additional SPICE commands *********
.end
Output responses:
Result:
The Half Adder is constructed in Tanner EDA v13.1, the spice code is generated and wave forms
are verified.
