20/07/2018 Vlsi Physical Design - - Unit 11 - Week 10
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Unit 11 - Week 10
Course
outline Week 10 Assignment
The due date for submitting this assignment has passed. Due on 2018-04-04, 23:59 IST.
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the portal Submitted assignment
Week 1 1) The necessary condition to detect a stuck-at fault in a circuit is: 1 point
The fault-free and faulty logic values at the site of the fault must be different.
Week 2
The fault-free and faulty logic values at the primary output(s) must be different.
Week 3 The fault-free and faulty logic values at the site of the faulr must be same.
None of the above.
Week 4
No, the answer is incorrect.
Week 5 Score: 0
Accepted Answers:
Week 6 The fault-free and faulty logic values at the site of the fault must be different.
The fault-free and faulty logic values at the primary output(s) must be different.
Week 7
2) The Boolean difference of a function F = A'B + B'C + C' with respect to the variable B is given 1 point
Week 8 by:
A’C
Week 9
AC
Week 10 A+C
A’ + C
Lecture 53 Test
Pattern No, the answer is incorrect.
Generation Score: 0
Lecture 54 Accepted Answers:
Design for AC
Testability
3) During the forward drive phase of the path sensitization method of test generation: 1 point
Lecture 55
Boundary Scan
Any change at the site of the fault is propagated to the output.
Standard
For all gates that lie from the site of the fault to the primary output, controlling values are applied
Lecture 56
to the side inputs.
Built-in Self-Test
(Part 1) A path is sensitized that propagates the effect of the fault.
All of the above.
Lecture 57
Built-in Self-Test No, the answer is incorrect.
(Part 2)
Score: 0
Week 10 Accepted Answers:
Lecture Material
Any change at the site of the fault is propagated to the output.
Feedback for A path is sensitized that propagates the effect of the fault.
week 10
4) Which of the following statement is true for the scan path DFT technique? 1 point
Quiz : Week 10
Assignment The test generation problem is reduced to that for a combinational circuit.
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20/07/2018 Vlsi Physical Design - - Unit 11 - Week 10
Lecture 53: Special shift register test sequences are applied to test faults in the scan flip-flops.
Note
The fanout of a scan flip-flop is same as that of a normal flip-flop in the original non-scan
Lecture 54: version of the circuit.
Note None of the above.
Lecture 55:
No, the answer is incorrect.
Note
Score: 0
Lecture 56:
Accepted Answers:
Note
The test generation problem is reduced to that for a combinational circuit.
Lecture 57: Special shift register test sequences are applied to test faults in the scan flip-flops.
Note
5) In a scan path design there are 250 scan flip-flops that are connected in a scan chain. For 1 point
Week 10
applying 5000 combinational test vectors, how many clock cycles will be required?
Assignment
Solution
About 1 million
Week 11 About 1.25 million
About 1.5 million
Week 12: About 2 million
DOWNLOAD No, the answer is incorrect.
VIDEOS Score: 0
Accepted Answers:
Supplementary About 1.25 million
Demo Tutorials
6) The INTEST mode of the IEEE 1149.1 standard is used to: 1 point
Test the internal logic circuits of a chip.
Test the boundary scan cells of the wrapper.
Test the interconnections among the chips.
None of the above.
No, the answer is incorrect.
Score: 0
Accepted Answers:
Test the internal logic circuits of a chip.
7) The BYPASS mode of the IEEE 1149.1 standard is used to: 1 point
Skip a test vector and move on to the next vector.
Bypass a chip and feed the serial data to the next chip in sequence.
Identify chips that do not require any testing.
None of the above.
No, the answer is incorrect.
Score: 0
Accepted Answers:
Bypass a chip and feed the serial data to the next chip in sequence.
8) For a 10-bit LFSR generating an m-sequence, which of the following statements are true? 1 point
The number of distinct patterns that can be generated is 1023.
The number of distinct patterns that can be generated is 1024.
The all-zero pattern is also generated in the sequence.
The all-one pattern is also generated in the sequence.
No, the answer is incorrect.
Score: 0
Accepted Answers:
The number of distinct patterns that can be generated is 1023.
The all-one pattern is also generated in the sequence.
9) For which of the following test strategies, we can carry out testing at the rated clock 1 point
frequency of the chip?
Scan based testing
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20/07/2018 Vlsi Physical Design - - Unit 11 - Week 10
Built-in self-test
Exhaustive testing
None of the above.
No, the answer is incorrect.
Score: 0
Accepted Answers:
Built-in self-test
10)For a 16-bit LFSR compacting a 10,000-bit serial bit pattern, the probability of aliasing is 1 point
approximately given by:
1 / 216
16 / 10000
1 / 210000
None of the above.
No, the answer is incorrect.
Score: 0
Accepted Answers:
1 / 216
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