Lecture 6

P&R

ITERATIONS

Import

Floorplanning (Part 2 of 4) Floorplan

VLSI Physical Design Fundamentals Course Place

CTS

Phil Hoang Route

Tresemi Export
Introduction

FP

ITERATIONS

INPUTS Define
Chip
Size
§ Design Netlist Import OUTPUTS
§ Physical Constraints Place IO
Cells
§ Die/Block Area Defined
− Area § I/O Cells Placed
− I/O Placement Place
− Macro Placement Macros § Macros Placed
§ Timing Constraints § Standard Cell Placement
Define
SC Areas
Areas Defined
§ Power Requirements § Power Grid Built
Create
Power
Grid
§ Custom Pre-Route
Created
Pre-route
Special
Nets

© Tresemi 2024 VLSI Physical Design Fundamentals p.2

Macro Placement Overview

Macro placement involves determining optimal positions for large functional blocks (macros)
within the chip layout to achieve the best possible PPA.
🎯 Goals:
§ Optimize Area Utilization
− Place macros to minimize white space and ensure a compact layout.
§ Minimize Wire Lengths
− Reduce interconnect delays and dynamic power by shortening signal paths.
§ Facilitate Routing
− Avoid congestion by maintaining proper spacing and structured placement.
§ Shorten Timing-Critical Paths
− Improve timing closure by minimizing delay on critical nets.
§ Reduce Switching Power
− Lower dynamic power by keeping frequently toggling blocks close.
§ Mitigate EMIR Risks
− Prevent hot spots and ensure uniform current distribution for IR drop and electromigration resilience.

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.3

Learning Objectives

§ By the end of this lecture, participants will be able to: FP

− Explain the purpose and impact of macro placement in physical design.
− Describe key factors influencing macro placement, including timing, ITERATIONS

congestion, and power delivery. Define

PnR
Boundary
− Apply industry best practices to place macros effectively in a chip layout. Place IO
Pads
(Pins)

Place
Macros

Define
SC Areas

Create
Power
Grid

Pre-route
Special
Nets

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.4

Key Influencing Factors

1. Timing Closure
2. Power Consumption
3. System Interface
4. Clock Distribution
5. Routing Congestion
6. Power Delivery & EM/Thermal

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.5

1. Timing Closure Impact on Macro Placement

§ Why It Matters:
− Timing closure is one of the hardest goals in physical design.
− Macro placement can make or break critical path delays.
§ Best Practices:
− Group related macros to minimize cross-region delays.
− Favor timing-critical data paths when placing macros.
− Avoid placing macros on opposite ends of the core if they communicate frequently.
§ Common Pitfalls:
− Ignoring data flow direction; placing timing-critical macros too far apart
• Long wiring delays making it difficult to close timing
− Neglecting clock distribution needs
• Clock sink macros placed far from clock source or buffer regions lead to excessive clock skew,
latency
− Failing to reserve routing resources near critical macros
• Leads to late-stage congestion and detoured routes, impacting setup/hold timing.

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.6

2. Power Consumption Impact on Macro Placement

§ Why It Matters:
− Frequently switching macros consume significant dynamic power.
− Long, high-activity interconnects waste energy and contribute to overall power inefficiency.
§ Best Practices:
− Place macros that communicate frequently near each other
→ Reduces switching currents on long nets and saves dynamic power.
− Align macro placement with the direction of data flow
→ Prevents unnecessary detours and long toggling paths.
§ Common Pitfalls:
− Spreading high-activity macros too far apart
→ leads to excessive dynamic power consumption.
− Misaligned data paths
→ Placing macros in a way that forces signals to take zig-zag or looped paths increases switching net
capacitances and therefore power.
− Neglecting macro toggle rate differences
→ Treating all macros equally can lead to inefficient placement — high-toggle blocks need more careful
placement than low-activity ones.

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.7

3. System Interface Impact on Macro Placement

§ Why It Matters:
− Interface-related macros need to connect cleanly to the outside
world or specific on-chip blocks.
− Poor placement can lead to long routes, noise issues, or
integration challenges.
§ Best Practices:
− Place macros near related IO pads or interface logic
→ e.g., position flash memory close to its IO controller.
− Keep sensitive analog/RF macros away from noisy digital or IO
regions Sensitive
Analog
→ Reduces risk of noise coupling and ensures reliable operation.
§ Common Pitfalls: Isolation Ring

− Placing interface macros far from IO → creates long, Noisy IO

congested, delay-prone connections. Pads Noisy
− Ignoring isolation needs of sensitive blocks → can lead to Digital

functional or signal integrity failures.

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.8

4. Clock Distribution Impact on Macro Placement

§ Why It Matters: Clock

PLL
Gen
− Macros with clocked interfaces (e.g., CLK
SRAMs) need well-balanced clock tree
paths. CPU

− Poor macro placement can lead to

excessive skew, high insertion delay.
§ Best Practices: Bad SRAM

− Place clocked macros near the core clock

distribution network
Clock

PLL
→ Reduces clock skew and makes CTS (Clock Gen
Tree Synthesis) easier. CLK

§ Common Pitfalls: SRAM CPU

− Isolated placement of clocked macros

→ Causes long clock routes, skew, and insertion
delay. ü Good

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.9

5. Routing Congestion Impact on Macro Placement

§ Why It Matters:
− Macros block routing resources above them — placing them too close can choke routing
channels.
− Congestion leads to longer detoured routes, increased delays, and possible routing failures.
§ Best Practices:
− Leave adequate spacing between macros
→ Allows room for signal, clock, and power routing.
− Spread out macros with high pin density
→ Reduces the chance of localized congestion.
− Use early congestion analysis (trial routing or congestion maps)
→ Helps identify potential hotspots and adjust macro positions before detailed placement.
§ Common Pitfalls:
− Macros placed too tightly → insufficient space for signal and clock routes.
− High-pin macros clustered in one region → creates dense local congestion.
− Blocking main routing channels with large macros → leads to routing detours and timing issues.

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.10

6. Power Delivery & EM/Thermal Impact

§ Why It Matters:
− Macros draw significant current and must connect efficiently to the power grid.
− Poor placement can lead to IR drop, electromigration (EM) failures, and thermal hotspots.
− High-power macros clustered together raise local power density and temperature.
§ Best Practices:
− Place high-power macros near robust power grid regions
→ Reduces local IR drop and ensures current delivery.
− Spread out macros with heavy current demand
→ Avoids hotspots and minimizes EM stress on shared power lines.
− Leave room for power straps and tap cells
→ Supports proper current distribution and local decoupling capacitance cell insertion.
§ Common Pitfalls:
− Clustering power-hungry macros → leads to localized IR drop and thermal issues.
− Placing macros far from power sources → causes voltage droop and EM violations.

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.11

Summary

Defined Placed Placed Ready for

FP Estimated
Chip Width the IO the Defining SC
Die Size
& Height Pads Macros Areas
ITERATIONS

Define
PnR
Boundary

Place IO
Pads
(Pins)

Place
Macros

Define
SC Areas

Create
Power
Grid

Pre-route
Special
Nets

© Tresemi 2024 VLSI Physical Design Fundamentals p.12

More Information...

1. Congestion
2. Macro Placement Guidelines
3. Floorplanning Strategies for Macro Dominating Blocks
4. Machine-Learning PPA Optimization

More references for Lecture 05:

1. What is Floorplanning
2. Utilization & Aspect Ratio

© Tresemi 2024 VLSI Physical Design Fundamentals p.13

References

§ CMOS VLSI Design – Weste-Harris § From Logic to Layout – Rob Rutenbar

§ Digital Integrated Circuits – Jan Rabaey § asic back-end - https://usebackend.wordpress.com
§ 2011 Lecture Notes - David Money Harris § System-on-Chip Design – Anand Raghunathan
§ Digital VLSI Design – Adam Teman § Physical Design Flow – Mohammad Kakoee
§ Principles of VLSI Design – Jim Plusquellic § Team VLSI Blog – “teamvlsi.com”
§ Digital Integrated Circuits – YuZhuo Fu § Cadence Online Support Site and YouTube Videos
§ VLSI Back-End Adventure, ASIC Blog – “SoC Physical § A Staggered CUP IO Methodology Using Encounter
Design” Platform – Pickesh Shah, et al.
§ VLSI Physical Design For Fresher – “physicaldesign4u.com” § Reliability of segmented edge seal ring for RF devices - J.
Gambino, et al.
§ VLSI Begin… Blog - “vlsibegin.blogspot.com”
§ A Reliable I/O Ring For A Reliable SoC – Abdelliah Bakhali
§ SoC Physical Design – “physicaldesign-asic.blogspot.com”
§ Apply Wire bonding PBGA or Flip Chip PBGA? - Fiona
§ VLSI Expert – “vlsiexpert.com” Zhang
§ ASIC-System on Chip-VLSI Design – “asic-soc.blogspot.com” § Floorplan Strategies for Macro Dominating Blocks – Team
§ Physical Design Concepts – VLSI
”physicaldesignconcepts.blogspot.com” § Floorplan Guidelines for Sub-Micron Technology Node for
Networking Chips - Dhaval S. Shukla
§ Internet search and many more…

© Tresemi 2024 VLSI Physical Design Fundamentals p.14

 Backup

© Tresemi 2024 VLSI Physical Design Fundamentals p.16

Data Path Optimization
XRAM YRAM

PLL
Macro Placement Guidelines:
Review the data flow diagram or a

CROM
high-level design description from
the chip designer
Core Area

Important for PPA PRAM

FFT operation (Multiply-Accumulate with Coefficients) on Data An example of macro placement

from XRAM and YRAM and Coefficients from CROM.
XRAM/YRAM, CROM and PRAM(Program RAM) are placed of a DSP Chip
closed to each other for speed and power.

• Reducing wirelength • Less delay

on timing critical • Less cell area needed for
paths and frequently timing fixes
switching signals • Less switching power

ü Better Performance (P)

ü Lower Power (P)
ü Less Area (A)

© Tresemi 2024 VLSI Physical Design Fundamentals p.17

Macro Placement For Better QoR
Large and contiguous
standard cell placement areas

• Better congestion control

• More routing & placement
resources Pins facing each other to
minimize routing
• Less delay
• Less cell area needed for timing fixes
• Less power
Most pins interact with Shorter
Wires
the standard cells – Have
ü Better Performance (P)
them face the SC areas
ü Lower Power (P)
ü Less Area (A)
Pins away from
corners
Leave room for routing & cell placement
through the macro stack
• Less delay
• Less cell area
ü Better Performance (P)
• Long Wires can be buffered needed for
ü Lower Power (P)
• More routing options timing fixes
ü Less Area (A)
• Less wiring detours • Less power

• Less Delay ü Better Performance (P)

© Tresemi 2024 VLSI Physical Design Fundamentals p.18

Macro Placement For Routability

Leave room for routing through

the macro stack

Avoid notch
Avoid chimneys, narrow formation (high
placement areas, (no wire density)
cell placement area,
high wire density)
High wire density =
congestion
problems

© Tresemi 2024 VLSI Physical Design Fundamentals p.19

Macro Orientation & Placement Blockages

Analyze connectivity for best macro’s orientation

• Pin facing outward if they are not connected. For non-pin sides of
• Pins facing each other if they are connected macros a minimal
(minimize signal lengths) separation is adequate.

Add placement blockages, halos to

manage local congestion

Allow only buffers or

set a low max
utilization in
There should be space
planned for VDD/VSS tapping chimneys

© Tresemi 2024 VLSI Physical Design Fundamentals p.20

Macro Placement Guidelines (3)

Add
placement Sometimes
blockages, Macro Keep-out just a corner
halos blockage is
needed

Flight-line
Analysis to
analyze
connectivity
and
minimize
routing

© Tresemi 2024 VLSI Physical Design Fundamentals p.21

Macro Placement Guidelines (4)

Poly Layer’s Orientation

In advanced technology
nodes, the macro’s
orientation is fixed since
the Poly layer’s
orientation can’t vary.
Use flight lines and
place the macros
based on connectivity

FIXED

“FIX” the macro locations

VLSI Back-End Adventure after done with placement,
so that the tool won’t
move them during
Avoid crisscross optimization (standard
connectivity between macros cells are moved by the
tool during optimization)

© Tresemi 2024 VLSI Physical Design Fundamentals p.22

Placement Blockages

§ Halo
Halos– blocks placement around
Placement Blockage Types: macros
§ Hard - blocks placement in this − Fixed blockage sizes
area. − Associated with specific macros
§ Partial - allows placement to − Halo blockages moved with macro
certain maximum utilization (for movements.
example 50%) in this area.
§ Soft - only allows certain cells
such as buffers, inverters, clock
gaters, etc. in this area.
§ Macro-only – blocks placement of
macros in this area

© Tresemi 2024 VLSI Physical Design Fundamentals p.23

Routing Blockages

Congestion can be
managed either by or by routing
placement blockages blockages

Routing blockages prevent

routing in an area for specified
layer(s)

© Tresemi 2024 VLSI Physical Design Fundamentals p.24

Macro Placement For Power Distribution

There should be space

Source: Adam Teman planned for VDD/VSS tapping

Place blocks with the highest performance

and highest power consumptions:
• near the power pads (IR Drop) and
• away from each other (EM)

© Tresemi 2024 VLSI Physical Design Fundamentals p.25