Lecture 4

Design Import
VLSI Physical Design Fundamentals Course

Phil Hoang
Tresemi
Import
Physical Library
P&R Logical/Timing Library
Gate Netlist
SC.lef Macro.lef Pad.lef
ITERATIONS SC.lib Macro.lib Pad.lib

Import

P&R Tech File

Floorplan
Timing
Constraints
Place
MMMC/SDC

CTS Interconnect
Technology Files
Physical
Route
Constraints,
including die size
Export
and IO Placement
File
Read and check Inputs are valid Design is ready for
quality of inputs Constraints are accurate & complete Floorplanning

© Tresemi 2024 VLSI Physical Design Fundamentals p.2

Netlist Import

▪ Netlist is at gate level

− Building blocks are leaf cells
Import
and macros
Gate Netlist − What is a leaf cell?
− What is a macro?
Cell
Abstracts
▪ File format is Verilog VHDL
Timing
Constraints
− What are the other formats?
− Where does the netlist come
Logic
Physical
Constraints from?
Synthesis
▪ Imported by a single tool
command
Innovus
− What is the name of the tool
that we are using for this step?
− What is the name of the read_netlist
command?

© Tresemi 2024 VLSI Physical Design Fundamentals p.3

Cell Abstracts Import

▪ Cells in P&R Standard Cells,

Memories, Other IPs
− What are “cells” in P&R?
Import

Gate Netlist
▪ File format is LEF
OA, Milkyway
− What are the other formats?
− Where do the abstracts come
Cell
Abstracts IP Download
from? or Abstract
Timing Generation
▪ Imported by a single
Constraints

Physical
Constraints
command File
− What is the name of this
command for the Cadence read_physical
tool?

© Tresemi 2024 VLSI Physical Design Fundamentals p.4

 Import

Gate Netlist

Cell
Abstracts

Timing
Constraints

Physical
Constraints

Timing Constraints Import

© Tresemi 2024 VLSI Physical Design Fundamentals p.5

Library Sets

▪ One library set for each

PVT Corner
Import
− What are the main Timing Models
Gate Netlist
components?
Cell
− What are some of the typical
Abstracts
PVTs?
Timing
Constraints

Physical
Constraints

Nslow Pslow Vmin Tmax

Nfast Pfast Vmax Tmin
Ntypical Ptypical Vnom Tnom

© Tresemi 2024 VLSI Physical Design Fundamentals p.6

Constraint Modes

▪ Defining Chip Operating Functional, Scan,

Test, etc.
Modes
Import
− What are a few example Delay Constraints
Gate Netlist
constraint modes? (SDC)

Cell
− What are the main
Abstracts
components?
Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Fundamentals p.7

RC Corners

▪ Defining Parasitics rc_max 125C,

Corners rc_min -40C
Import
− What are a few example RC Extraction
Gate Netlist
constraint modes? Tech Files

Cell
− What are the main
Abstracts
components?
Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Fundamentals p.8

Delay Corners

▪ Delay Corner = Library

Set + RC Corner
Import
− What are a few example
Gate Netlist
delay corners?
Cell
− What are the main
Abstracts
components?
Timing
Constraints
Slow Transistors, Hot, Max RCs
Physical Fast Transistors, Cold, Min RCs
Constraints

Just “create_delay_corner”
commands in MMC File

© Tresemi 2024 VLSI Physical Design Fundamentals p.9

Analysis Views

▪ Analysis View = Delay Max Delay, Functional Mode

Corner + Constraint Mode Min Delay, Scan Mode
Import
− What are a few example
Gate Netlist
analysis views?
− What are the main Nothing
Cell
Just “create_analysis_view” and
Abstracts
components? “set_analysis_view” commands in MMC File
Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Fundamentals p.10

 Import

Gate Netlist

Cell
Abstracts

Timing
Constraints

Physical
Constraints

End of Timing Constraints Import

© Tresemi 2024 VLSI Physical Design Fundamentals p.11

Physical Constraints Import

▪ Create Power/Ground
Net names
(iopad
Import − Connect all cells to the (top

Gate Netlist
appropriate power and (inst name=“ringinst/pad100mii1_mdc” place_status=placed )
(inst name=“ringinst/pad100mii1_txd_0” place_status=placed )
ground nets ...
(left
Cell
Abstracts ▪ Create I/O Pad (inst name=“ringinst/pad195ide_dmack_n” place_status=placed )
(inst name=“ringinst/pad196ide_iordy” place_status=placed )
Timing
placement file ...
(bottom
− DATA/asic_entity.io
Constraints
(inst name=“ringinst/pad284em_d1_2” place_status=placed )
(inst name=“ringinst/pad284em_d1_1” place_status=placed )
Physical
Constraints ...
(right
(inst name=“ringinst/pad55em_a_10” place_status=placed )
(inst name=“ringinst/pad55em_a_9” place_status=placed )
...

asic_entity.io

© Tresemi 2024 VLSI Physical Design Fundamentals p.12

 Quality of Inputs Checking

© Tresemi 2024 VLSI Physical Design Fundamentals p.13

Quality of Inputs Checks

▪ Any errors in P&R log file?

▪ Does the netlist compile correctly?
− Are all instances unique?
− Any empty module in the input netlist? They will
create black boxes
▪ Are Timing Constraints Correct and
Complete?
− Are false paths, multi-cycle paths accurate?
− Any sink points with no clocks?
− Any unconstrained endpoints?
− Any dropped constraints?
− Any missing I/O constraints?
▪ Timing Sanity Checks
− Does the design meet timing with zero RC
delays?

© Tresemi 2024 VLSI Physical Design Fundamentals p.14

Import Summary
Read and check
quality of inputs
P&R

ITERATIONS

Import Import

Floorplan
Floorplanning

Place

CTS

Route
Inputs are valid
Constraints are accurate & complete
Export

NO YES
Ready for
Floorplanning?
Design is ready for Floorplanning

© Tresemi 2024 VLSI Physical Design Fundamentals p.15

 Appendix

© Tresemi 2024 VLSI Physical Design Fundamentals p.16

Inputs to Back-End Design
Front-End Design
Foundry
Spec
Device Models
Architecture
P&R Tech Files
RTL
Design Rules

Back-End Design IP Design

External IP Vendors Memory Instances

Synthesis
Standard Cell Libraries
Hard IPs

I/O Cell Libraries

Soft IPs
P&R
Memory Compilers

Hard IPs
Sign-off
Soft IPs

© Tresemi 2024 VLSI Physical Design Fundamentals p.17

Place and Route (P&R) Flow
• Read and check Import DB • Inputs are valid
Gate Level
Import quality of inputs • Constraints are complete
Netlist
• Design is routable
• Define Boundaries • IR drop is below limits
Cell Abstracts • Set up placement • Timing closure is feasible
areas for different
Floorplanning Floorplan DB
types of components
Timing • Create the Power • Design is routable
Constraints Distribution Structures • No timing violations
• Power consumption is minimized
Physical
Constraints
Placement • Place all components Placement DB • Clock trees are optimized
for timing and power
Inputs
Clock Tree Synthesis • Build the clock trees CTS DB • Design is free of design
rule errors
Routing • Route all signals Route DB • No timing violations
• IR drop is below limits
• Power is within budget
Gate Level Netlist • Design is reliable
• Design is manufacturable
Layout
Export • Write outputs
QOR Reports • Design is ready for
FAB
verification and then
Steps Outputs on to Manufacturing

© Tresemi 2024 VLSI Physical Design Fundamentals p.18

Gate-Level Netlist
Manually Generated Constraints
create_clock –period 10 ... Gate-level Netlist is a textual description of a design circuit
module control … set_input_delay –max 1.2 ... • Functionally equivalent to RTL
input A, B, C; set_output_delay –max 2.5 ... • Described in Verilog HDL
output reg X; set_load 0.25 ...
… .....
if (A) This design abstraction
X = B | C; represents a design that
else module control … meets timing constraints with:
X = B &C; input A, B, C; • Ideal clocks
output reg X;
P&R …
• Estimated clock skews
Inputs and2 U1 (.I0(B), .I1(C), .Z(T1); • Estimated wire parasitics
or2 U2 (.I0(B), .I1(C), .Z(T2);
Gate-level
RTL Code Synthesis mux2 U3 (.S(A), .I1(T1), .I2(T2) .Z(X);
Netlist (Verilog) (Genus)
Gate-Level Netlist Structured
Technology (Verilog)
Files

IP Models

Timing Translation Mapping &

Constraints
Optimizatoin
Generic Boolean
Physical
Constraints Mapped to target technology
Logic Synthesis Optimized for timing, power, and area

© Tresemi 2024 VLSI Physical Design Fundamentals p.19

Leaf Cells & Macros

LEAF CELLS MACROS

▪ The basic building blocks or primitive cells used in the ▪ A higher-level building block or
design of integrated circuits. functional unit that is more
− These cells are the fundamental components from which more complex complex than a basic leaf cell or
circuits are constructed. standard cell.
− Leaf cells are also known as standard cells. − Macros are typically larger and can
represent more sophisticated functions,
▪ Leaf cells are pre-designed and characterized functional such as memory blocks, arithmetic
units that perform specific logic functions, such as gates, units, or even entire subsystems.
flip-flops, latches, and other elementary operations. ▪ Are macros considered leaf cells?
− They are created and optimized for a specific semiconductor technology − No. While leaf cells are the smallest
and process node. building blocks in a standard cell library
▪ Standard cell libraries consist of a set of these leaf cells, and and represent basic logic functions like
gates and flip-flops, macros are larger
designers use them to assemble more complex digital and may encapsulate multiple leaf cells
circuits on a chip. or even custom-designed components.
− The use of standard cells allows for a more efficient design process, as − Macros can be seen as higher-level
designers can focus on the higher-level functionality of a circuit without abstractions that simplify the design
having to recreate every basic logic function from scratch. process by providing pre-designed and
pre-verified functional units.
▪ Leaf cells are typically characterized in terms of their area,
power consumption, and delay,
− The design process involves selecting and connecting these cells in a way
that meets the overall performance and power requirements of the target
application.

© Tresemi 2024 VLSI Physical Design Fundamentals p.20

Import
read_netlist Physical Library read_physical
P&R Logical/Timing Library
Gate Netlist
SC.lef Macro.lef Pad.lef
ITERATIONS SC.lib Macro.lib Pad.lib

Import

P&R Tech File

Floorplan read_mmmc
Timing
Constraints
Place
MMMC/SDC

CTS Interconnect
Technology Files
Physical
Route
Constraints,
including die size
Export
and IO Placement
File
Read and check Inputs are valid Design is ready for
quality of inputs Constraints are complete Floorplanning

© Tresemi 2024 VLSI Physical Design Fundamentals p.21

Physical Abstraction

P&R SITE core

Inputs SIZE 0.140 BY 0.900 ; PIN VSS
SYMMETRY Y ; DIRECTION INOUT ;
CLASS CORE ; USE GROUND ;
Gate-level END core SHAPE ABUTMENT ;
Netlist PORT
MACRO NAND_1 LAYER M1 ;
CLASS CORE ; RECT 0.095 -0.075 0.280 0.075 ;
FOREIGN AN2D0BWP30P140 0.000 0.000 ; RECT 0.045 -0.075 0.095 0.200 ;
Technology ORIGIN 0.000 0.000 ; RECT 0.000 -0.075 0.045 0.075 ;
Files SIZE 0.560 BY 0.900 ; END
SYMMETRY X Y ; END VSS
SITE core ;
PIN VDD
IP Models PIN Y DIRECTION INOUT ;
ANTENNADIFFAREA 0.026350 ; USE POWER ;
DIRECTION OUTPUT ; SHAPE ABUTMENT ;
USE SIGNAL ; PORT LAYER M1 ;
Timing Physical Abstraction PORT RECT 0.095 0.825 0.280 0.975 ;
Constraints LAYER M1 ; RECT 0.045 0.685 0.095 0.975 ;
- Representation of layout
RECT 0.485 0.125 0.535 0.755 ; RECT 0.000 0.825 0.045 0.975 ;
for P&R purpose RECT 0.465 0.125 0.485 0.335 ; END
- Only metals are used in RECT 0.465 0.545 0.485 0.755 ; END VDD
Physical
Constraints P&R therefore the abstracts END
END Y OBS
only contain metals. The LAYER CO ;
rest of the layers are RECT 0.190 0.130 0.230 0.170 ;
PIN A
“hidden” ANTENNAGATEAREA 0.009300 ; RECT 0.190 0.715 0.230 0.755 ;
DIRECTION INPUT ; RECT 0.115 0.410 0.155 0.450 ;
USE SIGNAL ; RECT 0.050 0.125 0.090 0.165 ;
PORT RECT 0.050 0.720 0.090 0.760 ;
LAYER M1 ; END
Abstract RECT 0.095 0.320 0.155 0.555 ;
Generator END END NAND_1
(Abstract) END A

... Cell Abtract

(LEF)

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.22

MMMC Examples

create_library_set -name ls_ssh –timing [list libs/lib/sc_ssg0p81v125c.lib libs/mem_ssg0p81v125c.lib]

create_library_set -name ls_ffh –timing [list libs/lib/sc_ffg0p99v125c.lib libs/mem_ffg0p99v125c.lib]

create_constraint_mode -name cm_func -sdc_files func.sdc

create_constraint_mode -name cm_test -sdc_files test.sdc

create_rc_corner -name rc_max -qrc_tech ~/rcworst/qrcTechFile -temperature 125

create_rc_corner -name rc_min -qrc_tech ~/rcbest/qrcTechFile -temperature -40

create_delay_corner -name dc_max –library_set ls_ssh –rc_corner rc_max

create_delay_corner -name dc_min –library_set ls_ffh –rc_corner rc_min

create_analysis_view -name av_func_max –delay_corner dc_max –constraint_mode cm_func

create_analysis_view -name av_test_min –delay_corner dc_min –constraint_mode cm_test

set_analysis_view -setup [list av_func_max] -hold [list av_test_min]

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.23

SDC

Synopsys Delay Constraints

Standard Delay Constraints

YouTube Link

YouTube Link

Part II

© Tresemi 2024 VLSI Physical Design Fundamentals p.24

Interconnect Technology File

P&R
Inputs
▪ The RC tech file provides resistance and capacitance tables used
Gate-level
Netlist for RC extraction for a specific process corner.
Technology
Files

qrcTechFile_rcworst
qrcTechFile_rcbest
IP Models qrcTechFile_typical
...

Timing
Techgen
RCX Tech Files
Constraints
(binary)
Physical
Fabrication
RC
Constraints P&R
(Innovus) Extraction
Interconnect Technology Files (QRC)
(.ICT)

RC’s RC’s
(SPEF) (SPEF)

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.25

Chip Physical Constraints

P&R
Inputs
▪ Chip x and y dimensions
Gate-level
Netlist
▪ Locations of the I/O pads.

Technology
Files

IP Models
Y

Timing
Constraints

Physical
Constraints

Timing
constraints were
X
covered in L2

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.26

Block Physical Constraints

P&R
Inputs
▪ PR boundary
Gate-level
Netlist
▪ Pin locations

Technology
Files

IP Models

Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.27

Timing Paths

Delays

Timing
Constraints

© Tresemi 2024 VLSI Physical Design Fundamentals p.28

Timing Slacks

Delays

Timing
Constraints

Timing
Analysis

© Tresemi 2024 VLSI Physical Design Fundamentals p.29

Timing Reports Header

Delays

Timing
Constraints

Timing
Analysis

© Tresemi 2024 VLSI Physical Design Fundamentals p.30

Timing Path

Delays

Timing
Constraints

Timing
Analysis

© Tresemi 2024 VLSI Physical Design Fundamentals p.31

References

▪ CMOS VLSI Design – Weste-Harris ▪ asic back-end - https://usebackend.wordpress.com

▪ Digital Integrated Circuits – Jan Rabaey ▪ System-on-Chip Design – Anand Raghunathan
▪ 2011 Lecture Notes - David Money Harris ▪ Physical Design Flow – Mohammad Kakoee
▪ Digital VLSI Design – Adam Teman ▪ Team VLSI Blog – “teamvlsi.com”
▪ Principles of VLSI Design – Jim Plusquellic ▪ Cadence Online Support Site and YouTube Videos
▪ Digital Integrated Circuits – YuZhuo Fu ▪ Reliability of segmented edge seal ring for RF devices
- J. Gambino, et al.
▪ VLSI Back-End Adventure, ASIC Blog – “SoC
Physical Design” ▪ A Reliable I/O Ring For A Reliable SoC – Abdelliah
Bakhali
▪ VLSI Physical Design For Fresher –
“physicaldesign4u.com” ▪ Apply Wire bonding PBGA or Flip Chip PBGA? -
Fiona Zhang
▪ VLSI Begin… Blog - “vlsibegin.blogspot.com”
▪ Floorplan Strategies for Macro Dominating Blocks –
▪ SoC Physical Design – “physicaldesign- Team VLSI
asic.blogspot.com”
▪ Floorplan Guidelines for Sub-Micron Technology
▪ VLSI Expert – “vlsiexpert.com” Node for Networking Chips - Dhaval S. Shukla
▪ ASIC-System on Chip-VLSI Design – “asic- ▪ Internet search and many more…
soc.blogspot.com”
▪ From Logic to Layout – Rob Rutenbar

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.32