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UEC750

The document outlines the examination paper for the BE (Semester VI) End Semester Examination in MOS Circuit Design at Thapar Institute of Engineering and Technology. It includes various questions related to CMOS circuit design, such as patterning SiO2 layers, implementing Boolean functions, deriving expressions for CMOS inverters, and analyzing NMOS transistors. The paper consists of eight questions, each requiring detailed explanations, calculations, and diagrams.

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Ehab Zaidi
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29 views1 page

UEC750

The document outlines the examination paper for the BE (Semester VI) End Semester Examination in MOS Circuit Design at Thapar Institute of Engineering and Technology. It includes various questions related to CMOS circuit design, such as patterning SiO2 layers, implementing Boolean functions, deriving expressions for CMOS inverters, and analyzing NMOS transistors. The paper consists of eight questions, each requiring detailed explanations, calculations, and diagrams.

Uploaded by

Ehab Zaidi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Roll Number:

Thapar Institute of Engineering and Technology, Patiala


Electronics and Communication Engineering Department
BE (Semester VI) End Semester Examination UEC750: MOS Circuit Design
May, 2023 Name of Faculty: Dr. Arun Kumar Chatterjee,
Time: 03 Hours; Dr. Sujit Kumar Patel, Dr. Anil Singh,
MM: 40 Dr.Rajneesh Sharma
Note: Attempt all questions. Assume any missing data appropriately, if required.

. What are the steps required to pattern the SiO2 layer over the p-substrate? Describe all 151
the steps with help of neat and clean diagrams.
Q2. Implement the following function at CMOS level such that ABCD exists as a one of the 151
common Euler's path for the function. Draw the stick diagram using ABCD as a Euler's
path. Use the stick diagram colour coding scheme while drawing the same.

Y(A,B,C,D) = (A + B + C). D
Q3. For a CMOS inverter, derive an expression for Vii (Maximum input voltage that will be 151
. recognized as a low input logic level) as a function of its output.

Q4. Consider a CMOS inverter with the following parameters: 151

Vio.n = 0.5 V 1.inCos = 98 pA/V2 (W/1.),, = 20


V io.p = - 0.48 V ppC',,,.= 46 µA/V2 (W/I.)p = 30

The power supply voltage is 1.2 V and the output load capacitance is 10 IF. Calculate
the rise time of the output signal using average current method.

Q5. Implement the following Boolean expression in CMOS logic style using only 5 NMOS 151
and 5 PMOS transistors:
F(A,B,C) = (A. B + B. C + C. A)
Also calculate the switching threshold voltage of this circuit ignoring the short channel
effects and using the equivalent CMOS inverter circuit approach.

Q6. Draw and discuss the energy band diagrams for MOS structure with p-substrate in
accumulation, depletion and inversion operating regions. 151

Q7. For NMOS transistor, draw the low-frequency small-signal model and calculate the 151
values of it's parameters. The transistor biasing condition is: V Ds = 4.5V ,VGs =
2.7V and VsB = OV . Use 120!I = 0.45V, y = 0.2 V1/ 2, A = 0.01 V -1, kr, = 0.04
mA/V2 and Vt0,,, = 0.7V.

Q8. Derive an expression for small-signal voltage-gain (A,,) of common source amplifier 151
with resistive load. Determine the numerical value of A, if the device current ID =
35o2 A, y
235pA, RL = 6E1, g m = = 0 V1/2, A = 0.012 V.

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