LABORATORY MANUAL
DIT UNIVERSITY
oIT
VERSITY EXPERIMENT TITILE:
EXPERIMENT NO: 8
PRATICAL INSTRUCION SHEET NANDNOR gates.
Design and test of an S R Nip Nop using
ISSUE NO.:1
ISSUE DATE: 24/06/2022
REV N0.:0
REV. DATE: PAGE:Page I of3
EECE
LABORATORY:Digital System Design SEMESTER:II
OBJECTIVE: Design and lest of an SRIlip lop using NAND NOR gates
EOUIPMENT & COMPONENTS REQUIRED:
S.NO. Equipment OR
DC Power SupplyComponents
(5V)
Multimeter
Bread Board
7400 1C
7402 IC
7
Connecting Wires &LED's
THEORY:
The SR flip-flop is one of the fundamental parts of the sequential circuit logic. SR flip-tlop IS a
memory device and a binary data ofl- bit can be stored in it. SR flip-flop has two stable states in Wnien t
can store data in the form of either binary zero or binary one. Like all
flip-flops, an SR flip-flop IS aso a
edge sensitive device. SR flip-flop is one of the most vital
components in digital logic and t IS aso e
most basic sequential circuit that is possible. The S and R in SR flip-flop means SET and
RESEI
respectively. Hence it is also called Set-Reset flipflop, The symbolic representation of the SR Fip Flor is
shown below.
Set Pin S Output
Reset Inverted
R
Pin
Output
Clock
Fig. I -Block Diagram of S-R flip flop.
LABONATOKY MANUAL.
plT
NERSITY EXPERMENT
DIT UNIVERSITY
PRATICAL INSTRUCTION SHEET
Designand test of an SR lip lop using
NAND/NOR gates.
EXPERIMENT NO:TITILE:
ISSUE DATE: 24/06/2022
REV NO0.:0 8 ISSUE NO.:1
PAGE: Page 2 of 3
: EECE REV. DATE: SEMESTER: II
LABORATORV: Digital System Design
Working rinciple:
R lip-lop works during the transition of clock pulse either from lowto high or from high to low
(depending on the design) i.e. it can be either positive edge triggered or negative edge triggered.
for apositive edge triggered SR flip-flop. Suppose, ifsinput is at high level (logic1) and Rinput is at low
level (logie 0) during alowto high transition on clock pulse, then the SR flip-flop is saidto be in SET state
and the output of the SR flip-flop is SET to I. For the same clock situation, if the Rinput is at high level
(logic 1) and S input is at low level c 0), then the SR flip-flop is said to be in
RESET state and the
(logic
output of the SR flip-flop is RESET to 0.
The SR lip-flops can be designed by using logic gates like NOR gates and NAND gates.
S-R Flip-Flop Using NAND Gate
SR flip flop can be designed by cross oftwo NAND gates.
coupling in below
ve loW input SR flip-flop. The circuit of SR lip-flop using NAND gates is shown
figure:2.
2
7400
7400
CLOE
1
1
2
7400
7400
Fig. 2- S-R flip flop using NANDgates.
SR Flip lop Truth table
|NPUT OUTPUT
S R Q Q^
() ()
)
()
DTIIVRSIY
Aeious tute
Tg RSMptop using NOR ges
PROCTDRE:
Connections are given as per crcuit diagram.
2.
Logical inputs are given as per circuit
J. Obsene the output and verify the truth diagram.
table.
RESULT: Design of S-R Flip flop using NAND &NOR gates was veritied successfully
PRECAUTIONS:
1.
Connections should be
made properly and verify before starting the experiments.
2. Power supply should not be
more than +ZV DC.
J. 1C and other components should be handled
carefully on breadboard I set up.
