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Pre & Post 5

The document outlines Lab #5 focused on the analysis and design of latches and flip-flops, detailing the characteristic equations and excitation tables for SR latches, D-flip-flops, and JK flip-flops. It includes objectives such as building various latch circuits using NAND and NOR gates, designing a D-flip-flop, and verifying their operations. Conclusions highlight the learning outcomes regarding the functionality of flip-flops and latches, including issues encountered during the lab.

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10 views9 pages

Pre & Post 5

The document outlines Lab #5 focused on the analysis and design of latches and flip-flops, detailing the characteristic equations and excitation tables for SR latches, D-flip-flops, and JK flip-flops. It includes objectives such as building various latch circuits using NAND and NOR gates, designing a D-flip-flop, and verifying their operations. Conclusions highlight the learning outcomes regarding the functionality of flip-flops and latches, including issues encountered during the lab.

Uploaded by

ibrahimalqunoon.thabat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Jordan University of Science and Technology

Section : WEDNESDAY (2.15-5.15)

Lab #5: Analysis and Design of Latches


and Flip Flops

POSTLAP

Prepared by :
20042025005 ‫نبيل حسين شامي‬
20042025009 ‫مؤيد سمارة‬
LAB 5: Analysis and Design of Latches
and Flip Flops

Q1. Derive the characteristic equations and the excitation tables for the Set/Reset (SR)
latch, the D-flip/flop, and JK-flip/flop. The characteristic equation gives the next state in
terms of the inputs and the current state. The excitation table shows the excitation signals
as functions of inputs and current state.

** SR Latch:

S R Q Q' Next State of Q


1 0 1 0 Q=1 ; Set State
0 0 1 0 Q=1 ; No Change
0 1 0 1 Q=0 ; Reset State
0 0 0 1 Q=0 ; No Change
1 1 0 0 Indeterminate

** S' R' Latch:

S R Q Q' Next State of Q


1 0 0 1 Q=0 ; Reset State
1 1 0 1 Q=0 ; No Change
0 1 1 0 Q=1 ; Sett State
1 1 1 0 Q=1 ; No Change
0 0 1 1 Indeterminate

** SR Latch With Control Input :

C S R Next State of Q
0 X X No Change
1 0 0 No Change
1 0 1 Q=0 ; Reset State
1 1 0 Q=1 ; Set State
1 1 1 Indeterminate

*** The Characteristic Equation of SR Latch is :


Q(t+1) = S + R’Q
** D Flip/Flop :

D Next State of Q
0 Q=0 ; Reset State Q(t+1) = D
1 Q=1 ; Set State

*** The Characteristic Equation of D Flip/Flop is :


Q(t+1) = D

** JK Flip/Flop:

J K Next State of Q
0 0 Q(t) No Change
Q(t+1)=JQ' + K'Q
0 1 0 Reset
1 0 1 Set
1 1 Q'(t) Complement

*** The Characteristic Equation of JK Flip/Flop is :


Q(t+1) = JQ’ + K’Q
Q2. Build the SR latch circuit using NOR gates.

Q3. Build the S'R' latch using NAND gates.


Q4. Build the SR latch with enable by adding 2 NAND gates to the S'R' latch.

Q5. Design a D-flip/flop using only NAND gates.


Q6. Build a JK-flip/flop using a D-flip/flop.
LAB 5: Analysis and Design of Latches
and Flip Flops

Q1. Draw the timing diagrams for Q and Q' of an SR latch given the timings of S and R,
as shown below. Don’t take the propagation delay issue into consideration.

Q2. Draw the timing diagrams for Q and Q' of a D-flip/flop given the timing of D and
clock, as shown below. Don’t take the propagation delay issue into consideration.
****Objectives and Conclusions****
- Objectives:

In this experiment we try to:

.a. Build the SR latch circuit using NOR gates

b. Build the S'R' latch using NAND gates.

.c. Build the SR latch with enable by adding 2 NAND gates to the S'R' latch

.d. Design a D-flip/flop using only NAND gates

e. Build a JK-flip/flop using a D-flip/flop.

f. Verify the operation of the flip-flops & check if we get the same expected results or
not.
g. Derive the characteristic equation for the latches & flip-flops above

- Conclusions:

a. In this lab we build at first SR and S`R` latches, during that we faced some
problems, the first one was About the clock, the switch was damaged

b. We learn that the output of the Flip/Flop is not change without the Clock But the
latch is change when we change the input .

c. We can build a JK- Flip/Flop using D-Flip/Flop and how to build the SR latch
using NAND gates and NOR gates and with enable .

d. We learn that the D-Flip/Flop consist of 2 latches and the clock of the 2 latches is
convert to other .

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