TRUBA GROUPS OF INSTITUTES BHOPAL
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.
LIST OF EXPERIMENTS
MEVD (107)
DIGITAL DESIGN
1. Study of VHDL and comparison with verilog.
2. Write a VHDL code for all the basic gates usingXilinx 6.2 and simulate them.
3. Write the VHDL code for following functions.
4.Write the VHDL CODE for half adder circuit using Xilinx 6.2 .
5. Weite a VHDL code for full adder circuit using Xilinx 6.2 .
6. Write a VHDL code for 2*4 Decoder circuit using Xilinx 6.2 .
7. Write a VHDL code for 2*1 MUX using Xilinx 6.2 .
8. Write a VHDL CODE FOR 4*1 MUX using Xolinx 6.2 .
9. Implement the D and T flip flop with VHDL coding using Xilinx 6.2 .
10. Write the VHDL code for 4 bit adder using Xilinx.
Experiment No: 4
AIM:
To study of VHDL CODE for half adder circuit using Xilinx 6.2
DESCRIPTION:
A half adder is a type of adder, an electronic circuit that performs the addition of numbers. Type of Logic
gates used in Half Adder is one EX-OR gate and one AND gate.
VHDL Code Half adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_adder is
port(a,b:in bit; sum,carry:out bit);
end half_adder;
architecture data of half_adder is
begin
sum<= a xor b;
carry <= a and b;
end data;
Half Adder Circuit Diagram.
Half-adder Simulation Output:
Result:
Hence the study of VHDL CODE for half adder circuit using Xilinx 6.2 is Completed Successfully.
EXPERIMENT NO: 5
AIM:
To study of VHDL code for full adder circuit using Xilinx 6.2
DESCRIPTION:
Full Adder is the adder which adds three inputs and produces two outputs. The logic gates used in Full
Adder is 2 Half Adders and a OR gate is required to implement a Full Adder.
VHDL Code Half adder:
Full adder Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_adder is port
(a,b,c:in bit; sum,carry:out bit);
end full_adder;
architecture data of full_adder is
begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;
Full adder Circuit Diagram
Full-adder Simulation Output:
Result:
Hence the study of VHDL CODE for full adder circuit using Xilinx 6.2 is Completed Successfully.
EXPERIMENT NO: 6
AIM:
To study of VHDL code for 2*4 Decoder circuit using Xilinx 6.2
DESCRIPTION:
A 2 to 4 decoder is a combinational logic circuit that takes two input lines, typically labeled A and B, and
generates four output lines, usually labeled Y0, Y1, Y2, and Y3. The decoder analyzes the input
combination and activates the corresponding output line.
