Hailo-8L™

Datasheet

Revision 1.5
August 2024

Part Numbers
Industrial: HNC1LBI11BH
See Table 1 for ordering information.

Confidential and proprietary – unauthorized reproduction prohibited

 Hailo-8L™ Datasheet Rev.1.5

Disclaimer and proprietary

information notice:
Copyright
© 2024 Hailo Technologies Ltd (“Hailo”). All rights reserved.

No part of this document may be reproduced or transmitted in any form without the
express, written permission of Hailo. Nothing contained in this document should be
construed as granting any license or right to use proprietary information without the
written permission of Hailo.

This version of the document supersedes all previous versions.

General Notice
To the fullest extent permitted by law, Hailo provides this document “as is” and
disclaims all warranties, either express or implied, statutory or otherwise, including but
not limited to the warranties of merchantability, non-infringement of third party rights,
and fitness for particular purposes.

This document may inadvertently contain technical inaccuracies or other errors. Hailo
assumes no liability for any such errors and for damages, whether direct, indirect,
incidental, consequential or otherwise, that may result from such errors, including but
not limited to loss of data or profits.

The content in this document is subject to change without notice. Hailo reserves the
right to make changes to document content without notification to users.

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 Hailo-8L™ Datasheet Rev.1.5

Documentation Control
History Table

Revision Date Description

0.1 July 2022 Initial release

1.0 November 2022 Removal of commercial part details

1.1 December 2022 Section 2.2-U5 removed from GND

Replaced V3 with A19
Section 2.2 U5 and J3 added to RESERVED

1.2 August 2023 Updated voltages in Section 4.2 Recommended

Operating Conditions
Revised Section 4.3 Power-up Sequence New
sequence description, drawing and timing
requirements table

1.3 October 2023 Updated system modes and usage scenarios

1.4 December 2023 Section 4.4.1 updated VDDIO to 300 mA,

Max VDD_Core to 7.2A and Max VDD_Top to 1A
Typo correction on pin names PCIE_REFCLK and
CSI_TX _CLK

1.5 August 2024 Updated Functional Assignment table

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 Hailo-8L™ Datasheet Rev.1.5

Table of Contents
1. Overview ......................................................................................................................................... 10
1.1. Introduction .......................................................................................................................10
1.2. General Description .........................................................................................................10
1.3. Features ...............................................................................................................................11
1.4. Applications ....................................................................................................................... 12
1.5. Block Diagram ................................................................................................................... 13
1.6. Ordering Information ......................................................................................................14
1.7. Mechanical Details ..........................................................................................................14
1.8. Glossary............................................................................................................................... 17
2. Pinout Description ....................................................................................................................... 19
2.1. Pin Assignment ................................................................................................................. 19
2.2. Functional Assignment .................................................................................................. 21
2.3. Pin Multiplex Specifications ........................................................................................ 29
2.3.1 GPIO Group [0-1] ................................................................................................................ 30
2.3.2 GPIO Group [2-3] ................................................................................................................. 31
2.3.3 GPIO Group [4-5] ................................................................................................................ 32
2.3.4 GPIO Group [6-7] ................................................................................................................ 33
2.3.5 GPIO Group [8-15] .............................................................................................................. 34
2.3.6 GPIO Group [16-31] ............................................................................................................ 36
3. Thermal Characteristics ........................................................................................................... 39
4. Electrical Characteristics ......................................................................................................... 40
4.1. Absolute Maximum Ratings ........................................................................................ 40
4.1.1 Power Rails.......................................................................................................................... 40
4.1.2 Thermal Ratings ................................................................................................................ 42
4.2. Recommended Operating Conditions ...................................................................... 43
4.3. Power-up Sequence ....................................................................................................... 45
4.4. Power Consumption ....................................................................................................... 47
4.4.1 Maximum Supply Current .............................................................................................. 47
4.4.2 Supply Current in Selected Test Cases ...................................................................... 49

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 Hailo-8L™ Datasheet Rev.1.5

4.4.3 Power Modes ...................................................................................................................... 49

4.5. Digital I/O DC Characteristics ..................................................................................... 50
4.6. PCIE Characteristics (DC And AC) ............................................................................... 54
4.7. MIPI DPHY RX Characteristics ..................................................................................... 57
4.8. MIPI DPHY TX Characteristics ..................................................................................... 59
4.8.1 LP Characteristics ............................................................................................................. 59
4.8.2 HS Characteristics.............................................................................................................. 61
4.9. USB Characteristics ........................................................................................................ 66
4.9.1 HS Characteristics............................................................................................................. 66
4.9.2 FS Characteristics ..............................................................................................................67
4.9.3 LS Characteristics ............................................................................................................. 68
4.9.4 Termination Characteristics.......................................................................................... 70
4.10. SDIO Characteristics....................................................................................................... 72
4.11. RGMII Characteristics .................................................................................................... 79
4.12. Reset Characteristics ......................................................................................................81
5. Detailed Description .................................................................................................................. 82
5.1. System Modes and Usage Scenarios ....................................................................... 82
5.1.1 Hailo-8L as a Companion Device ................................................................................. 82
5.2. Bootstraps ......................................................................................................................... 83
5.3. NN Core ............................................................................................................................... 84
5.4. High Bandwidth Interfaces .......................................................................................... 85
5.4.1 Ethernet ................................................................................................................................ 85
5.4.2 PCI Express (PCIe) ............................................................................................................. 86
5.4.3 MIPI CSI ................................................................................................................................. 87
5.4.4 Camera Parallel LVCMOS Interface............................................................................. 88
5.4.5 Universal Serial Bus (USB) ............................................................................................. 88
5.4.6 SDIO ........................................................................................................................................ 89
5.5. Low Bandwidth Interfaces ........................................................................................... 89
5.5.1 Inter-Integrated Circuit (I2C) ......................................................................................... 90
5.5.2 Quad Serial Peripheral Interface (QSPI) .................................................................... 90

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 Hailo-8L™ Datasheet Rev.1.5

5.5.3 Universal Asynchronous Receiver Transmitter (UART) ...................................... 90

5.5.4 Inter-IC Sound (I2S) Input ............................................................................................... 90
5.6. MCU ....................................................................................................................................... 91
5.6.1 Cortex M4 Cores ................................................................................................................. 91
5.6.2 MCU Memory ...................................................................................................................... 92
5.6.3 Flash System ...................................................................................................................... 92
5.7. Vision Subsystem ............................................................................................................ 92
5.7.1 Image Signal Processing (ISP) ...................................................................................... 92
5.7.2 H.264 Encoder .................................................................................................................... 94
5.8. System Peripherals ........................................................................................................ 95
5.8.1 Temperature Sensor ........................................................................................................ 95
5.8.2 Voltage Monitor ................................................................................................................. 95
5.8.3 Direct Memory Access (DMA) ....................................................................................... 95
5.8.4 General-Purpose Input Output (GPIO) ....................................................................... 96
5.8.5 Timer...................................................................................................................................... 96
5.8.6 Watchdog ............................................................................................................................. 96
5.8.7 Mailbox ..................................................................................................................................97
5.8.8 Semaphore ...........................................................................................................................97
5.8.9 CRC Hardware Offload Engine .......................................................................................97
5.9. Security System ............................................................................................................... 98
5.9.1 Features ............................................................................................................................... 98
5.9.2 Lifecycle Management .................................................................................................... 98
5.9.3 True Random Number Generator (TRNG) ................................................................. 98
5.9.4 Cryptographic Accelerator............................................................................................. 98
5.9.5 Trusted Execution Environment (TEE) ....................................................................... 99

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 Hailo-8L™ Datasheet Rev.1.5

List of Figures
Figure 1: Hailo-8L Block Diagram ......................................................................................................13
Figure 2: Hailo-8L Package Views ....................................................................................................15
Figure 3: Hailo-8L Ball Diagram .......................................................................................................20
Figure 4: Power-up Sequence..........................................................................................................46
Figure 5: RGMII Multiplexing & Timing Diagram – TX signals.............................................. 80
Figure 6: RGMII Multiplexing & Timing Diagram – RX Signals ............................................. 80
Figure 7: Reset Characteristics ......................................................................................................... 81
Figure 8: Hailo-8L as a Companion Device ...................................................................................82

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 Hailo-8L™ Datasheet Rev.1.5

List of Tables
Table 1: Ordering Information ........................................................................................................... 14
Table 2: Hailo-8L Package Dimensions ........................................................................................ 16
Table 3: Glossary .................................................................................................................................... 17
Table 4: Hailo-8L Functional Pin Assignment ..............................................................................21
Table 5: GPIO Group [0-1] Multiplex Options ...............................................................................30
Table 6: GPIO Group [2-3] Multiplex Options................................................................................31
Table 7: GPIO Group [4-5] Multiplex Options ............................................................................... 32
Table 8: GPIO Group [6-7] Multiplex Options............................................................................... 33
Table 9: GPIO Group [8-15] Multiplex Options .............................................................................34
Table 10: GPIO Group [16-31] Multiplex Options ......................................................................... 36
Table 11: Thermal Resistance ............................................................................................................ 39
Table 12: Absolute Maximum Power Rail Ratings .................................................................... 40
Table 13: Absolute Maximum Thermal Ratings ..........................................................................42
Table 14: Hailo-8L Operating Ranges ............................................................................................43
Table 15: Power-up Sequence Timing Requirements ..............................................................46
Table 16: Maximum Supply Current ................................................................................................ 47
Table 18: Low-Power Modes, Power Consumption...................................................................49
Table 19: Failsafe Digital Pin DC Characteristics ........................................................................ 50
Table 20: Regular GPIOs DC Characteristics ................................................................................ 52
Table 21: PCIe Gen1 Transmitter Characteristics ....................................................................... 54
Table 22: PCIe Gen2 Transmitter Characteristics ...................................................................... 54
Table 23: PCIe Gen3 Transmitter Characteristics ...................................................................... 54
Table 24: PCIe Transmitter Data Rate Independent Characteristics .................................. 55
Table 25:PCIe Receiver Electrical Idle Detect Threshold ......................................................... 55
Table 26:PCIe Receiver Termination Characteristics................................................................ 55
Table 27: MIPI RX DPHY Clock Lane LP Voltage and Timing Characteristics .................... 57
Table 28: MIPI RX DPHY Data Lane LP Voltage and Timing Characteristics ..................... 57
Table 29: MIPI RX DPHY HS DC Differential Input Impedance ............................................... 58
Table 30: MIPI TX DPHY Data Lane LP DC Characteristics...................................................... 59
Table 31: MIPI TX DPHY Data Lane LP AC Characteristics........................................................ 59
Table 32: MIPI TX DPHY Clock Lane LP DC Characteristics .....................................................60
Table 33: MIPI TX DPHY Clock Lane LP AC Characteristics......................................................60

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 Hailo-8L™ Datasheet Rev.1.5

Table 34: MIPI TX DPHY Data Lane HS DC Characteristics ...................................................... 61

Table 35: MIPI TX DPHY Data Lane HS AC Characteristics ...................................................... 62
Table 36: MIPI TX DPHY Clock Lane HS DC Characteristics ..................................................... 63
Table 37: MIPI TX DPHY Clock Lane HS AC Characteristics .....................................................64
Table 38: MIPI TX DPHY Data Lane HS AC Characteristics ......................................................64
Table 39: USB PHYHS Transmitter – DC Characteristics ......................................................... 66
Table 40: USB PHY HS Transmitter – AC Characteristics ........................................................ 66
Table 41: USB PHY FS Transmitter – DC Characteristics ......................................................... 67
Table 42: USB PHY FS Transmitter – AC Characteristics ......................................................... 67
Table 43: USB PHY FS Single-Ended Receiver – DC Characteristics ....................................68
Table 44: USB PHY FS Single-Ended Receiver – AC Characteristics ....................................68
Table 45: USB PHY LS Transmitter – DC Characteristics .........................................................68
Table 46: USB PHY LS Transmitter – AC Characteristics ......................................................... 69
Table 47: USB PHY LS Single-Ended Receiver – DC Characteristics .................................... 70
Table 48: USB PHY LS Single-Ended Receiver – AC Characteristics .................................... 70
Table 49: USB PHY Termination Characteristics ........................................................................ 70
Table 50: SDIO Receiver Thresholds - 1.8V................................................................................... 72
Table 51: SDIO Receiver Thresholds - 1.2V.................................................................................... 72
Table 52: SDIO Receiver Duty Cycle ................................................................................................ 73
Table 53: SDIO IO Leakage .................................................................................................................. 74
Table 54: SDIO TX Impedance - DC .................................................................................................. 74
Table 55: SDIO TX Capacitance - AC ................................................................................................ 74
Table 56: SDIO TX VOH/VOL............................................................................................................... 75
Table 57: SDIO TX Weak Pull-up/Pull-down................................................................................ 76
Table 58: SDIO Transmitter Rise/Fall Times and Duty-Cycle ................................................ 76
Table 59: SDIO Delay Line Open-Loop ............................................................................................ 78
Table 60: RGMII Timing Requirements .......................................................................................... 79

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 Hailo-8L™ Datasheet Rev.1.5

1. Overview
1.1. Introduction
This datasheet provides a technical description of the Hailo-8L™ System
on a Chip (SoC), an Artificial Intelligence (AI) processor. The Hailo-8L
shares all of its features and innovative architecture with the Hailo-8
however, features lower performance grade, specifically tailored for
applications which emphasize cost and power over performance, yet
requires NN engine with incomparable compute power at the relevant
operating point with respect to cost and TOPS/W efficiency.
This document must be read in conjunction with the Hardware
Integration Guide to ensure proper design.

1.2. General Description

The Hailo-8L SoC provides groundbreaking efficiency for neural network
(NN) deployment based on unique design elements within the Hailo-8L
NN Core, including:
• Distributed memory fabric with purpose-built pipeline elements
that allow very low-power memory access during NN processing
• Extremely efficient computational elements that can be applied
variably, as needed
• Dataflow-oriented interconnect that adapts to the structure of the
NN and allows high resource utilization
The NN Core can be coupled with multiple industry-leading interfaces and
subsystems to deliver high efficiency and high compute, leading-edge AI
solutions.
Hailo-8L enables a broad range of applications by integrating an optimal
mix of performance, low power and sophisticated video analytics
processing.

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 Hailo-8L™ Datasheet Rev.1.5

4-lane PCI Express Gen3

1.3. Features •
endpoint with integrated
• MCU PHY

o 2 ARM Cortex-M4 • MIPI CSI 1.3, 2 RX and TX

@ 200 MHz interfaces

o 640 KB internal o Integrated 4-lane

SRAM (ECC DPHY
protected) o 2.5 Gbps per lane
o FPU, MPU o TX interfaces can
• Neural Processing Unit be used as DSI TX
(NN-Core) • Camera Parallel LVCMOS
o Up to 13 [TOPS] Interface: up to 24 bits
wide @ 100MHz
o High-performance,
Hailo NN multi- • 1Gbps Ethernet
stream, multi- controller, IEEE1588
network core compliant, 100/1000
Mbps
o Hardware offload
engines for Deep • 4 UARTs
Neural Networks • 4 I2C interfaces
(DNN) with pre and
post processing: • 4 timers
• 2 x multi-channel
- Tensor
programmable DMA
manipulation
engines
(crop & resize, ROI
pooling, reshape) • 32 configurable GPIOs
with interrupt support
- Non Maximum
Suppression • Quad SPI Flash Interface
(NMS) o Up to 50MHz clock
- Bi-linear supported
transformation o Includes Flash
- Softmax cache hardware

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 Hailo-8L™ Datasheet Rev.1.5

• Vision Subsystem • Security Features

o H.264 encoder o Hardware crypto
accelerators
o Image Signal
Processor (ISP) for o Firewall
a single sensor
o Secure ROM and
o Input formats: boot
RAW8, RAW10,
• Power, reset and clock
RAW12, RAW14
management
o Output formats:
• Voltage monitor
RGB888, YUV422
• Temperature monitor
o Maximum input
resolution: • Package
4096X4096 P o 400-pin HFCBGA
o Throughput: 4k @ o 17mm x 17mm,
40 FPS, 1080p @ 0.8mm pitch
120 FPS

1.4. Applications
The Hailo-8L SoC enables a broad range of applications, including:
• Smart cities: public safety, intelligent mobility, health monitoring,
infrastructure & services management
• Industry 4.0: manufacturing automation, robotic vision, safety &
security
• Smart retail: automated store, smart analytics, targeted advertising
• Smart home: lifestyle & entertainment, safety & security
• Drones: sense, avoid and navigate

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 Hailo-8L™ Datasheet Rev.1.5

1.5. Block Diagram

Figure 1 shows the subsystems and functional modules of the Hailo-8L SoC.

Figure 1: Hailo-8L Block Diagram

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 Hailo-8L™ Datasheet Rev.1.5

1.6. Ordering Information

Table 1: Ordering Information

Temperature
Part Number Device Grade
Range

HNC1LBI11BH Industrial -40° to 85° C

1.7. Mechanical Details

Figure 2 shows the top, bottom and side views of the 400-pin HFCBGA
package including package dimensions.

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 Hailo-8L™ Datasheet Rev.1.5

Figure 2: Hailo-8L Package Views

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 Hailo-8L™ Datasheet Rev.1.5

Table 2: Hailo-8L Package Dimensions

Common Dimensions
Description Symbol
Min Nom Max
Total thickness A 2.326 2.476 2.626
Standoff A1 0.300 - 0.500
Substrate thickness A2 C676 Ref
Thickness from substrate
A3 -
surface to die backside

E 17 BSC
Body size
D 17 BSC
Ball diameter C.500
Ball width b 0.400 - 0.600
Ball pitch e C.800 BSC
Ball count d 400
Edge ball center to center E1 15.200 BSC
D1 15.200 BSC
E2 BSC
Expose die size
D2 BSC
Package edge tolerance aaa C.200
Substrate parallelism bbb C.250
Top parallelism ccc C.350
Coplanarity ddd C.150
Ball offset (package) eee C.250
Ball offset (ball) fff C.100

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 Hailo-8L™ Datasheet Rev.1.5

1.8. Glossary
Table 3 shows a list of the abbreviations used in this document.
Table 3: Glossary

Abbreviation Description
BS Boot strap
CMOS Complementary Metal-Oxide
Semiconductor
CS Chip Select
CSI Camera Serial Interface
DMA Direct Memory Access
DNN Deep Neural Network
DSI Display Serial Interface
ECC Error Correction Code
ETM Electronic Trace Management
FPU Floating Point Accelerator Unit
FS Full Speed
GPIO General-Purpose Input Output
HS High Speed
I/O Input Output
I2C Inter-Integrated Circuit
I2S Inter-IC Sound
LP Low Power
MCU Microcontroller Unit
MIPI Mobile Industry Processor Interface

MMU Memory Management Unit

MPU Memory Protection Unit

NMS Non-Maximum Suppression

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 Hailo-8L™ Datasheet Rev.1.5

NN Neural Network

PCIe Peripheral Component Interconnect

Express
PHY Physical Layer
PLL Phase-Locked Loop
PVT Process, Voltage, and Temperature
QSPI Queued Serial Peripheral Interface

RGMII Reduced Gigabit Media Independent

Interface
RMII Reduced Media-Independent Interface
ROI Region of Interest
RoT Root of Trust
RX Receiver
SRP Session Request Protocol
SDIO Secure Digital Input Output
SoC System on a Chip
TEE Trusted Execution Environment
TOPS Tera Operations Per Second
TX Transmitter
UART Universal Asynchronous Receiver
Transmitter
USB Universal Serial Bus
XIP Execute in Place

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 Hailo-8L™ Datasheet Rev.1.5

2. Pinout Description
2.1. Pin Assignment
Figure 3 on the following page, shows the schematic view of the Hailo-8 ball diagram.

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 Hailo-8L™ Datasheet Rev.1.5

Figure 3: Hailo-8L Ball Diagram

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 Hailo-8L™ Datasheet Rev.1.5

2.2. Functional Assignment

Hailo-8L functional pin assignment is described in Table 4 .
Pin Types are categorized as follows:
• Power: SoC power rails
• I: input signals (Analog/Digital)
• O: output signals (Analog/Digital)
• OD: Open Drain IO
Table 4: Hailo-8L Functional Pin Assignment

Ball Default
Default
Pin Numbers Pin Name Description Reset Cell Type Schmitt
Direction
State Trigger
Main Power and Sensing
A1, A5, A15, A20, B5, B15, C4, C5, C9, C10, C11,
C15, C16, D1, D4, D5, D7, D10, D12, D14, D15,
D16, E4, E5, E6, E7, E8, E9, E11, E12, E13, E14,
E15, E16, E17, E18, E19, E20, F4, F7, F8, F11,
F12, F15, G1, G2, G3, G4, G7, G8, G11, G12,
G15, H4, H7, H8, H11, H12, H15, J7, J8, J11, J12,
J15, J16, J17, J18, J19, J20, K4, K7, K8, K11, K12,
GND Digital ground for device Power
K15, L2, L7, L8, L11, L12, M4, M7, M8, M11,
M12, M15, N4, N7, N8, N11, N12, N15, N17,
N19, N20, P4, P7, P8, P11, P12, P15, R1, R4, R7,
R8, R11, R12, R15, T4, T5, T6, T7, T8, T9, T10,
T11, T12, T13, T14, T15, U4, U6, U7, U8, U10,
U11, U12, U13, U14, U16, V5, V8, V11, V14,
W15, Y1, Y15, Y16, Y20

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 Hailo-8L™ Datasheet Rev.1.5

Ball Default
Default
Pin Numbers Pin Name Description Reset Cell Type Schmitt
Direction
State Trigger
F5, F6, F9, F10, F13, F14, G5, G6, G13, G14, H5,
H6, H13, H14, J5, J6, J14, K5, K6, K14, L5, L6,
Digital supply for SoC NN core
L13, L14, M5, M6, M13, M14, N5, N6, N9, N10, VDDCORE Power
domain
N13, N14, P5, P6, P9, P10, P13, P14, R5, R6, R9,
R10, R13, R14
G9, G10, H9, H10, L9, L10, M9, M10, V16, W16 VDDTOP Digital supply for SoC top domain Power
D2, D3, J9, J10, K9, K10, R2, R3 VDDIO Digital supply for IO pads Power
K13 PLL_VSSA Analog ground for PLL Power
J13 PLL_VDDA Analog supply for PLL Power
Analog supply for temperature
E10, U9 AVDD_TS Power
sensor
L4 AVDD_VS Analog supply for voltage sensor Power
J4 VDD_SENSE Sense for VDDCORE Sensing
L15 VDD_SENSE1 Sense for VDDTOP Sensing
PCI Express (PCIe) Interface
D6 PCIE_WAKE_N Input PCIe wake signal to host LVCMOS
Drive
D8 PCIE_CLKREQ_N Output PCIe clock request to host LVCMOS
0
D9 PCIE_PERST_N Input PCIe reset in PD LVCMOS Yes
PCIe positive signal of data transmit
A6, A8, A12, A14 PCIE_TX[0:3]_P I Analog
diff-pair
PCIe negative signal of data transmit
B6, B8, B12, B14 PCIE_TX[0:3]_N O Analog
diff-pair
PCIe positive signal of the data
A7, A9, A11, A13 PCIE_RX[0:3]_P I Analog
receive diff-pair
PCIe negative signal of data receive
B7, B9, B11, B13 PCIE_RX[0:3]_N I Analog
diff-pair
B10 PCIE_REFCLK_N I PCIe ref clock in negative Analog

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 Hailo-8L™ Datasheet Rev.1.5

Ball Default
Default
Pin Numbers Pin Name Description Reset Cell Type Schmitt
Direction
State Trigger
A10 PCIE_REFCLK _P I PCIe ref clock in positive Analog
PCIe calibration connection to
D11 PCIE_CMN_REXT I Analog
external resistor
Analog power for high-speed clock
A4, A16, B4, B16 PCIE_AVDD_C Power
and digital functions
Clean analog power for high speed
C6, C7, C8, C12, C13, C14 PCIE_AVDD_D Power
clock
D13 PCIE_AVDD_H PCIe Analog I/O voltage Power
MIPI CSI TX Interface
Negative output of MIPI CSI TX
Y6, Y7, Y8, Y9 CSI0_TX[0:3]_N O Analog
interface[0] data lanes
Positive output of MIPI CSI TX
W6, W7, W8, W9 CSI0_TX[0:3]_P O Analog
interface data lane
Negative output of MIPI CSI TX
Y11, Y12, Y13, Y14 CSI1_TX[0:3]_N O Analog
interface[1] data lanes
Positive output of MIPI CSI TX
W11, W12, W13, W14 CSI1_TX[0:3]_P O Analog
interface[1] data lanes
Negative output of MIPI CSI TX
Y5, Y10 CSI[0:1]_TXCLK_N O Analog
interface clock
Positive output of MIPI CSI TX
W5, W10 CSI[0:1]_TXCLK_P O Analog
interface clock
Pin connected to external resistor
V9, V15 CSI[0:1]_TX_RCALIB I/O for calibrating on-SoC resistors for Analog
MIPI CSI TX interface
Analog power supply for MIPI CSI TX
V6, V12 CSI[0:1]_TX_AVDD Power
core
Analog power supply for MIPI CSI TX
V7, V13 CSI[0:1]_TX_AVDDH Power
bias and PLL
Clean analog power supply for high-
V4, V10 CSI[0:1]_TX_AVDD_CLK Power
speed clock applications

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 Hailo-8L™ Datasheet Rev.1.5

Ball Default
Default
Pin Numbers Pin Name Description Reset Cell Type Schmitt
Direction
State Trigger
MIPI CSI RX Interface
Negative input of MIPI CSI RX[0]
K17, K18, K19, K20 CSI0_RX[0:3]_N I Analog
interface data lane
Positive input of MIPI CSI RX[0]
L17, L18, L19, L20 CSI0_RX[0:3]_P I Analog
interface data lane
Negative input of MIPI CSI RX[1]
F17, F18, F19, F20 CSI1_RX[0:3]_N I Analog
interface data lane
Positive input of MIPI CSI RX[1]
G17, G18, G19, G20 CSI1_RX[0:3]_P I Analog
interface data lane
Negative input of MIPI CSI RX
K16, F16 CSI[0:1]_RXCLK_N I Analog
interface clock
Positive input of MIPI CSI RX
L16, G16 CSI[0:1]_ RXCLK_P I Analog
interface clock
Pin connected to external resistor
M18, H16 CSI[0:1]_RX_RCALIB I/O for calibrating on-SoC resistors for Analog
MIPI CSI RX interface
Analog power supply for MIPI CSI
M19, M20 CSI0_RX_AVDD Power
RX[0] core
Analog power supply for MIPI CSI
H19, H20 CSI1_RX_AVDD Power
RX[1] core
Analog power supply for MIPI CSI
M16, M17 CSI0_RX_AVDDH Power
RX[0] bias and PLL
Analog power supply for MIPI CSI
H17, H18 CSI1_RX_AVDDH Power
RX[1] bias and PLL
Universal Serial Bus (USB) Interface
L1 USB_DP I/O USB2.0 positive data Analog
K1 USB_DM I/O USB2.0 negative data Analog
K3 USB_ID I USB2.0 ID Analog
Pin connected to external resistor
L3 USB_RTRIM I Analog
for calibrating on-SoC resistors

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 Hailo-8L™ Datasheet Rev.1.5

Ball Default
Default
Pin Numbers Pin Name Description Reset Cell Type Schmitt
Direction
State Trigger
M2 USB_AVDD_CORE Analog power supply for USB core Power
M1 USB_AVDD_IO Analog power supply for USB I/Os Power
K2 USB_AVDD_IO_HV Analog power supply for USB Power
M3 USB_VBUS USB2.0 VBUS Analog
Secure Digital Input Output (SDIO) Interface
U3, N3 SDIO[0-1]_CLK SDIO/eMMC clock HiZ SDIO
T2, P1 SDIO[0-1]_CMD SDIO /eMMC control HiZ SDIO
T1, U2, T3, U1
SDIO[0-1]_DATA [0:3] SDIO /eMMC data I/O HiZ SDIO
P2, N1, P3, N2
R2, R3 VDDIO_SDIO Digital power supply for SDIO I/O Power
Ethernet Interface
Drive
B2, A3, A2, C1 ETH_RGMII_TXD[0:3] Output Transmit data signal to PHY LVCMOS
0
Drive
B1 ETH_RGMII_TX_CLK Output Transmit clock signal to PHY LVCMOS
0
Drive
B3 ETH_RGMII_TX_CTL Output Transmit control signal to PHY LVCMOS
0
F3, E3, E2, E1 ETH_RGMII_RXD[0:3] Input Receive data signal from PHY PD LVCMOS Yes
F1 ETH_RGMII_RX_CLK Input Receive clock signal from PHY PD LVCMOS Yes
F2 ETH_RGMII_RX_CTL Input Receive control signal from PHY PD LVCMOS Yes
PD,
C2 ETH_MDC Output Management interface clock Drive LVCMOS
0
Management interface Data input
C3 ETH_MDIO Input PU LVCMOS Yes
output

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 Hailo-8L™ Datasheet Rev.1.5

Ball Default
Default
Pin Numbers Pin Name Description Reset Cell Type Schmitt
Direction
State Trigger
Camera Parallel LVCMOS Interface
P20 PARALLEL_PCLK Input Parallel input clock PD LVCMOS
Pin multiplexed with GPIOs PARALLEL_VSYNC I Parallel VSYNC
Pin multiplexed with GPIOs PARALLEL_HSYNC I Parallel HSYNC
Pin multiplexed with GPIOs PARALLEL_DATA[0:23] I Parallel data in
Flash Interface
PD,
V3 FLASH_RESET Output Flash reset out Drive LVCMOS
1
PU,
Y3, W3 FLASH_CS[0:1]_N Output Flash chip select, active low Drive LVCMOS
1
Pin multiplexed with GPIOs FLASH_CS[2:3]_N Flash chip select, active low PD
V1, V2, Y2, W2 FLASH_DQ[0:3] Input Flash data in/out LVCMOS
Drive
W1 FLASH_SCLK Output Flash clock LVCMOS
0
Universal Asynchronous Receiver Transmitter (UART) Interface
J1, J2 UART[0:1]_RXD Input UART receive data PD LVCMOS Yes
H1 UART[0]_TXD Input UART transmit data PD LVCMOS Yes
H2 UART[1]_TXD HiZ UART transmit data LVCMOS Yes
Inter-Integrated Circuit (I2C) Interface
D18, B18 I2C[0:1]_SDA Input I2C[0-1] serial data PU LVCMOS
C18, A18 I2C[0:1]_SCL Input I2C[0-1] clock PU LVCMOS
Pin multiplexed with GPIOs I2C[0:3]_CURRENT_ I/O Fast mode I2C pin
SRC_EN
Pin multiplexed with GPIOs I2C[2:3]_SDA I/O I2C[2-3] serial data

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 Hailo-8L™ Datasheet Rev.1.5

Ball Default
Default
Pin Numbers Pin Name Description Reset Cell Type Schmitt
Direction
State Trigger
Pin multiplexed with GPIOs I2C[2:3]_SCL O I2C[2-3] clock
Inter-IC Sound (2S) Interface
A17 I2S_WS Input I2S word select PD LVCMOS
Drive
B17 I2S_SCK Output I2S serial clock LVCMOS
X, PD
C17 I2S_SDI Input I2S serial data in PD LVCMOS
I2S serial data out. Used as
D17 I2S_SDO Input BS_IO_SEL[0] during Bootup. See PD LVCMOS
section 5.2 below
Reset and Clock
D19 CLK_IN Input SoC main clock LVCMOS
A19 NRESET I Chip reset, active low PD LVCMOS Yes
JTAG
C20 JTAG_TDI Input JTAG data input PU LVCMOS
Drive
C19 JTAG_TDO Output JTAG data output LVCMOS
0, PD
B20 JTAG_TMS Input JTAG mode select PU LVCMOS
B19 JTAG_TCK Input JTAG clock PD LVCMOS
D20 JTAG_TRSTN Input JTAG reset. Active low PD LVCMOS Yes
GPIO
General configurable pins. Output Drive
P16, U15, P17, N18 GPIO[0, 2-4] Output LVCMOS
during Bootup. 0
General configurable pins. Output Drive
N16 GPIO[1] Output LVCMOS
during Bootup. X
General configurable pins. Output Drive
T16 GPIO[5] Output LVCMOS
during Bootup. 1

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 Hailo-8L™ Datasheet Rev.1.5

Ball Default
Default
Pin Numbers Pin Name Description Reset Cell Type Schmitt
Direction
State Trigger
P18, P19, R16, R17, V17, W17, Y17, R18, T18,
GPIO[6-9, 12-23] Input General configurable pins PD LVCMOS
U18, V18, W18, Y18, Y19, W19, V19
Drive
T17, U17, U19, T19, R19, R20, T20, U20 GPIO[10-11, 24-29] Output General configurable pins LVCMOS
0
Drive
V20, W20 GPIO[30-31] Output General configurable pins LVCMOS
1
MCU GPIOS
Pin multiplexed with GPIOs MCU_GPIO[0-31] I/O GPIOs
Timers
Pin multiplexed with GPIOs TIMER[0-3]_EXT_IN I External timer clock input
Electronic Trace Management (ETM)
Pin multiplexed with GPIOs ETM_TRACE_CLOCK ETM clock out
Pin multiplexed with GPIOs ETM_DATA[0-3] ETM trace data out
Miscellaneous
H3, J3, U5, W4, Y4 RESERVED I Factory use only. Do not connect. PD

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 Hailo-8L™ Datasheet Rev.1.5

2.3. Pin Multiplex Specifications

This section describes the possible multiplex configurations available for Hailo-8L GPIOs. Each of the 32
GPIOs has up to 8 options.
Important: Each group of pins can only be set to the same option.
• Option1 – pads_pinmux_mode[3:0] = [0000]
• Option2 – pads_pinmux_mode[3:0] = [0010]
• Option3 – pads_pinmux_mode[3:0] = [0011]
• Option4 – pads_pinmux_mode[3:0] = [0100]
• Option5 – pads_pinmux_mode[3:0] = [0101]
• Option6 – pads_pinmux_mode[3:0] = [0110]
• Option7 – pads_pinmux_mode[3:0] = [0111]
• Option8 – pads_pinmux_mode[3:0] = [1000]
• Option9 – pads_pinmux_mode[3:0] = [1001]

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 Hailo-8L™ Datasheet Rev.1.5

2.3.1 GPIO Group [0-1]

The multiplex options for GPIO[0] and GPIO[1] are listed in Table 5.
Table 5: GPIO Group [0-1] Multiplex Options

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7 Option8 Option9

GPIO0 INITIAL_ GPIO[0] I2C0_CUR FLASH_C PWM[0] Reserved SDIO0_GP UART2_T I2C2_CURR
DEBUG_ RENT_SRC S[2] _OUT XD ENT_SRC_E
BUS [0] _EN N

GPIO1 INITIAL_ GPIO[1] I2C1_CUR FLASH_C PWM[1] Reserved SDIO1_GP UART3_T I2C3_CURR
DEBUG_ RENT_SRC S[3] _OUT XD ENT_SRC_E
BUS [1] _EN N

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 Hailo-8L™ Datasheet Rev.1.5

2.3.2 GPIO Group [2-3]

The multiplex options for GPIO[2] and GPIO[3] are listed in Table 6.
Table 6: GPIO Group [2-3] Multiplex Options

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7 Option8 Option9

GPIO2 INITIAL_ GPIO[2] I2C0_CU FLASH_CS PWM[0] Reserved SDIO0_ UART2_T I2C2_CURR
DEBUG RRENT_ [2] GP_OUT XD ENT_
_BUS [2] SRC_EN SRC_EN

GPIO3 INITIAL_ GPIO[3] I2C1_CU FLASH_CS PWM[1] Reserved SDIO1_ UART3_T I2C3_CURR
DEBUG_ RRENT_ [3] GP_OUT XD ENT_
BUS [3] SRC_EN SRC_EN

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 Hailo-8L™ Datasheet Rev.1.5

2.3.3 GPIO Group [4-5]

The multiplex options for GPIO[4] and GPIO[5] are listed in Table 7.
Table 7: GPIO Group [4-5] Multiplex Options

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7 Option8 Option9

GPIO4 INITIAL_ GPIO[4] I2C0_CUR FLASH_ PWM[0] Reserved SDIO0_GP UART2_T I2C2_CUR
DEBUG_ RENT_ CS[2] _OUT XD RENT_
BUS [4] SRC_EN SRC_EN

GPIO5 INITIAL_ GPIO[5] I2C1_CUR FLASH_ PWM[1] Reserved SDIO1_GP UART3_T I2C3_CUR
DEBUG_ RENT_ CS [3] _OUT XD RENT_
BUS [5] SRC_EN SRC_EN

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 Hailo-8L™ Datasheet Rev.1.5

2.3.4 GPIO Group [6-7]

The multiplex options for GPIO[6] and GPIO[7] are listed in Table 8.
Table 8: GPIO Group [6-7] Multiplex Options

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7 Option8

GPIO6 PARALLEL GPIO[6] SDIO0_GP TIMER0_ TIMER2_ UART2_RXD I2C2_SDA I2C3_SDA

_HSYNC _IN EXT_IN EXT_IN

GPIO7 PARALLEL GPIO[7] SDIO1_GP TIMER1_ TIMER3_ UART3_RXD I2C2_SCL I2C3_SCL

_VSYNC _IN EXT_IN EXT_IN

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 Hailo-8L™ Datasheet Rev.1.5

2.3.5 GPIO Group [8-15]

The multiplex options for GPIO[8] to GPIO[15] are listed in Table 9.
Table 9: GPIO Group [8-15] Multiplex Options

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7

GPIO8 SDIO0_GP_ GPIO[8] PARALLEL_ I2C2_SDA TIMER0_ Reserved FLASH_CS [2]

IN DATA[0] EXT_IN

GPIO9 SDIO1_GP_ GPIO[9] PARALLEL_ I2C2_SCL TIMER1_ Reserved FLASH_CS[3]

IN DATA[1] EXT_IN

GPIO10 SDIO0_GP_ GPIO[10] PARALLEL_ I2C3_SDA PWM[0] I2C0_CURR UART2_RXD

OUT DATA[2] ENT_SRC_E
N

GPIO11 SDIO1_GP_ GPIO[11] PARALLEL_ I2C3_SCL PWM[1] I2C1_CURR UART2_TXD

OUT DATA[3] ENT_SRC_E
N

GPIO12 TIMER0_ GPIO[12] PARALLEL_ Reserved PWM[2] I2C2_CURR UART3_RXD

EXT_IN DATA[4] ENT_
SRC_EN

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 Hailo-8L™ Datasheet Rev.1.5

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7

GPIO13 TIMER1_ MCU PARALLEL_ Reserved PWM[3] I2C3_CURR UART3_TXD

EXT_IN GPIO[13] DATA[5] ENT_
SRC_EN

GPIO14 TIMER2_ MCU PARALLEL_ PARALLEL_ PWM[4] PARALLEL_ PARALLEL_

EXT_IN GPIO[14] DATA[6] HSYNC HSYNC HSYNC

GPIO15 TIMER3_ MCU PARALLEL_ PARALLEL_ PWM[5] PARALLEL_ PARALLEL_

EXT_IN GPIO[15] DATA[7] VSYNC VSYNC VSYNC

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 Hailo-8L™ Datasheet Rev.1.5

2.3.6 GPIO Group [16-31]

The multiplex options for GPIO[16] to GPIO[31] are listed in Table 10.
Table 10: GPIO Group [16-31] Multiplex Options

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7

GPIO16 UART2_RXD GPIO[16] PARALLEL_ PARALLEL_ Reserved SDIO0_GP_I SDIO0_GP_I

DATA[8] DATA[0] N N

GPIO17 UART2_TXD GPIO[17] PARALLEL_ PARALLEL_ Reserved SDIO0_GP_O SDIO0_GP_O

DATA[9] DATA[1] UT UT

GPIO18 UART3_RXD GPIO[18] PARALLEL_ PARALLEL_ Reserved PWM[0] SDIO1_GP_I

DATA[10] DATA[2] N

GPIO19 UART3_TXD GPIO[19] PARALLEL_ PARALLEL_ Reserved PWM[1] SDIO1_GP_O

DATA[11] DATA[3] UT

GPIO20 I2C2_SDA GPIO[21] PARALLEL_ PARALLEL_ Reserved PWM[2] UART2_RXD

DATA[12] DATA[4]

GPIO21 I2C2_SCL GPIO[21] PARALLEL_ PARALLEL_ Reserved PWM[3] UART2_TXD

DATA[13] DATA[5]

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 Hailo-8L™ Datasheet Rev.1.5

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7

GPIO22 I2C3_SDA GPIO[22] PARALLEL_ PARALLEL_ reserved PWM[4] UART3_RXD

DATA[14] DATA[6]

GPIO23 I2C3_SCL GPIO[23] PARALLEL_ PARALLEL_ Reserved PWM[5] UART3_TXD

DATA[15] DATA[7]

GPIO24 I2C0_CURR GPIO[24] PARALLEL_DA PARALLEL_D TIMER0_ Reserved PWM[0]

ENT_SRC_E TA[16] ATA[8] EXT_IN
N

GPIO25 I2C1_CURR GPIO[25] PARALLEL_DA PARALLEL_D TIMER1_ Reserved PWM[1]

ENT_SRC_E TA[17] ATA[9] EXT_IN
N

GPIO26 I2C2_CURR GPIO[26] PARALLEL_DA PARALLEL_D TIMER2_ Reserved I2C2_SDA

ENT_SRC_E TA[18] ATA[10] EXT_IN
N

GPIO27 I2C3_CURR GPIO[27] PARALLEL_DA PARALLEL_D ETM_ Reserved I2C2_SCL

ENT_SRC_E TA[19] ATA[11] TRACE_CLK
N

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 Hailo-8L™ Datasheet Rev.1.5

GPIO Option1 Option2 Option3 Option4 Option5 Option6 Option7

GPIO28 PWM[0] GPIO[28] PARALLEL_DA PARALLEL_D ETM_ Reserved I2C3_SDA

TA[20] ATA[12] DATA[0]

GPIO29 PWM[1] GPIO[29] PARALLEL_DA PARALLEL_D ETM_ Reserved I2C3_SCL

TA[21] ATA[13] DATA[1]

GPIO30 Reserved GPIO[30] PARALLEL_DA PARALLEL_D ETM_ Reserved Reserved

TA[22] ATA[14] DATA[2]

GPIO31 Reserved GPIO[31] PARALLEL_DA PARALLEL_D ETM_ Reserved Reserved

TA[23] ATA[15] DATA[3]

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 Hailo-8L™ Datasheet Rev.1.5

3. Thermal Characteristics
Package thermal resistance at various junctions and under various airflow
conditions is shown in Table 11. The board that achieved these results is
defined by JEDEC (please refer to JEDEC standard JESD51-9, Test Board for
Array Surface Mount Package Thermal Measurements) as follows:
• 8 PCB layers
• PCB dimensions [mm X mm] - 101.5 X 114.5
• PCB thickness [mm X mm] - 1.6 mm
Table 11: Thermal Resistance

Location Airflow Thermal Resistance

(° C/W)

Junction to ambient No airflow 8.9

𝜽𝑱𝑨 _𝟎

Junction to ambient 1 m/s airflow 7.8

𝜽𝑱𝑨 _𝟏

Junction to ambient 2 m/s airflow 7.3

𝜽𝑱𝑨 _𝟐

Junction to board No airflow 2.28

𝜽𝑱𝑩

Junction to case No airflow 0.35

𝜽𝑱𝑪

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 Hailo-8L™ Datasheet Rev.1.5

4. Electrical Characteristics
4.1. Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 13 may
cause permanent damage to the device and affect device reliability. These
are stress ratings only and functional operation of the device at these
conditions is not implied.

4.1.1 Power Rails

Table 12 provides the absolute maximum ratings of the power rails.
Table 12: Absolute Maximum Power Rail Ratings

Supply Name Description Min Max Unit

Digital Power Rails

VDD_TOP Top logic -0.3 1.05 V

VDD_CORE NN core -0.3 1.05 V

VDDIO IO banks -0.3 1.98 V

VDDIO_SDIO SDIO IO -0.3 1.98 V

MIPI DPHY Analog Power Rails

CSI_RX_AVDD MIPI DPHY RX/TX core supply for -0.3 1.05 V

analog and digital
CSI_TX_AVDD

CSI_RX_AVDD_H High voltage power for the RX/TX -0.3 1.98 V

analog, bias and PLL (PLL only for
CSI_TX_AVDD_H
TX)

CSI_TX_CLK MIPI DPHY TX (only) clean core -0.3 1.05 V

supply for analog high-speed
clocking circuits

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 Hailo-8L™ Datasheet Rev.1.5

Supply Name Description Min Max Unit

PCIe PHY Analog Power Rails

PCIE_AVDD_D Analog power for non-high speed -0.3 1.05 V

clock and digital functions

PCIE_AVDD_C Clean analog power for high speed -0.3 1.05 V

clock applications

PCIE_AVDD_H High voltage power for the bias and -0.3 1.98 V
parts of the PLL

USB PHY Analog Power Rails

USB_AVDD_CORE USB core -0.3 1.05 V

USB_AVDD_IO USB IO -0.3 1.98 V

USB_AVDD_IO_HV Clean analog power supply for USB -0.3 3.63 V

IO

Miscellaneous

PLL_AVDD PLL analog power rail -0.3 1.05 V

FUSE_VQPS Factory use only. Connect to GND. - - V

AVDD_TS Temperature sensor analog power -0.3 1.98 V

rail

AVDD_VS Voltage sensor analog power rail -0.3 1.98 V

Input voltage applied to Input Low Voltage -0.3 1.98 V

digital IOs

V_ESD (HBM) Electrostatic discharge voltage 2000 V

(Human Body Model)

V_ESD (CDM) Electrostatic discharge voltage 500 V

(Charged Device Model)

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 Hailo-8L™ Datasheet Rev.1.5

Supply Name Description Min Max Unit

Latch UP (LU) class II of JESD78E immunity level A1 -

4.1.2 Thermal Ratings

Table 13 provides the storage and maximum junction temperature values.
Table 13: Absolute Maximum Thermal Ratings

Parameter Description Value Unit

T_Storage Storage temperature –65 to +150 °C

T_J Maximum junction temperature 125 °C

1 Immunity level A: Pass the ±100mA and 1.5xVdd or MSV

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 Hailo-8L™ Datasheet Rev.1.5

4.2. Recommended Operating Conditions

Table 14 describes the recommended operating conditions for power
rails, clocks and ambient temperature.
Table 14: Hailo-8L Operating Ranges

Supply Name Description Min Nom Max Unit

Digital Domain Power Rails

VDD_TOP Top logic power rail 0.78 0.83 0.88 V

VDD_CORE Neural Network Core Power rail 0.78 0.83 0.88 V

VDDIO Digital Power Rail for IO banks 1.62 1.8 1.98 V

VDDIO_SDIO1 Digital Power Rail for SDIO IO 1.08/ 1.2/ 1.32/ V

1.62 1.8 1.98

MIPI DPHY Analog Power Rails

CSI_RX_AVDD MIPI RX/TX MIPI DPHY Core supply for 0.78 0.83 0.88 V
analog and digital
CSI_TX_AVDD

CSI_RX_AVDD_H High voltage power for the RX/TX MIPI 1.62 1.8 1.98 V
DPHY analog, bias and PLL (PLL only
CSI_TX_AVDD_H
for TX)

CSI_TX_CLK MIPI DPHY TX (only) clean core supply 0.78 0.83 0.88 V
for analog high-speed clocking
circuits

PCIe PHY Analog Power Rails

PCIE_AVDD_D Analog power for non-high speed 0.78 0.83 0.88 V

clock and digital functions

1
Depending on the selected mode of SDIO IO power rail. 1.2V or 1.8V.

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 Hailo-8L™ Datasheet Rev.1.5

Supply Name Description Min Nom Max Unit

PCIE_AVDD_C Clean analog power for high speed 0.78 0.83 0.88 V
clock applications

PCIE_AVDD_H High voltage power for the bias and 1.08 1.8 1.98 V
parts of the PLL

USB PHY Analog Power Rails

USB_AVDD_CORE Analog power supply for the USB core 0.78 0.83 0.88 V

USB_AVDD_IO Analog power supply for the USB’s IO 1.62 1.8 1.98 V

USB_AVDD_IO_HV Clean analog power supply for USB’s 2.97 3.3 3.63 V
IO

Other Power Rails

PLL_AVDD PLL analog power rail 0.78 0.83 0.88 V

FUSE_VQPS Factory use only. Connect to GND. - - - V

AVDD_TS Temperature sensor analog power 1.62 1.8 1.98 V

rail

AVDD_VS Voltage sensor analog power rail 1.62 1.8 1.98 V

External Clocks

CLK_IN1 Frequency 25±100PPM MHz

Main Input clock signal
Duty Cycle 40 50 60 %
(square wave)

Ambient Operating Temperature

T_A Consumer grade 0 70 o

C

Industrial grade -40 85 o

C

1
CLK_IN clock pin must receive a square wave clock signal (oscillator output clock signal).

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 Hailo-8L™ Datasheet Rev.1.5

4.3. Power-up Sequence

The power-up sequence should follow these guidelines: 1
1. Initial state: NRESET pin is asserted (held low).
2. VDDIO rises to 1.8V. Slew rate should be less than 18V/ms.
3. VDD_CORE rises to 0.83V. VDD_CORE must hold VDD_CORE <VDDIO-
0.3V. Slew rate of VDD_CORE should be less than 18V/ms.
4. PLL_VDDA should rise with VDD_CORE and be powered from
VDD_CORE power regulator with filtering.
5. After the VDD_CORE reaches final level:
a) Power-up CSI_RX/TX_AVDD and CSI_RX/TX_AVDDH. Each power
ramp-up should be between 100us and 2ms. CSI_RX/TX_AVDDH
and CSI_RX/TX_AVDD can power-up in any order.2
b) Power-up PCIE_AVDD_D, PCIE_AVDD_C, PCIE_AVDD_H in any order.
There are no timing limitations (minimum or maximum) when
powering-up multiple power supplies.
c) PCIE_AVDD_D, PCIE_AVDD_C can be powered from VDD_CORE
power regulator as long as noise target is met.11
d) Power-up USB_VBUS, USB_AVDD_CORE, USB_AVDD_IO and
USB_AVDD_IO_HV in any order.
o There are no timing limitations (minimum or maximum) when
powering-up multiple power supplies.
o Between the supplied and VBUS – there is no specific ramp up,
and VBUS can be present in cases when there are both supplies
and are no supplies provided to the USB 2.01 1
6. Enable reference clock after VDDIO reached final voltage level.

1
T12 requirement derived from PCI Express Specification Rev 3.0, Section 2.6.2. AC Specifications:

“De-asserted NRESET such having enough margin to the end point enter LTSSM Detect State within 20
ms of the end of Fundamental Reset (PERSTn) , and 100ms before system sending a Configuration
Request to the device”.

2
On PCIe Only configuration – x_AVDD can be derived from with VDD_CORE, and x_AVDDH can be
derived from VDDIO. Refer to 3.1.2.2 PCIe Only (Minimum Configuration).

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 Hailo-8L™ Datasheet Rev.1.5

7. De-assert NRESET after clock is stable for 10 cycles. clock is stable

when it meets the requirements for CLK_IN.
8. For PCIe application: De-assert NRESET before or up to 500us PCIe
PERST is de-asserted. For non-PCIe application: Add 1K-2K PU on
PERSTn

Figure 4: Power-up Sequence

Table 15: Power-up Sequence Timing Requirements

Description Min Nom Max Unit

T1 VDDIO to VDD_CORE and VDD_TOP 1 - - us
T2 VDD_CORE to PCIE_AVDD_H 1 - - us
T3 VDD_CORE to PCIE_AVDD_C 1 - - us
T4 VDD_CORE to PCIE_AVDD_D 1 - - us
T5 VDD_CORE to CSI_AVDD_H 1 - - us
T6 VDD_CORE to CSI_AVDD 1 - - us
T7 VDD_CORE to USB_AVDD_CORE 1 - - us
T8 VDD_CORE to USB_AVDD_IO 1 - - us
T9 VDD_CORE to USB_AVDD_IO_HV 1 - - us
T10 VDDIO to Stable Clock 1 - - ms
T11 Stable CLK to RESET_N de-assertion 100 - - us
T12 VDDIO to RESET_N de-assertion - - 70 ms

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 Hailo-8L™ Datasheet Rev.1.5

4.4. Power Consumption

4.4.1 Maximum Supply Current
The maximum current that can be drawn from each power rail is
application-dependent. The measurements in Table 16 were made during
device characterization and represent worst-case results across all PVT
corners. The numbers are provided here only as general guidelines for
power supply design.
Table 16: Maximum Supply Current

Supply Name Max Current Unit

VDD_CORE1 7.2 A

VDD_TOP 1 A
VDDIO2
0.3 A

VDDIO_SDIO3 60 (4) mA

CSI0_RX_AVDD 25 mA

CSI0_RX_AVDDH 30 mA

CSI1_RX_AVDD 25 mA

CSI1_RX_AVDDH 30 mA

CSI0_TX_AVDD 100 mA

CSI0_TX_AVDDH 14 mA

1 The maximum current assumes heavy compute networks, for lowering the values, if needed, please
evaluate the specific neural model and SoC integration for the specific network and add an adequate
margin to cover all PVT corners and current spikes.
1
2 𝑉𝐷𝐷𝐼𝑂[𝑉] ∙ ∑𝐼𝑂𝑖 (𝐶𝑖 [𝐹] ∙ ∙ 𝑓𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 [𝐻𝑧]) Each IO_i drives a capacitance C_i[F] and is switched from 1 to
2
0 and vice versa at a frequency of 0.5f[Hz]. Add C_i[F]x0.5f[Hz] of all the IOs and multiply this sum by
the VDDIO[V] voltage rail to obtain the VDDIO current consumption I_VDDIO[A].

3 For 1.8V IO power rail

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 Hailo-8L™ Datasheet Rev.1.5

Supply Name Max Current Unit

CSI0_TX_AVDD_CLK 10 mA

CSI1_TX_AVDD 100 mA

CSI1_TX_AVDDH 14 mA

CSI1_TX_AVDD_CLK 10 mA

PCIE_AVDD_D 280 mA

PCIE_AVDD_C 180 mA

PCIE_AVDD_H 21 uA

USB_AVDD_CORE 7 mA

USB_AVDD_IO 17 mA

USB_AVDD_IO_HV 1.1 mA

PLL_AVDD 1.2 mA

AVDD_TS 0.5 mA

AVDD_VS 0.3 mA

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 Hailo-8L™ Datasheet Rev.1.5

4.4.2 Supply Current in Selected Test Cases

TBD

4.4.3 Power Modes

When powered on, Hailo-8L can be operated in fully functional, normal
mode or in any of three low-power modes: doze, sleep and hibernate.
Doze, sleep and hibernate modes are designed to help system integrators
to optimally manage the exit latency vs. power tradeoff.
• Doze mode retains all memory and register-stored data to minimize
reconfiguration time. The PLL remains powered-on to eliminate PLL
lock time. Unused logic is clock-gated, and analog macros are held in
the protocols’ relevant low power states.
• Sleep mode minimizes power consumption more than Doze mode by
powering off the PLL and the NN Core logic. This significantly reduces
power requirements but requires additional wake-up time for PLL
stabilization and register reconfiguration.
• Hibernate is the most aggressive low-power mode. It powers off NN
Core memories in addition to NN Core logic and the PLL, requiring
complete reconfiguration at wake-up.
See Table 17 for the power values of the three low-power modes.
Table 17: Low-Power Modes, Power Consumption

Power Consumption
Mode
VDD_CORE + VDD_TOP [mW]

Doze TBD

Sleep TBD

Hibernate TBD

Note: VDDIO and all MIPI power rails can only be powered off when the
SoC is powered off.

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4.5. Digital I/O DC Characteristics

There are two groups of I/O types:
Failsafe I/Os with strong PU/PD: Signals using this I/O type are:
PCIE_PERST_N, PCIE_CLKREQ_N, PCIE_WAKE_N, GPIO0, GPIO1, CLK_IN and
NRESET.
Regular I/Os: All other GPIOs use this I/O type.
Table 18 describes the DC characteristics of the failsafe digital pins as
characterized across all PVT corners.

Table 18: Failsafe Digital Pin DC Characteristics

Symbol Parameter Min Typ Max Unit

VIL Input Low Voltage -0.3 0.35*VDD_IO V

VIH Input High Voltage 0.65*VDD_IO 1.98 V

VT Threshold Point 0.91 1 1.13 V

VT+ Schmitt Trigger Low to 0.97 1.09 1.2 V

High Threshold Point

VT- Schmitt Trigger High to 0.75 0.86 0.97 V

Low Threshold Point

VTPU Threshold point with 0.82 0.95 1.07 V

Pull-Up Resistor Enabled

VTPD Threshold point with 0.91 1.01 1.14 V

Pull-Down Resistor
Enabled

VT+PU Schmitt Trigger Low to 0.87 1 1.13 V

High Threshold Point
with Pull-Up Resistor
Enabled

VT-PU Schmitt Trigger High to 0.69 0.8 0.92 V

Low Threshold Point

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Symbol Parameter Min Typ Max Unit

with Pull-Up Resistor
Enabled

VT+PD Schmitt Trigger Low to 0.98 1.09 1.22 V

High Threshold Point
with Pull-Down Resistor
Enabled

VT-PD Schmitt Trigger High to 0.75 0.86 0.98 V

Low Threshold Point
with Pull-Down Resistor
Enabled

IL Input Leakage Current @ +/-10 uA

Vi=1.8V or 0V

IOZ Tri-State Output Leakage +/-10 uA

Current @ Vi=1.8V or 0V

RPU Pull-Up Resistor 31 46 84 KΩ

RPD Pull-Down Resistor 31 44 71 KΩ

VOL Output Low Voltage 0.45 V

VOH Output High Voltage 1.35 V

C Output/Input - 1.05 - pF
capacitance

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Table 19 describes the DC characteristics of the regular GPIOs pins, as

characterized across all PVT corners.
Table 19: Regular GPIOs DC Characteristics

Symbol Parameter Min Typ Max Unit

VIL Input Low Voltage -0.3 0.35*VDD_IO V

VIH Input High Voltage 0.65*VDD_IO 1.98 V

VT Threshold Point 0.82 0.92 1 V

VT+ Schmitt Trigger Low to 0.98 1.1 1.21 V

High Threshold Point

VT- Schmitt Trigger High to 0.74 0.82 0.9 V

Low Threshold Point

VTPU Threshold point with 0.82 0.91 1 V

Pull-Up Resistor Enabled

VTPD Threshold point with 0.83 0.93 1.02 V

Pull-Down Resistor
Enabled

VT+PU Schmitt Trigger Low to 0.97 1.09 1.2 V

High Threshold Point
with Pull-Up Resistor
Enabled

VT-PU Schmitt Trigger High to 0.73 0.81 0.89 V

Low Threshold Point
with Pull-Up Resistor
Enabled

VT+PD Schmitt Trigger Low to 0.99 1.11 1.22 V

High Threshold Point
with Pull-Down Resistor
Enabled

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Symbol Parameter Min Typ Max Unit

VT-PD Schmitt Trigger High to 0.75 0.83 0.91 V

Low Threshold Point
with Pull-Down Resistor
Enabled

IL Input Leakage Current @ +/-10 uA

Vi=1.8V or 0V

IOZ Tri-State Output Leakage +/-10 uA

Current @ Vi=1.8V or 0V

RPU Pull-Up Resistor 17 24 40 KΩ

RPD Pull-Down Resistor 17 23 36 KΩ

VOL Output Low Voltage 0.45 V

VOH Output High Voltage 1.35 V

C Output/Input - 0.88 - pF
capacitance for all other
pads

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4.6. PCIE Characteristics (DC And AC)

The following tables describe the PCIe characteristics as characterized
across all PVT corners.
Table 20: PCIe Gen1 Transmitter Characteristics

Parameter Description Min Max Unit

Differential peak-peak Tx voltage

VTX-DIFF-PP 876 1130 mV
swing for full swing operation

Differential peak-peak Tx voltage

VTX-DIFF-PP-LOW 489.33 669.19 mV
swing for low swing operation

LTX-SKEW Lane-to-Lane Output Skew - 0.438 ns

Table 21: PCIe Gen2 Transmitter Characteristics

Parameter Description Min Max Unit

Differential peak-peak Tx voltage

VTX-DIFF-PP 810 1070 mV
swing for full swing operation

Differential peak-peak Tx voltage

VTX-DIFF-PP-LOW 445 625 mV
swing for low swing operation

LTX-SKEW Lane-to-Lane Output Skew - 0.235 ns

Table 22: PCIe Gen3 Transmitter Characteristics

Parameter Description Min Max Unit

Differential peak-peak Tx voltage

VTX-DIFF-PP 800 1010 mV
swing for full swing operation

Differential peak-peak Tx voltage

VTX-DIFF-PP-LOW 401 547 mV
swing for low swing operation

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Parameter Description Min Max Unit

Minimum voltage swing

VTX-EIEOS-FS 262 - mVPP
during EIEOS for full swing signaling

Minimum voltage swing during

VTX-EIEOS-RS 256 - mVPP
EIEOS for reduced swing signaling

LTX-SKEW Lane-to-Lane Output Skew - 0.438 ns

Table 23: PCIe Transmitter Data Rate Independent Characteristics

Parameter Description Min Max Unit

Tx AC peak-peak common mode

VTX-AC-CM-PP - 134 mVPP
voltage

Tx DC peak-peak common mode

VTX-DC-CM 0.396 0.404 V
voltage

VTX-CM-DC-LINE- Absolute Delta of DC Common

2.1 7.2 mV
DELTA Mode Voltage between D+ and D-

Electrical Idle Differential Peak

VTX-IDLE-DIFF-AC-p 8.09 19.98 mV
Output Voltage

DC Electrical Idle Differential Output

VTX-IDLE-DIFF-DC 0.1 1.4 mV
Voltage

ZTX-DIFF-DC DC differential Tx impedance 69.2 75.3 Ω

Table 24:PCIe Receiver Electrical Idle Detect Threshold

Parameter Description Min Max Unit

VRX-IDLE-DET-DIFF-
Electrical Idle Detect threshold 92 154 mV
PP

Table 25:PCIe Receiver Termination Characteristics

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Parameter Description Min Max Unit

Receiver DC single ended

ZRX-DC 49.7 54.9 Ω
impedance

ZRX-HIGH-IMP-DC- DC input CM input impedance for

53k - Ω
POS (0-200 mV) V≥0 during Reset or power-down

ZRX-HIGH-IMP-DC- DC input CM input impedance for

144k - Ω
POS (> 200 mV) V≥0 during Reset or power-down

ZRX-HIGH-IMP-DC- DC input CM input impedance

4.6k - Ω
NEG for V<0 during Reset or power-down

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4.7. MIPI DPHY RX Characteristics

The following tables describe the MIPI RX DPHY characteristics as
characterized across all PVT corners.
Table 26: MIPI RX DPHY Clock Lane LP Voltage and Timing Characteristics

Parameter Description Value Unit

LP-RX Logic 1 Input Minimum voltage level where LP

665 mV
Voltage (VIH) receiver consistently detects Logic 1

LP-RX Logic 0 Input Maximum voltage level where non-

Voltage, Non-ULP ULP LP receiver consistently detects 605 mV
State (VIL) Logic 0

LP-RX Input
Maximum Logic 1 hysteresis 25 mV
Hysteresis (VHYST)

LP-RX Minimum
Pulse Width Maximum Pulse width which LP
15 ns
Response (TMIN- receiver can detect without any error.
RX)

Table 27: MIPI RX DPHY Data Lane LP Voltage and Timing Characteristics

Parameter Description Value Unit

LP-RX Logic 1 Input Minimum voltage level where LP

665 mV
Voltage (VIH) receiver consistently detects Logic 1

LP-RX Logic 0 Input Maximum voltage level where non-

Voltage, Non-ULP ULP LP receiver consistently detects 605 mV
State (VIL) Logic 0

LP-RX Input
Maximum Logic 1 hysteresis 25 mV
Hysteresis (VHYST)

LP-RX Minimum
Maximum Pulse width which LP
Pulse Width c 15 ns
receiver can detect without any error
(TMIN-RX)

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Table 28: MIPI RX DPHY HS DC Differential Input Impedance

Parameter Description Value Unit

Data Lane: DC Differential Input

100.1/122.9 Ohm
HS-RX DC Differential Impedance (ZID)
Input Impedance
(ZID) Clock Lane: DC Differential Input
102.9/117.1 Ohm
Impedance (ZID)

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4.8. MIPI DPHY TX Characteristics

The following tables describe the MIPI TX DPHY characteristics as
characterized across all PVT corners.

4.8.1 LP Characteristics
Table 29: MIPI TX DPHY Data Lane LP DC Characteristics

Parameter Conditions Min Typ Max Unit

Data Lane LP-TX

Thevenin output high CLOAD = 70 pF 0.969 1.153 1.217 V
voltage level (VOH)

Data Lane LP-TX

Thevenin Output Low CLOAD = 70 pF -35 -0.87 49 mV
Level Voltage (VOL)

Table 30: MIPI TX DPHY Data Lane LP AC Characteristics

Parameter Conditions Min Typ Max Unit

Data Lane LP-TX 15%-

CLOAD = 70 pF 18.136 21.02 ns
85% Rise Time (TRLP)

Data Lane LP-TX 15%-

CLOAD = 70 pF 17.66 22.04 ns
85% Fall Time (TFLP)

Data Lane LPTX

Runtime XOR Clock
CLOAD = 70 pF 21.18 34.49 ns
Pulse Width (TLP-
PULSE-TX)

Data Lane LPTX

Runtime XOR Clock
CLOAD = 70 pF 47.91 49.71 ns
Pulse Width (TLP-
PULSE-TX) (Initial)

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Parameter Conditions Min Typ Max Unit

Data Lane LP-TX

Period of Exclusive-OR CLOAD = 70 pF 92.83 97.06 ns
Clock (TLP-PER-TX)

Data Lane Slew Rate

CLOAD = 70 pF 115.9 mV/ns
Max

Data Lane Slew Rate

CLOAD = 70 pF 26.34 36.238 mV/ns
Min

Data Lane Slew Rate

CLOAD = 70 pF 0.19 9.352 mV/ns
Margin

Table 31: MIPI TX DPHY Clock Lane LP DC Characteristics

Parameter Conditions Min Typ Max Unit

Clock Lane LP-TX

Thevenin output High CLOAD = 70 pF 1.036 1.185 1.23 V
Voltage Level (VOH)

Clock Lane LP-TX

Thevenin Output Low CLOAD = 70 pF -36 -16.6 30 mV
Level Voltage (VOL)

Table 32: MIPI TX DPHY Clock Lane LP AC Characteristics

Parameter Conditions Min Typ Max Unit

Clock Lane LP-TX 15%-

CLOAD = 70 pF 18.27 23.23 ns
85% Rise Time (TRLP)

Clock Lane LP-TX 15%-

CLOAD = 70 pF 17.38 19.75 ns
85% Fall Time (TFLP)

Clock Lane Slew Rate

CLOAD = 70 pF 113.98 mV/ns
Max

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Parameter Conditions Min Typ Max Unit

Clock Lane Slew Rate

CLOAD = 70 pF 34.57 mV/ns
Min

Clock Lane Slew Rate

CLOAD = 70 pF 0.29 mV/ns
Margin

4.8.2 HS Characteristics
Table 33: MIPI TX DPHY Data Lane HS DC Characteristics

Parameter Conditions Min Typ Max Unit

HS Data TX Differential
-263.4 -212 -176.5 mV
Voltage (VOD(0) Pulse)

HS Data TX Differential
170.16 201.91 268.61 mV
Voltage (VOD(1) Pulse)

Data Lane HS-TX

Differential Voltage -13.93 2.73 mV
Mismatch (ΔVOD)

Data Lane HS-TX Single

Ended Output High Termination=80,100, 293.36 349.73 mV
Voltage (VOHHS) 125 Ω
Data rate =
Data Lane HS-TX Static
2.5G,1G,1.5G,80Mbps
Common-Mode 158.9 172.7 248.27 mV
Voltage (VCMTX)

Data Lane HS-TX Static

Common-Mode
4.92 mV
Voltage Mismatch
(ΔVCMTX)

Data Lane HS-TX

Dynamic Common- 9.02 23.15 mVPEAK
Level Variations
Between 50-450MHz

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Parameter Conditions Min Typ Max Unit

(ΔVCMTX(LF))

Data Lane HS-TX

Dynamic Common-
Level Variations Above 5.63 11.21 mVrms
450MHz
(ΔVCMTX(HF))

Table 34: MIPI TX DPHY Data Lane HS AC Characteristics

Parameter Conditions Min Typ Max Unit

Data Lane HS-TX

20%-80% Rise time 153.64 248.37 356.51 ps
tR (bit rate <=1Gbps)

Data Lane HS-TX

20%-80% Rise time 146.08 179.76 249.23 ps
tR (bit rate >1Gbps)

Data Lane HS-TX

20%-80% Rise time
105.55 124.24 145.73 ps
tR (bit rate >1.5
Termination=80,100,125
Gbps)
Ω
Data rate =
Data Lane HS-TX
2.5G,1G,1.5G,80Mbps
80%-20% Fall time 182.27 248.4 356.13 ps
tR (bit rate< = 1Gbps)

Data Lane HS-TX

80%-20% Fall time 145.55 179.34 240.22 ps
tR (bit rate >1Gbps)

Data Lane HS-TX

80%-20% Fall time
107.14 125.83 148.87 ps
tR (bit rate > 1.5
Gbps)

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Table 35: MIPI TX DPHY Clock Lane HS DC Characteristics

Parameter Conditions Min Typ Max Unit

HS Clock TX
Differential
Voltage(VOD(0)
Pulse)

HS Clock TX
Differential
159.53 192.13 245.06 mV
Voltage(VOD(1)
Pulse)

Clock Lane HS-TX

Differential Voltage -13.9 8.65 mV
Mismatch (ΔVOD)

Clock Lane HS-TX

Single Ended Output Termination=80,100,125
269.2 345.8 mV
High Voltage Ω
(VOHHS) Data rate =
2.5G,1G,1.5G,80Mbps
Clock Lane HS-TX
Static Common-
179.74 188.87 243.68 mV
Mode Voltage
(VCMTX)

Clock Lane HS-TX

Static Common-
1.01 3.84 mV
Mode Voltage
Mismatch (ΔVCMTX)

Clock Lane HS-TX

Dynamic Common-
Level Variations 7.53 23.54 mVPEAK
Between 50-450MHz
(ΔVCMTX(LF))

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Parameter Conditions Min Typ Max Unit

Clock Lane HS-TX

Dynamic Common-
Level Variations 5.53 11.77 mVrms
Above 450MHz (Δ
VCMTX(HF))

Table 36: MIPI TX DPHY Clock Lane HS AC Characteristics

Parameter Conditions Min Typ Max Unit

Clock Lane HS-TX

20%-80% Rise time 186.29 232.91 296.69 ps
tR (bit rate <=1Gbps)

Clock Lane HS-TX

20%-80% Rise time 144.94 171.32 243.25 ps
tR (bit rate > 1Gbps)

Clock Lane HS-TX

20%-80% Rise time
112.54 128.45 159.25 ps
tR (bit rate > 1.5
Termination=80,100,125
Gbps)
Ω
Data rate =
Clock Lane HS-TX
2.5G,1G,1.5G,80Mbps
80%-20% Fall time 188.54 231.1 292.18 ps
tR (bit rate< = 1Gbps)

Clock Lane HS-TX

80%-20% Fall time 143.11 168.71 241.65 ps
tR (bit rate > 1Gbps)

Clock Lane HS-TX

80%-20% Fall time
110.12 129.1 157.89 ps
tR (bit rate > 1.5
Gbps)

Table 37: MIPI TX DPHY Data Lane HS AC Characteristics

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Parameter Conditions Min Typ Max Unit

Data Lane HS-TX

Single Ended Output 40.61 51.75 55.92 Ω
impedance (ZOS)

Clock Lane HS-TX

Single Ended Output 40.67 49.25 53.58 Ω
impedance (ZOS)

Data Lane Single

Ended Output
1.06 9.94 %
Impedance
Termination=80,100,125
Mismatch (delta ZOS)
Ω
Data rate =
Clock Lane Single
2.5G,1G,1.5G,80Mbps
Ended Output
0.65 9.66 %
Impedance
Mismatch (delta ZOS)

Data Lane LP-TX

Output Impedance 117.34 136.55 Ω
(ZOLP)

Clock Lane LP-TX

Output Impedance 116.31 135.05 Ω
(ZOLP)

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4.9. USB Characteristics

The following tables describe the USB PHY characteristics as characterized
across all PVT corners.

4.9.1 HS Characteristics
Table 38: USB PHYHS Transmitter – DC Characteristics

Parameter Symbol Min Typ Max Unit

Idle Level VIdle -2.3 -1.5 -0.9 mV

Low Level VOL -2.4 -1.6 -0.9 mV

Device Chirp K Dev CK -742 -663 -604 mV

Host Chirp K Host CK -896 -808 -759 mV

Host Chirp J Host CJ 807 854 940 mV

Table 39: USB PHY HS Transmitter – AC Characteristics

Parameter Symbol Min Typ Max Unit

Signal Rate SR 479.99 480.01 480.03 Mbps

Rising Edge Rate RER 990 1127 V/us

Falling Edge Rate FER 990 1127 V/us

Rise Time RT 567 646 ps

Fall Time FT 567 646 ps

EOP Width EOPW 7.86 7.89 7.92 bits

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4.9.2 FS Characteristics
Table 40: USB PHY FS Transmitter – DC Characteristics

Parameter Symbol Min Typ Max Unit

Low Level (Idle) VOL 0.005 0.05 V

Low Level (Driven) VOL 0.03 0.07 V

High Level (Driven) VOH 2.95 3.26 3.57 V

Crossover Voltage VCRS 1.17 1.49 1.83 V

Table 41: USB PHY FS Transmitter – AC Characteristics

Parameter Symbol Min Typ Max Unit

Signal Rate TFDRATHS 11.995 12 12.005 Mbps

Rise Time TFR 9.8 11.5 13.5 ns

Fall Time TFF 10.5 12.7 14.9 ns

Rise Fall Matching TFRFM 90 91.5 93.4 %

Consecutive Jitter TDJ1 -891 -18 603 ps

Paired JK Jitter TDJ2 -963 81 967 ps

Paired KJ Jitter TDJ2 -518 62 806 ps

EOP Width TFEOPT 166 166.5 167 ns

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Table 42: USB PHY FS Single-Ended Receiver – DC Characteristics

Parameter Symbol Min Typ Max Unit

Input High Level

VIH 2 V
(Driven)

Input Low Level VIL 0.8 V

Differential Input
VDI 0.2 V
Sensitivity

Differential Common
VCM 1.7 V
Mode Range

Table 43: USB PHY FS Single-Ended Receiver – AC Characteristics

Parameter Symbol Min Typ Max Unit

Jitter (to Next

TJR1 -18.5 18.5 ns
Transition)

Jitter (Paired
TJR2 -9 9 ns
Transition)

4.9.3 LS Characteristics
Table 44: USB PHY LS Transmitter – DC Characteristics

Parameter Symbol Min Typ Max Unit

Low Level (Idle) VOL 0.005 0.056 V

Low Level (Driven) VOL 0.03 0.07 V

High Level (Driven) VOH 2.95 3.26 3.56 V

Rise Time TR 113 132 151 ns

Fall Time TF 116 142 165 ns

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Table 45: USB PHY LS Transmitter – AC Characteristics

Parameter Symbol Min Typ Max Unit

Rise Fall Matching TLRFM 94.4 97.42 99.6 %

Signal Rate TLDRATHS 1.5 1.5 1.5 Mbps

Crossover Voltage VCRS 1.35 1.52 1.72 V

Consecutive Jitter
Consecutive Jitter-UP -3.5 0.3 3.6 ns
(Upstream)

Paired JK Jitter
Paired JK Jitter-UP -3.4 0.2 3.1 ns
(Upstream)

Paired KJ Jitter
Paired KJ Jitter-UP -2.6 0.1 2.6 ns
(Upstream)

Consecutive Jitter Consecutive Jitter-

-3.5 0.3 3.6 ns
(Downstream) Down

Paired JK Jitter
Paired JK Jitter-Down -3.4 0.2 3.1 ns
(Downstream)

Paired KJ Jitter
Paired KJ Jitter-Down -2.6 0.1 2.6 ns
(Downstream)

EOP Width TLEOPT 1.33 1.33 1.34 us

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Table 46: USB PHY LS Single-Ended Receiver – DC Characteristics

Parameter Symbol Min Typ Max Unit

Input High Level

VIH 2 V
(Driven)

Input Low Level VIL 0.8 V

Differential Input
VDI 0.2 V
Sensitivity

Differential Common
VCM 1.7 V
Mode Range

Table 47: USB PHY LS Single-Ended Receiver – AC Characteristics

Parameter Symbol Min Typ Max Unit

Jitter (to Next

TJR1 -152 152 ns
Transition)

Jitter (Paired
TJR2 -199 199 ns
Transition)

4.9.4 Termination Characteristics

Table 48: USB PHY Termination Characteristics

Parameter Symbol Min Typ Max Unit

Pullup Resistance (Idle

RPU2 1.2 1.3 1.3 kΩ
Bus)

Pullup Resistance
RPU1 2.1 2.1 2.2 kΩ
(Active Bus)

Pulldown Resistance RPD 14.5 18.7 19.1 kΩ

Input Impedance ZINP 434.4 kΩ

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Parameter Symbol Min Typ Max Unit

FS Output Impedance ZFSDRV 43.9 45.2 46.5 Ω

HS Output Impedance ZHSDRV 43.1 44.2 45.4 Ω

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4.10. SDIO Characteristics

The following tables describe the SDIO PHY characteristics as
characterized across all PVT corners.
Table 49: SDIO Receiver Thresholds - 1.8V

Parameter Min Typ Max Unit

Rx Type 1.8V Schmitt

0.81 - 1.054 V
Trigger Assertion

Rx Type 1.8V Schmitt

0.772 - 1.009 V
Trigger De-assertion

Rx Type 1.8V Schmitt

0.037 - 0.064 V
Trigger Hysteresis

Rx Type 1.8V
Comparator Vth 0.787 - 0.998 V
Assertion

Rx Type 1.8V
Comparator Vth De- 0.797 - 1.002 V
assertion

Table 50: SDIO Receiver Thresholds - 1.2V

Parameter Min Typ Max Unit

Rx Type 1.2V Schmitt

0.533 - 0.713 V
Trigger Assertion

Rx Type 1.2V Schmitt

0.529 - 0.71 V
Trigger De-assertion

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Parameter Min Typ Max Unit

Rx Type 1.2V Schmitt

-0.001 - 0.007 V
Trigger Hysteresis

Rx Type 1.2V
0.556 - 0.711 V
Comparator Assertion

Rx Type 1.2V
Comparator De- 0.56 - 0.715 V
assertion

Table 51: SDIO Receiver Duty Cycle

Parameter Min Typ Max Unit

Duty Cycle Rx Type

49.214 - 54.017 %
1.8V Schmitt Trigger

Duty Cycle Rx Type

46.036 - 50.69 %
1.8V Comparator Vth

Duty Cycle Rx Type

47.402 - 54.005 %
1.2V Schmitt Trigger

Duty Cycle Rx Type

47.143 - 53.417 %
1.2V Comparator Vth

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Table 52: SDIO IO Leakage

Parameter Conditions Min Typ Max Unit

Internal pull-up and

PHY 1.8V Instance IO
pull-down -0.81 - 0.036 uA
Leakage
resistors disconnected

Internal pull-up and

PHY 1.2V Instance IO
pull-down -1.06 - 0.277 uA
Leakage
resistors disconnected

Table 53: SDIO TX Impedance - DC

Parameter Conditions Min Typ Max Unit

PHY 1.8V Instance Pull-up 48.937 - 62.474 Ohm

Driver Strength:
50 Ohm Pull-down 49.57 - 64.677 Ohm

PHY 1.2V Instance Pull-up 47.421 - 65.557 Ohm

Driver Strength:
50 Ohm Pull-down 47.157 - 71.184 Ohm

PHY 1.8V Instance Pull-up 39.55 - 50.488 Ohm

Driver Strength:
40 Ohm Pull-down 39.954 - 52.047 Ohm

PHY 1.2V Instance Pull-up 38.324 - 52.949 Ohm

Driver Strength:
40 Ohm Pull-down 38.01 - 57.166 Ohm

Table 54: SDIO TX Capacitance - AC

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Parameter Conditions Min Typ Max Unit

PHY 1.8V Instance Pull-up 3.443 - 4.228 pf

Driver Strength:
50 Ohm Pull-down 3.448 - 4.212 pf

PHY 1.2V Instance Pull-up 3.061 - 4.277 pf

Driver Strength:
50 Ohm Pull-down 3.075 - 4.269 pf

PHY 1.8V Instance Pull-up 2.163 - 3.435 pf

Driver Strength:
40 Ohm Pull-down 2.111 - 3.413 pf

PHY 1.2V Instance Pull-up 1.72 - 3.564 pf

Driver Strength:
40 Ohm Pull-down 1.712 - 3.552 pf

Table 55: SDIO TX VOH/VOL

Parameter Conditions Min Typ Max Unit

PHY 1.8V Instance

Output High Voltage Pull-up 1.508 - 1.886 V
(50 Ohm)

PHY 1.8V Instance

Output Low Voltage Pull-down 0.09 - 0.112 V
(50 Ohm)

PHY 1.8V Instance

Output High Voltage Pull-up 1.53 - 1.904 V
(50 Ohm)

PHY 1.8V Instance

Output Low Voltage Pull-down 0.073 - 0.09 V
(50 Ohm)

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Parameter Conditions Min Typ Max Unit

PHY 1.2V Instance

Output High Voltage Pull-up 0.968 - 1.231 V
(50 Ohm)

PHY 1.2V Instance

Output Low Voltage Pull-down 0.087 - 0.111 V
(50 Ohm)

PHY 1.2V Instance

Output High Voltage Pull-up 0.99 - 1.248 V
(40 Ohm)

PHY 1.2V Instance

Output Low Voltage Pull-down 0.07 - 0.09 V
(40 Ohm)

Table 56: SDIO TX Weak Pull-up/Pull-down

Parameter Conditions Min Typ Max Unit

Weak pull-up drive

PHY 1.8V Instance 37.878 - 41.933 KOhm
Strength =50 ohm

Weak pull-down. drive

PHY 1.8V Instance 38.032 - 41.476 KOhm
strength =50 ohm

Weak pull-up. drive

PHY 1.2V Instance 39.185 - 45.752 KOhm
strength = 50 ohm

Weak pull-down. drive

PHY 1.2V Instance 39.254 - 44.99 KOhm
strength = 50 ohm

Table 57: SDIO Transmitter Rise/Fall Times and Duty-Cycle

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Parameter Conditions Min Typ Max Unit

PHY 1.8V Instance

Transmitter Rise/Fall 0.822 - 1.263 ns/ns
Time Ratio

PHY 1.2V Instance

Transmitter Rise/Fall Drive strength = 50 Ohm. 0.849 - 1.014 ns/ns
Time Ratio Slew rate control =
fastest
PHY 1.8V Instance
0.482 - 0.971 ns
Transmitter Rise Time

PHY 1.2V Instance

0.551 - 0.751 ns
Transmitter Rise Time

PHY 1.8V Instance

0.563 - 0.795 ns
Transmitter Fall Time Drive strength = 50 Ohm.
Slew rate control =
fastest
PHY 1.2V Instance
0.578 - 0.836 ns
Transmitter Fall Time

PHY 1.8V Instance

47.327 - 54.171 %
Transmitter Duty Cycle Drive strength = 50 Ohm.
Slew rate control =
PHY 1.2V Instance fastest
48.752 - 54.175 %
Transmitter Duty Cycle

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Table 58: SDIO Delay Line Open-Loop

Parameter Conditions Min Typ Max Unit

Delay Line Total Delay VDD_TOP = 0.8V,

5.355 - 9.269 ns
of Variable Delay Chain1 dl_step=0

Delay Line Average VDD_TOP = 0.8V,

42.382 - 73.59 ps
Step Size1 dl_step=0

1
The Delay Line Open-Loop characterization test is intended to accurately measure the delay per each
programmed delay line code. For this purpose, all the 128 delay codes have been swept and the
respective step measured under nominal VT conditions. This characterization has been made
exclusively on Delay Line 1. The values included in the tables refer to the highest respective code delay
for all the samples.

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4.11. RGMII Characteristics

Meeting the timing requirements of the RGMII interface, as described
here, is crucial for proper operation when interfacing RGMII compliant
devices.
Table 59: RGMII Timing Requirements

Parameter Description Min Typical Max Unit

T_cyc1 Clock cycle duration 7.2 8 8.8 ns

Duty_G2 Duty cycle for Gigabit mode 45 50 55 %

Duty_T2 Duty cycle for 100T mode 40 50 60 %

Data to clock output skew at

TskewT3 -500 0 500 ps
transmitter

Data to clock input skew at

TskewR3 1 1.8 2.6 ns
receiver

Tr / Tf Rise/Fall time 20-80% - - 0.75 ns

See the Hardware Integration Guide for further design guidelines.

1
For 100Mbps, Tcyc will scale to 40ns+-4ns.

2
The duty cycle may be stretched/shrunk during speed changes or while transitioning to a received
packet's clock domain on condition that the minimum duty cycle is not violated and stretching occurs
for no more than three Tcyc of the lowest transitioning speed.

3
This applies to all versions of RGMII prior to 2.0. This implies that PC board design will require clocks to
be routed with an additional trace delay of greater than 1.5ns and less than 2.0ns, to be added to the
associated clock signal. For 100Mbps, the maximum value is unspecified.

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TXC
(at transmitter)
Tskew_T

TXD [8:5][3:0] TXD [8:5]

TXD[3:0]
TXD [7:4][3:0] TXD [7:4]

TXD[4] TXD [9]

TX_CTL
TXEN TXERR

TXC
Tskew_R
(at Receiver)

Figure 5: RGMII Multiplexing & Timing Diagram – TX signals

RXC
(at transmitter)
Tskew_T

RXD [8:5][3:0] RXD [8:5]

RXD[3:0]
RXD [7:4][3:0] RXD [7:4]

RXD[4] TXD [9]

RX_CTL
RXDV RXERR

RXC
(at Receiver) Tskew_R

Figure 6: RGMII Multiplexing & Timing Diagram – RX Signals

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4.12. Reset Characteristics

The NRESET pad should be driven by a Reset signal that meets the
following requirements to provide Hailo-8L with a proper Reset pulse:
Rise and fall time (measured between 20% and 80% of VDDIO) < 5ns
NRESET assertion time (held low) >28us.

NRESET

<5ns >28usec <5ns

Figure 7: Reset Characteristics

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5. Detailed Description
This section describes various system modes and usage scenarios, and
provides detailed information on various Hailo-8L subsystems.
See Hailo SW documentation for further elaboration.
https://hailo.ai/developer-zone/documentation/

5.1. System Modes and Usage Scenarios

5.1.1 Hailo-8L as a Companion Device
In companion mode, depicted in Figure 8, Hailo-8L is used to efficiently
offload Neural Network workload from the host application processor. It
receives inference data and returns insights. Hailo-8L typically
communicates with the application processor over PCIe.

Figure 8: Hailo-8L as a Companion Device

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5.2. Bootstraps
Hailo-8L has one functional boot strap, called BS_IO_SEL[0] (multiplexed
with I2S_SDO), to enable the selection between two possible boot modes,
PCIe when Boot Strap is pulled up, or Flash when Boot Strap is pulled
down.
For PCIe boot, the SoC ROM handles the process with the host platform
that runs the Hailo RT PCIe driver. Firmware is then fetched over the PCIe
link to boot the device firmware.
For Flash boot, the SoC ROM fetches firmware from an on-board SPI flash
device to complete the boot process.
The integrator can select the desired boot-flow according to dedicated
system characteristics. See section 5.1 for further details.
See the Board Design Guidelines for further implementation and
bootstrap connectivity guidelines.

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5.3. NN Core
The Hailo-8L NN Core enables deployment of Deep NNs (DNNs) organized
in four internal functional units called clusters.
Key features include:
• Up to 13 TOPs, 8-bit precision
• Four clusters that can be used to deploy multiple NNs
o Compute, control and memory structure optimized for NN
primitives
o Fully programmable architecture to allow instantiation of all
common NN building blocks, based on available software support
delivered by the Hailo Dataflow Compiler (this includes, but is not
limited to, layers such as convolution, pooling, fully connected and
activation)
o Support for advanced NN architecture with native support for split,
concatenation and add layers
• Power modes
o Normal (fully functional), doze, sleep and hibernate
o Power shutdown can be executed at cluster level
• Up to 16 I/O channels to the NN core
• Configurable interconnect between NN core inputs, outputs and
pre/post units
• 8/16-bit precision for both weights and activations, configurable at
layer granularity
• 4-bit precision for weights, configurable at layer granularity
• NN pre/post processing hardware accelerator used to offload the
following functions from host:
o NMS engine
▪ Up to 128k proposals post score threshold
▪ One comparison per cycle, two NMS engines may be
aggregated to offer double throughput
▪ Configurable intersection over union and score
threshold with up to 16 threshold classes

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o Bilinear interpolation engine

▪ Streaming bilinear up to 8K resolution
▪ Crop and Resize operations
o Reshape engine
▪ Translates standardized formats to Hailo proprietary
format and vice versa
▪ Offloads advanced tensor reshape operations
o Softmax engine

5.4. High Bandwidth Interfaces

5.4.1 Ethernet
The Hailo-8L provides an IEEE-802.3-2002-compliant Media Access
Controller (MAC) for Ethernet LAN communications through an industry-
standard Reduced Gigabit Media-Independent Interface (RGMII) or
Reduced Media-Independent Interface (RMII). The Hailo-8L requires an
external physical interface device (PHY) to connect to the physical LAN bus
(twisted-pair, fiber, etc.). The MAC integrates a DMA, 1588 functionality,
TSN/AVB and PCS for automotive applications.
Key features include:
• 100, 1000 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers from the
dedicated SRAM throughout the
• Tagged MAC frame support (VLAN support)
• TCP/IP and UDP offload
• MAC control sublayer (control frames)
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast addresses
(multicast and group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit
FIFO and the receive FIFO are each 2 Kbytes (4 Kbytes total)
• Hardware Precision Time Protocol (PTP) in accordance with IEEE 1588

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2008 (PTP V2) with the time stamp comparator connected to the TIM2
input
• Time Stamping Unit (TSU) supports a 102-bit timer
• Credit Based Shaping - TSN, 802.1Qav
• Enhanced Scheduled Traffic - TSN, 802.1Qbv
• Frame Replication and Elimination for Reliability - TSN, 802.1CB

5.4.2 PCI Express (PCIe)

Hailo-8L provides a 4-lane PCI-SIG compliant PCIe gen 3 PHY and
controller, enabling it to be integrated as a PCIe endpoint. It integrates a
dedicated scatter-gather DMA for efficient memory mapped transactions.
Key features include:
• Up to 32 Gbps bi-directional throughput
o X1/X2/X4 lanes
o Supports link rate of 2.5, 5.0, 8.0 GT/s per lane
• Lane reversal support
• L1 PM Substates with CLKREQ
• Latency Tolerance Reporting (LTR)
• Single Physical Function
• Single Virtual Function
• Single Virtual Channel (VC)
• Up to 2.5𝜇𝑠 read latency from host memory in full BW
• Support also Device low power modes - D0, D3
• Up to 512 Byte maximum payload size
• Advanced Error Reporting (AER) support
• ECRC generation and check support
• MSI (up to 32) and INT message support
• Internal DMA (32 channels)
• Dynamic Scatter-Gather DMA configuration, such as interrupt
generation or start and end conditions for each specific SG page.
• Core Context switch over PCIe – configuration and data

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• FW boot from PCIe

• Control protocol
• Up to 16 dedicated RX and TX channels with low latency streaming
FIFOs
• Supports out of order TLP arrival with integrated re-order buffer
• Retransmit buffer of 2KB
• Receive buffer of 2KB
• Up to 32 outstanding read requests
• Integrated safety mechanisms that detect transient and permanent
faults in data and control paths
• Full support for link power management including ASPM L0, ASPM L1,
L1.1 andL1.2

5.4.3 MIPI CSI

Hailo-8L integrates two MIPI CSI-RX v1.3 controllers and DPHY v1.2 with
four lanes per DPHY, as well as two MIPI CSI-TX v1.3 controllers that are
also equipped with DPHY v1.2 with four lanes per DPHY. This allows easy
interfacing to sensors, displays and other SoCs. Each interface supports
up to 10 Gbps throughput, for a total streaming throughput of 40 Gbps.
The MIPI interfaces double as chip-to-chip interconnect, allowing a
seamless expansion to the Hailo-8L NN core.

5.4.3.1 CSI-RX
The CSI-RX subsystem allows efficient streaming of pixel data to the Hailo-
8L NN core. The CSI-RX is responsible for handling a CSI-2 protocol-based
camera sensor or sensor data stream, and for unpacking the payload data
and forwarding it to the pixel stream interfaces. The CSI-RX allows the
selection of multiple independent input streams and supports the control
of the destination for each stream (ISP or NN core).
Key features include:
• Operation modes:
o High-Speed (HS): maximum up to 2.5Gbps per lane
o Escape mode
▪ Remote triggers

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▪ LP-DT: up to 10Mbps
▪ ULPS mode
• Supports up to four streams for each interface over distinct virtual
channels and for different data types, which may be forwarded to
different destinations in the NN-Core or to the ISP.
• Supports the following data types:
o RAW6, RAW7, RAW8, RAW10, RAW12, RAW14
o RGB444, RGB555, RGB565, RGB666, RGB888
o YUV8, YUV10

5.4.3.2 CSI-TX
The CSI-TX subsystem can process pixel data from a source and generate
the CSI-2 data packets for short and long types. The CSI-TX also performs
ECC/CRC generation and provides data support for frame and line counter
packets.
The CSI-TX supports virtual channel and data type selection as well as all
primary data types defined by MIPI CSI-2.

5.4.3.3 DSI-TX
The DSI-TX subsystem is intended to interface NN Core output data with a
DSI compliant video mode display by embedding a DSI controller. This
controller can be multiplexed by static configuration to feed data into the
DPHY instead of using the CSI-TX controller.

5.4.4 Camera Parallel LVCMOS Interface

Hailo-8L integrates a camera parallel LVCMOS interface port of up to 24
bits wide at up to 100MHz, that connects to the video data bus from an
image sensor.

5.4.5 Universal Serial Bus (USB)

Hailo-8L contains an embedded USB full-speed device peripheral with
integrated transceivers. It is compliant with the USB 2.0 specification, has
software-configurable endpoint settings, and supports suspend/resume.
It requires a dedicated 48 MHz clock that is generated by a PLL connected
to the oscillator.

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Key features include:

• Combined RX and TX FIFO size of 320 × 35 bits with dynamic FIFO
sizing
• Supports the Session Request Protocol (SRP)
• 4 bidirectional endpoints
• 8 host channels with periodic OUT support

5.4.6 SDIO
SDI IF Key features include:
• Compliant with
o eMMC 5.1 (no backward support of HS400)
o SD6.0 1.8 V low voltage signaling (LVS) host
o JESD8-7a (1.2 V/1.8 V)
• Six I/O signals – eMMC (4-bit data) operation
• Three delay lines
• Glitch-free, power-sequence free operations
• Hi-Z I/O pad power-up default state
• Clock speeds up to 334MHz and data rate up to 667 MB/s
• SPI operation
• Open drain applications
• ESD protection for I/O signals and for 1.8 V/1.2 V power supply
• eMMC (1.8 V/1.2 V) PHY has four functional receivers per I/O pad:
o 1.8-V Schmitt trigger
o 1.2-V Schmitt trigger
o 1.8-V comparator receiver
o 1.2-V comparator receiver
• Power supply requirements
o 1.8 V I/O signaling: 1.8 V and a low-voltage digital power supply
o 1.2 V I/O signaling: 1.2 V and a low-voltage digital power supply

5.5. Low Bandwidth Interfaces

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5.5.1 Inter-Integrated Circuit (I2C)

Hailo-8L integrates up to four I2C interfaces that may double as SCCB
(Serial Camera Control Bus) interface to allow the device to be the Master
that controls attached sensors.
Key features include:
• Each interface can be Master or Slave
• High and low-speed support
• Bandwidth
o Fast mode, up to 400Kbps
o High-speed mode, up to 3.4Mb/s

5.5.2 Quad Serial Peripheral Interface (QSPI)

Hailo-8L integrates a single QSPI to work with external Flash devices.
Key support includes:
• Up to two external Chip Selects (CS)
• Execute in Place (XIP) for external Flash device
• Up to 1Gb of external memory space
• SPI (x1), DSPI (x2) and QSPI (x4) modes
• DDR and SDR modes
• Boot from external Flash
• External device frequency of up to 50MHz

5.5.3 Universal Asynchronous Receiver

Transmitter (UART)
Hailo-8L integrates up to four simple UART interfaces (no flow control
signal support).
Key features include:
• 8-bit communication with parity and fixed at one stop bit
• Baud rate up to 2Mbaud

5.5.4 Inter-IC Sound (I2S) Input

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Hailo-8L integrates a single I2S input interface to process digital audio

inputs. The I2S bus is a simple three-wire serial bus protocol. Since it only
handles the transfer of audio data, control and sub-coding signals must
be transferred separately using a different bus protocol, such as I2C.
Key features include:
• Audio resolution of 12,16,20,24 and 32 bits
• External SCLK gating and enable signals

5.6. MCU
Hailo-8L integrates two Cortex M4 cores with a memory subsystem.

5.6.1 Cortex M4 Cores

Each of the two Cortex M4 MCU cores is equipped with a Memory
Protection Unit (MPU) and a Floating Point Accelerator Unit (FPU) engine.
The cores communicate with each other through mailbox and semaphore
modules.
Key features include:
• MPU
• FPU
• Embedded Trace Microcell (ETM)
• Support for up to 200MHz frequency
• ARM core based on ARMv7 architecture
• Boot from external Flash or PCIe by external boot strap pins

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5.6.2 MCU Memory

The MCU memory is accessible by both cores.
Key features include:
• Six data/code memory ports
• Total of 640KB SRAM memory for code and data with ECC
• 256KB ROM
• Up to 1Gb memory space for external Flash devices

5.6.3 Flash System

Hailo-8L can access external Flash devices either directly through the QSPI
controller or through the Flash caching system. The Flash caching system
can cache read only instruction memory up to 512B.
Key features include:
• Two-way 512B cache
• Up to 4MB of configurable memory cache
• Configurable fetching
• Configurable ECC on the cached data

5.7. Vision Subsystem

5.7.1 Image Signal Processing (ISP)
Hailo-8L integrates an ISP unit. It can be used to directly connect a CMOS
sensor to the SoC.
Key features include:
• Complete and fully configurable ISP pipeline
• Input formats:
o RAW8, RAW10, RAW12, RAW14
• Output formats:
o RGB888, YUV422
• 4k resolution: 40 fps videos

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• 1080p resolution: 120 fps video

• Up to 4096h x 4096v resolution
• Optimized for low light environment applications
• Video statistics support Auto Focus, Auto White Balance, Auto
Exposure
• On-the-fly defective pixel correction
• 10-bit Bayer channel gain supports up to x7.99
• Linear algebra for input pixel level adjustment
• Gb/Gr correction with maximum correction tolerance Gb/Gr rate of
12.5%
• 2D lens-shading correction (8x6)
o Normal R/Gb/Gr/B channel shading correction
o Color stain correction
• High resolution RGB interpolation: ES/Hue-Med/Average/Non-
Direction based hybrid type algorithm
• Color correction matrix (3x3)
• Bayer gamma correction (19 points)
• High-performance noise reduction for low light environment:
Bayer/RGB/YC domain
• High-resolution sharpness control: Multi-sharp filter and individual
sharp gain control
• Color enhancement: hue, saturation, Delta-L control (RGBCMY)
• Auto Exposure: supports 16x16 luminance weight window and pixel
weighting
• Auto white balance: RGB-based feed-forward method Tone mapping:
multi-band scheme using liner transformation as multi-slope
• Auto Focus (AF): 2-type 6-region AF value return

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5.7.2 H.264 Encoder

Hailo-8L integrates an advanced ITU-T H.264 high-profile compliant
encoder, constrained to All-Intra encoding schemes.
This encoder can also serve other purposes. It can, for instance, compress
raw data from a sensor, or processed data (insights).
Key features include:
• Max resolution: 1080x1920P.
• Full compliance to the ITU-T H.264 and ISO/IEC 14496-10 specification
• High 10 intra, High 4:2:2 intra profiles encoding
• All-Intra Constraint Baseline or Main profiles encoding
• 8 and 10 bit per component color depth encoding
• 4:2:2 YCbCr digital video input, interleaved scan
• Level up to 5.2
• ITU-T H.264 Annex B compliant NAL byte stream output
• MCU-less, complete and autonomous operation
• True H.264 compression efficiency and perceptually optimized image
quality
• Psychovisual optimizations for better viewer experience
• High throughput implementation
• Sustained 2.4 (in 4:2:0) or 2.7 (in 4:2:2) clock cycles per pixel, worst
case processing rate
• Advanced Intra prediction
o All four Intra 16x16 prediction modes
o All four Intra Chroma prediction modes
o All nine Intra 4x4 prediction modes
• CABAC or CAVLC entropy coding

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5.8. System Peripherals

5.8.1 Temperature Sensor
The Hailo-8L temperature sensor is a high-precision low-power junction
temperature sensor embedded in the chip. Typical temperature sensor
applications may include clock speed optimization, power management
and thermal management.
Key features include:
• +/- 3.0°C accuracy
• 12-bit resolution (10-bit and 8-bit alternatives at lower accuracy),
parallel or serial
• Signature response on demand
• Analog fault coverage

5.8.2 Voltage Monitor

Hailo-8L embeds two on-chip voltage monitors that are low-power self-
contained blocks designed to monitor differential voltage levels within the
core logic voltage domains.
Key features include:
• 16 monitoring points
• +/-1% accuracy
• Up to 14-bit resolution
• Digital interface
• Signature response on demand
• Analog fault coverage

5.8.3 Direct Memory Access (DMA)

The Hailo-8L integrates two DMA modules to easily move and copy data.
Key features include:
• Four configurable channels per DMA
• Support for advanced HW LLP and scatter-gather features

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• Transfer capabilities: peripheral to memory, memory to peripheral,

memory to memory and peripheral to peripheral
• Supports hardware handshake interfaces for I2C module

5.8.4 General-Purpose Input Output (GPIO)

Hailo-8L integrates up to 32 GPIOs. Each of the GPIO pins can be
configured by software as output (push-pull or open-drain, with or
without pull-up or pull-down), as input (floating, with or without pull-up or
pull-down) or as a peripheral alternate function. Most of the GPIO pins are
shared with digital alternate functions. All GPIOs are high-current-capable
and have speed selection to better manage internal noise, power
consumption and electromagnetic emission.
The I/O alternate function configuration can be locked if needed by
following a specific sequence in order to avoid spurious writing to the I/O
registers.

5.8.5 Timer
Hailo-8L integrates four timers that can be programmed through the
GPIO interfaces.
Key features include:
• 32-bit counter
• Clock from external clock input or internal clock
• Interrupt output to MCU system
All timer counters can be frozen in debug mode.

5.8.6 Watchdog
Hailo-8L integrates two watchdogs to monitor the MCUs in the system.
Key features include:
• 32-bit counter
• Configurable Interrupt threshold
• Configurable system reset threshold

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5.8.7 Mailbox
Hailo-8L integrates eight mailboxes to transfer information between MCU
cores.
Each mailbox has one data register to pass pointers to data between
MCUs. After one MCU successfully writes data to the mailbox, the other
MCU receives an interrupt.

5.8.8 Semaphore
Hailo-8L integrates eight semaphore units to control access to a common
resource.

5.8.9 CRC Hardware Offload Engine

Hailo-8L includes an internal CRC generator and calculator to accelerate
CRC calculation on data and control.
Key features include:
• Generate and check CRC
• CRC32/CRC16 polynomials
• CRC calculation on 32/16-bit data width

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5.9. Security System

5.9.1 Features
Hailo-8L implements a wide range of security features for typical target
applications.
The security subsystem includes:
• Secure boot
• Complete Life Cycle Management (LCM)
• User-provided non-volatile hash (enabling RoT behavior)
• User access to hardware-accelerated cryptographic algorithms
• Secure debug access according to the product life cycle
• Inner configurable firewall to block unexpected access to secure
system regions

5.9.2 Lifecycle Management

Hailo-8L has lifecycle support for Hailo’s production and integrator
development processes, as well as for product deployment and Return
Merchandise Authorization (RMA).
The debug interface lock depends on the lifecycle state.

5.9.3 True Random Number Generator (TRNG)

Hailo-8L contains a TRNG that delivers 32-bit random numbers produced
by an integrated analog circuit.
The TRNG is fully compliant with FIPS 140-2.

5.9.4 Cryptographic Accelerator

Hailo-8L contains a hardware authentication engine and an
encryption/decryption engine that support the following algorithms:
• AES (128,192,256)
• SHA1/2
• RSA (2048,3072,4096)

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 Hailo-8L™ Datasheet Rev.1.5

The cryptographic accelerator can be used for secure boot, data-at-rest

and data-in-transit.

5.9.5 Trusted Execution Environment (TEE)

The Hailo-8L TEE monitors and controls incoming and outgoing traffic
inside the chip based on predetermined security rules set during software
boot.
The Hailo-8Lsecurity system has a configurable hardware firewall. It
protects access to peripherals inside the chip, internal SRAMs and
external memory regions.

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