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152 views55 pages

Noise 1

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agupta54145
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© © All Rights Reserved
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BEC 058 CMOS ANALOG VLSI DESIGN

Dr. Dharmender Nishad

Assistant Professor

Dept. of Electronics and Communication Engineering

G.L Bajaj Institute of Technology and Management,


Gr. Noida
05-Dec-24 CMOS ANALOG VLSI DESIGN 1
Syllabus
UNIT I: Introduction to MOS: MOS device models and short channel effects MOSFET level 1
and level 2 models, threshold voltage model, MOSFET basics, Single stage amplifiers, Basic
concept, Common source stage: with resistive load, with diode connected load, with current-
source load, with triode load, with source degeneration Source follower (common-drain) and
common gate with various loads.

UNIT II: Scheme and Implementation: basic current mirrors, cascode current mirrors and
active current mirrors with large and small signal analysis, CMOS amplifier Frequency response:
Miller effect, common source (CS), common gate (CG), common drain (CD) stages.

UNIT III: Noise: types of noise, significance of flicker and thermal. Analysis and representation
of noise in single stage amplifiers: CG, CS, CD (source follower) and cascode stage and noise in
differential pairs. Feedback: Feedback topologies (voltage-voltage, current-voltage, voltage-
current, current-voltage) and the noise and the loading effect analysis

UNIT IV: Design of the CMOS Operational Amplifiers: One-stage op amps and two stage op
amps, Gain boosting techniques, folded cascode, telescopic amplifier and common mode
feedback (CMFB) amplifier, Design of high speed and high gain amplifiers.

UNIT V: Stability and Frequency Compensation: Specification analysis, multi-pole system,


three stage op amp, phase margin Frequency compensation, pole-zero doublet analysis, Analog
layout techniques, Design rule check (DRC), layout versus schematic (LVS) and antenna effects.

05-Dec-24 CMOS Analog VLSI Design 2


Unit-2 OUTLINES
 Noise

 Nature of Noise

 Characterization of noise

 Propagation and shaping of noise

 Correlated and uncorrelated noise sources

05-Dec-24 CMOS Analog VLSI Design 3


Basics
Deterministic signal and Random Signal

 The value of t1 can be predicted from the previous value.

 The value of t2 cannot be predicted from the previous value.

05-Dec-24 CMOS Analog VLSI Design 4


Average Power
 Average power delivered by a periodic voltage v(t) to a load
resistance RL is given by

 For Random Signal

 Normalized Power

05-Dec-24 CMOS Analog VLSI Design 5


Power Spectral desnity
 Power spectral density (PSD): shows how much power the signal (noise in our
case) carries at each frequency. It is generally indicated by S(f), and measured
in V2/Hz

 If a signal (noise) with PSD SIN(f) is applied to a linear time-invariant


system with transfer function H(f), then the output spectrum SOUT(f) is
given by:

05-Dec-24 CMOS Analog VLSI Design 6


Noise Spectrum

05-Dec-24 CMOS Analog VLSI Design 7


Noise spectrum

05-Dec-24 CMOS Analog VLSI Design 8


Noise Spectrum

05-Dec-24 CMOS Analog VLSI Design 9


Propagation and Shaping of Noise
• If a signal with spectrum Sx(f) is applied to a linear time-invariant system
with transfer function H(s), then the output spectrum is given by

05-Dec-24 CMOS Analog VLSI Design 10


Example

 As illustrated in Figure. since regular telephones have a bandwidth of approximately


4 kHz, they suppress the high-frequency components of the caller’s voice.
 Note that, owing to its limited bandwidth, xout(t) exhibits slower changes than does
xin(t).
 This bandwidth limitation sometimes makes it difficult to recognize the caller’s
voice.

05-Dec-24 CMOS Analog VLSI Design 11


Correlated and Uncorrelated Sources

05-Dec-24 CMOS Analog VLSI Design 12


Correlated and Uncorrelated Sources

05-Dec-24 CMOS Analog VLSI Design 13


Thermal Noise
 Resistor Thermal Noise: Thermal noise is caused by the random thermally
excited vibration of the charge carriers in a conductor

 J. B. Johnson first observed thermal noise in 1927, and a theoretical analysis


was provided by H. Nyquist in 1928.

 Thermal noise is, therefore, also called Johnson or Nyquist noise.

 The spectrum of thermal noise is proportional to the absolute temperature

 The thermal noise of a resistor R can be modeled by a series voltage source,


with the one-sided spectral density

05-Dec-24 CMOS Analog VLSI Design 14


Thermal Noise

vn2 Power spectral density [ V2 / Hz ]


R
v n2  4kTR  f [ V2 ]
v2 in2
i 
2
n
n
2
R
4kT
i 
2
n  f [ A2 ] [Alternative model]
R R

05-Dec-24 CMOS Analog VLSI Design 15


Thermal Noise
 Ideal capacitors or inductors do not have noise sources. In practice, real components have
parasitic resistance that does display thermal noise!

 The equation Sv(f ) = 4kT R suggests that thermal noise is white.

 In reality, Sv(f ) is flat for up to roughly 100 THz, dropping at higher frequencies

 Some books write V2n = 4kT R Δf to emphasize that 4kT R is the noise power per unit
bandwidth.

• To simplify the notation, we assume that Δ f = 1 Hz, unless otherwise stated.

• In other words, we use Sv( f ) and V2n interchangeably.

05-Dec-24 CMOS Analog VLSI Design 16


Thermal Noise
 Consider the RC circuit shown in Fig. 7.15. Calculate the noise spectrum and the total noise
power in Vout

05-Dec-24 CMOS Analog VLSI Design 17


Thermal Noise
 The noise spectrum of R is given by Sv( f ) = 4kT R.

 Next, modeling the noise of R by a series voltage source VR, we compute the transfer
function from VR to Vout:

05-Dec-24 CMOS Analog VLSI Design 18


Thermal Noise

05-Dec-24 CMOS Analog VLSI Design 19


Thermal Noise
 Calculate the equivalent noise voltage of two parallel resistors R1 and R2

05-Dec-24 CMOS Analog VLSI Design 20


Noise in MOS transistors
Channel thermal noise: due to the random thermal motion of the carriers in the channel.

1/f noise: due to the random trapping and de-trapping of mobile carriers in the traps
located at the Si-SiO2 interface and within the gate oxide.

Bulk resistance thermal noise: due to the distributed substrate resistance.

Gate resistance thermal noise: due to the resistance of the polysilicon gate and of the
interconnections.

05-Dec-24 CMOS Analog VLSI Design 21


Channel thermal noise:
 MOS transistors also exhibit thermal noise. The most significant source is the noise generated
in the channel.

 For long-channel MOS devices operating in saturation, the channel noise can be modeled by a
current source connected between the drain and source terminals (Fig. 7.19) with a spectral
density.

 is excess noise coefficient = 2/3 for long channel


= 1 short channel device.

05-Dec-24 CMOS Analog VLSI Design 22


Channel thermal noise:
 Should we maximize or minimize gm ?

05-Dec-24 CMOS Analog VLSI Design 23


MOS channel Thermal noise
 Find the maximum noise voltage that a single MOSFET can generate.

 As shown in Fig. 7.20, the maximum output noise occurs if the transistor sees only its
own output impedance as the load, i.e., if the external load is an ideal current source

 The output noise voltage spectrum is then given by.

05-Dec-24 CMOS Analog VLSI Design 24


MOS Gate Resistance thermal noise
 The ohmic sections of a MOSFET also contribute to thermal noise. As conceptually
illustrated in the top view of Fig. 7.21(a), the gate, source, and drain materials exhibit finite
resistivity, thereby introducing noise.

 The source and drain resistance is typically negligible for a relatively wide transistor,
whereas the gate distributed resistance may become noticeable.

05-Dec-24 CMOS Analog VLSI Design 25


Basic Current Mirror
• In the noise model of Fig. 7.21(b), a lumped resistor R1 represents the
distributed gate resistance.

• Viewing the overall transistor as the distributed structure shown in


Fig. 7.21(c), we observe that the unit transistors near the left end see
the noise of only a fraction of RG whereas those near the right end see
the noise of most of RG.

• We therefore expect the lumped resistor in the noise model to be less


than RG. In fact, it can be proved that R1 = RG / 3

• Hence the noise generated by the gate resistance is given by V2nRG =


4kT RG /3

05-Dec-24 CMOS Analog VLSI Design 26


Flicker Noise
 Find the maximum thermal noise voltage that the gate resistance of a single
MOSFET can generate. Neglect the device capacitances.

05-Dec-24 CMOS Analog VLSI Design 27


Flicker Noise
 Flicker Noise or i/f Noise is generated due to the random trapping and de-trapping of
mobile carriers in the traps located at the Si-SiO2 interface and within the gate oxide.

 Since the silicon crystal reaches an end at this interface, many “dangling” bonds appear,
giving rise to extra energy states.

 As charge carriers move at the interface, some are randomly trapped and later
released by such energy states, introducing “flicker” noise in the drain current.

05-Dec-24 CMOS Analog VLSI Design 28


Flicker Noise
 Unlike thermal noise, the average power of flicker noise cannot be predicted
easily.

 Depending on the “cleanness” of the oxide-silicon interface, flicker noise may


assume considerably different values and as such varies from one CMOS
technology to another.

 The flicker noise is more easily modeled as a voltage source in series with the
gate and, in the saturation region, roughly given by

05-Dec-24 CMOS Analog VLSI Design 29


Flicker Noise
 where K is a process-dependent constant on the order of 10-25 V2F

• The inverse dependence on WL suggests that to reduce 1/f noise, the device area
must be increased.

05-Dec-24 CMOS Analog VLSI Design 30


Flicker Noise
 For an NMOS current source, calculate the total thermal and 1/ f noise in the drain
current for a band from 1 kHz to 1 MHz.

05-Dec-24 CMOS Analog VLSI Design 31


Flicker noise Vs Thermal nise

• In order to quantify the significance of 1/f noise with respect to thermal noise for a
given device, we plot both spectral densities on the same axes (Fig. 7.27). Called the
1/ f noise “corner frequency

05-Dec-24 CMOS Analog VLSI Design 32


Basic Current Mirror
 In the above example, the 1/ f noise corner, fC, of the output current is determined as

05-Dec-24 CMOS Analog VLSI Design 33


Flicker Noise

05-Dec-24 CMOS Analog VLSI Design 34


Representation of Noise in Circuits

 Noise Analysis Procedure


 Identify the source of Noise

 Find the transfer function from each source to the output.

 Determine the output spectrum due to each source

 Add all the contributions to the output

05-Dec-24 CMOS Analog VLSI Design 35


Pictorial Noise Analysis Procedure….

05-Dec-24 CMOS Analog VLSI Design 36


Example

05-Dec-24 CMOS Analog VLSI Design 37


Noise Analysis Procedure….
 Consider a Common source amplifier with an ideal noiseless current source.

 In the above circuit only MOS thermal noise is considered but not flicker noise.

How to optimize the circuit for noise? (Maximize or minimize gm?)

Note: If some signal is passing trough the transistor then we just look at not only noise at the
output but also signal at the output and see what happens to signal to noise ratio (S/N)

 We investigated the device with transconductance gm and 2gm

 The output noise voltage gets doubled when we double the gm.

 But what happens to the signal power ?

05-Dec-24 CMOS Analog VLSI Design 38


Noise Analysis Procedure….
 The input signal vin is multiplied with gm to get the current at the output and it is multiplied
with gmro to get voltage at the output

05-Dec-24 CMOS Analog VLSI Design 39


Representation of Noise in Circuits
 What is the total output noise voltage of the common-source stage shown in Fig. 7.29(a)?
Assume that λ = 0.

05-Dec-24 CMOS Analog VLSI Design 40


Representation of Noise in Circuits
 We must identify the sources of noise

 Find their transfer functions to the output, multiply their spectra by


the squared magnitude of the transfer functions and add the results.

 We model the thermal and flicker noise of M1 by two current sources

 We also represent the thermal noise of RD by a current source

05-Dec-24 CMOS Analog VLSI Design 41


Representation of Noise in Circuits
 Since these currents flow through RD, the output noise voltage per unit
bandwidth is equal to

05-Dec-24 CMOS Analog VLSI Design 42


Recap : Device Noise sources

05-Dec-24 CMOS Analog VLSI Design 43


Device Noise sources
Thermal noise of a MOSFET.

 Flicker noise of a MOSFET.

05-Dec-24 CMOS Analog VLSI Design 44


Input-Referred Noise
 The output-referred noise does not allow a fair comparison of the performance
of different circuits because it depends on the gain.

• For example, as depicted in Fig. 7.30, if a common-source stage is followed by a


noiseless amplifier having a voltage gain A1, then the output noise is equal to
the expression in (7.44) multiplied by A21

05-Dec-24 CMOS Analog VLSI Design 45


Input-Referred Noise
 Considering only the output noise,

 we may conclude that as A1 increases, the circuit becomes noisier,

 An incorrect result because a larger A1 also provides a proportionally higher signal


level at the output.

 That is, the output signal-to-noise ratio does not depend on A1.

• To overcome the above quandary, we usually specify the “input-referred noise” of


circuits.

• Illustrated conceptually in Fig. 7.31, the idea is to represent the effect of all noise
sources in the circuit by a single source,, at the input such that the output noise
in Fig. 7.31(b) equals that in Fig. 7.31(a).

05-Dec-24 CMOS Analog VLSI Design 46


Input-Referred Noise

• If the voltage gain is Av, then we must have that is, the input-referred
noise voltage in this simple case is given by the output noise voltage divided by the
gain

05-Dec-24 CMOS Analog VLSI Design 47


Input-Referred Noise

05-Dec-24 CMOS Analog VLSI Design 48


Example 2

05-Dec-24 CMOS Analog VLSI Design 49


Input-Referred Noise
 If the circuit has a finite input impedance, modeling the input-referred noise by
merely a voltage source implies that the output noise vanishes as the source
impedance becomes large, an incorrect conclusion.

• To resolve this issue, we model the input-referred noise by both a series voltage
source and a parallel current source (Fig. 7.33)

• so that if the output impedance of the preceding stage assumes large values—
thereby reducing the effect of the noise current source still flows
• through a finite impedance, producing noise at the input. It

05-Dec-24 CMOS Analog VLSI Design 50


Input-Referred Noise

05-Dec-24 CMOS Analog VLSI Design 51


Input-Referred Noise
• Calculate the input-referred noise voltage and current of Fig. 7.32, including only
the thermal noise of M1 and RD.

05-Dec-24 CMOS Analog VLSI Design 52


Input-Referred Noise

05-Dec-24 CMOS Analog VLSI Design 53


Input-Referred Noise

05-Dec-24 CMOS Analog VLSI Design 54


Research Target (2024-25)

Fig.1 show the effect of scaling on MOS Device

CMOS Analog VLSI Design


05-Dec-24 55

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