ELECTRONICS AND COMMUNICATION ENG. DEPT.
SPHINX UNIVERSITY
DIGITAL AND LOGIC CIRCUITS LEVEL 2 (2024-2025)
SHEET #8
A) The following S and R inputs are applied to an SR latch. Determine the waveform
that will be observed on the Q output. Assume that Q is initially LOW.
1)
Answer:
2)
Answer:
B) Determine the Q output waveform if the inputs in blue are applied to a gated D
latch, which is initially RESET.
1)
Answer:
C) Determine the Q and Q’ output waveforms of the flip-flop below for the D and CLK
inputs in blue. Assume that the positive edge-triggered flip-flop is initially RESET.
1)
Answer:
2)
Answer:
3)
Answer:
D) The following waveforms are applied to the J, K, and clock inputs as indicated.
Determine the Q output, assuming that the JK flip-flop is a positive edge-triggered
device which is initially RESET.
1)
Answer:
E) Develop the fout waveform for the circuit in following figure when an 8 kHz square
wave input is applied to the clock input of flip-flop A.
1)
Answer:
The three flip-flops are connected to divide the input frequency by eight (23 =
8) and the QC (fout) waveform is shown below. Since these are positive edge-triggered
flip-flops, the outputs change on the positive-going clock edge. There is one output
pulse for every eight input pulses, so the output frequency is 1 kHz. Waveforms of
QA and QB are also shown.
F) Determine the output waveforms in relation to the clock for QA, QB, and QC in the
following circuit and show the binary sequence represented by these waveforms.
1)
Answer:
The output is shown in the timing diagram below. Notice that the outputs
change on the negative-going edge of the clock pulses. The outputs go through
the binary sequence 000, 001, 010, 011, 100, 101, 110, and 111 as indicated.
