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hw4 Sol

The document provides solutions for homework problems related to digital circuits, specifically focusing on gated S-R latches, gated D latches, J-K flip-flops, and D flip-flops. It includes diagrams and explanations of how each component operates based on input waveforms and clock signals. Key concepts include the conditions for output changes and the differences between edge-triggered flip-flops.

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39 views3 pages

hw4 Sol

The document provides solutions for homework problems related to digital circuits, specifically focusing on gated S-R latches, gated D latches, J-K flip-flops, and D flip-flops. It includes diagrams and explanations of how each component operates based on input waveforms and clock signals. Key concepts include the conditions for output changes and the differences between edge-triggered flip-flops.

Uploaded by

gxrc46r82m
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Circuits: Homeworks #4 Solutions

1. Gated S-R Latch.


For a gated S-R latch, draw the Q and Q̄ outputs for the inputs in Figure 1. Show
them in proper relation to the enable input. Assume that Q starts LOW.

Figure 1: Input Waveform.

Solution: Gated S-R Latch


Recall that S-R Latch only works when EN is HIGH. If EN is HIGH, Q is HIGH when
S is HIGH, Q is LOW when R is HIGH, and Q is NC (no change) when both S and
R are LOW. Q output is shown in Figure 2

Figure 2: Output Waveform.

2. Gated D Latch.
Determine the output of a gated D latch for the inputs in Figure 3. Assume that Q
starts LOW.

Figure 3: Input Waveform.

Homework 4 Page 1 of 3
Solution: Gated S-R Latch
Recall that D Latch only forwards the value when EN is HIGH. If EN is HIGH, Q is
HIGH when D is HIGH, and Q is LOW when D is LOW. Q output is shown in Figure
4

Figure 4: Output Waveform.

3. J-K Flip-Flops.
Two edge-triggered J-K flip-flps are shown in Figure 5. If the inputs are as shown,
draw the Q output of each flip-flop relative to the clock, and explain the difference
between the two. Assume that flip-flops are initially RESET.

Figure 5: Input Waveform.

Solution: J-K Flip-Flops


Flip-flop in Figure 5 (a) is negative edge triggered flip-flop. So it is triggered at HIGH
to LOW transition. Flip-flop in Figure 5 (b) is positive edge triggered flip-flop. So it
is triggered at LOW to HIGH transition. Q output is showed in Figure 6

Figure 6: Output Waveform.

4. D Flip-Flops.
A D flip-flop is connected as shown in Figure 7. Draw the Q output in relation to

Homework 4 Page 2 of 3
the clock when the flip-flop is initially RESET. What specific function does this device
perform?

Figure 7: Input Waveform.

Solution: D Flip-Flops
Recall that D flip-flop forwards the value when CLK is transitting from LOW to HIGH.
It divides the frequency, in other words, it generates another CLK with half frequency.

Figure 8: Output Waveform.

Homework 4 Page 3 of 3

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