APW8879A

High Input Voltage 3.36V / 8A Synchronous Buck Converter with 100mA LDO

Features General Description

 Wide Operating Range from +5.5V to +24V Input The APW8879A is a 8A, synchronous buck converter with
Voltages integrated 25mΩ High-Side MOSFET and 12mΩ Low-
Side MOSFET. The APW8879A designed with a constant
 Power-On-Reset Monitoring on VIN at 4.5V ~ 4.9V
on-time control architecture can step down high voltage to
range accommodate low-voltage chipset for IMPV8 applications.
 Built-in 100uA low quiescent current The APW8879A is equipped with an automatic PFM/PWM
 Support IOUT = 8A Application mode operation. At light load, the converter operates in
the PFM mode to reduce the switching losses and provide
 Built in PWM & PFM Control Schemes with COT
high efficiency. At heavy load, the converter works in PWM
achitecture mode and operates nearly at constant frequency for low-
 Built in Integrated Bootstrap Forward P-CH noise requirements.
MOSFET The APW8879A is also equipped with Power-on-reset,
soft-start, soft-stop, and whole protections (under-voltage,
 Fixed Switching Frequency from700KHz
over-voltage, over-temperature, over-current and cur-
 Fixed 3.36V VOUT REF voltage with +0.6% rent-limit) into a single package.
accuracy The charge pump circuit with 250kHz clock driver uses
 Support Ultrasonic Mode selection on EN Pin VOUT as its power supply to generate approximately
10~12V DC voltage.
 Support built-in fixed Soft Start time 2.4ms
This device, available in TQFN 2x3-12 package, provides
 Integrated 25mΩ N-Channel MOSFET For High a very compact system solution to minimize external
Side MOS components and PCB area.
 Integrated 12mΩ N-Channel MOSFET For Low Side
MOS
 Built in Open-Drain Type POK function and EN
control Pin Configuration
 Built in 3.36V / 100mA LDO and Switch-over
MOSFET with PWM output APW8879A QBI
 UVP setting at 70%of VREF & OVP setting at 125%
AGND

VCC
LP#

EN

of VREF & Thermal Shutdown

 Built in Over Current Protection and Current Limit 12 11 10 9

Protection using high-side MOSFET RDS(on) and

low-side MOSFET RDS(on) sensing
VIN 1 8 BST
 Flip-Chip TQFN 2x3-12P with Lead Free & RoHS
compliant 7 LX

PGND 2

Applications 3 4 5 6
POK

VCLK

VOUT

LDO3

●● Notebook
●● Graphic card
FC - TQFN 2x3 -12P
●● Motherboard (TOP VIEW)

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise cus-
tomers to obtain the latest version of relevant information to verify before placing orders.

CopyrightANPEC Electronic Corp. 1 www.anpec.com.tw

Rev. A.5 – Apr, 2019
APW8879A
Simplified Application Circuit

VCC EN

CVCC

EN VIN
VCC VIN
RPOK CIN
BST
POK CB
CLK APW8879A
LX
LOUT
LP#
VOUT VOUT
COUT
AGND PGND LDO LDO
CLDO

Ordering and Marking Information

APW8879A Package Code

QB: TQFN2x3-12
Assembly Material Operating Ambient Temperature Range
Handling Code I : -40 to 85 C°
Temperature Range Handling Code
TR : Tape & Reel
Package Code Lead Free Code
L : Lead Free Device G : Halogen and Lead Free Device

8879A XXXXX - Date Code

APW8879A QB : XXXXX

Note 1: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant
with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak
reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in
homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).

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Rev. A.5 – Apr., 2019
APW8879A
Absolute Maximum Ratings (Note 2)

Symbol Parameter Rating Unit

VIN VIN Supply Voltage (VIN to AGND) -0.3 ~ 28 V
VBOOT BOOT Supply Voltage (BOOT to LX) VLX -0.3 ~ VLX +7 V
VGND AGND to PGND -0.3 ~ +0.3 V
All Other Pins (POK, EN, LP#, VOUT, CLK, LDO, VCC) -0.3 ~ 7 V
VLX LX Voltage (LX to GND) -0.3 ~ VIN+0.3 V
PD Power Dissipation Internally Limited W
o
TJ Junction Temperature 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature(10 Seconds) 260 C
Human Body Mode ±2 kV
VESD Minimum ESD Rating (Note 3)
MM Mode 0.2 kV
Note 2: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 3: The device is ESD sensitive. Handling precautions are recommended.

Thermal Characteristics
Symbol Parameter Typical Value Unit
o
qJA Junction-to-Ambient Resistance in free air (Note 4) – TQFN2x3-12 45 C/W
Note 4: θJA is measured with the component mounted on a four-layer Anpec evaluation board in free air.

Recommended Operating Conditions (Note 5)

Symbol Parameter Range Unit
VIN Converter Input Voltage 5.5 ~ 24 V
IOUT Converter Output Current 0~8 A
LOUT Converter Output Inductor 1.0 ~ 2.2 μH
CIN Converter Input Capacitor (MLCC) 20 ~ 30 μF
COUT Converter Output Capacitor (MLCC) 44 ~ 66 μF
o
TA Ambient Temperature -40 ~ 85 C
o
TJ Junction Temperature -40 ~ 125 C
Note 5: Refer to the typical application circuit.

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Rev. A.5 – Apr., 2019
APW8879A
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=19V, VEN=5V and TA= -40 to 85 oC. Typical values are at TA = 25oC.

APW8879A
Symbol Parameter Test condition Unit
Min. Typ. Max.
INPUT VOLTAGE
VIN POR Voltage Threshold VIN Rising 4.5 4.7 4.9 V
VIN
VIN POR Hysteresis - 0.2 - V
REFERENCE VOLTAGE & SOFT START
LP#=H - 3.36 - V
VOUT Reference Output Voltage
LP#=L - 3.23 - V
TA = 25 degree -0.6 - +0.6 %
Reference Voltage Accuracy
TA = -40 ~ 85 degree -1 - +1 %
TSS Soft Start Time From EN high to POK high - 2.4 - ms
VCC POR THRESHOLD
VCC POR Voltage Threshold VCC Rising - 4.3 - V
VCC
VCC POR Hysteresis - 0.2 - V
SUPPLY CURRENT
IVIN VIN Supply Current At no switching - 80 100 uA
IVIN_SD VIN Shutdown Current VIN = 19V , EN= L - 60 80 uA
SWITCHING FREQUENCY
FOSC Switching Frequency - 0.7 - MHz

TON(min) Minimum On Time - 50 - ns

TOFF(min) Minimum Off Time - 200 - ns

CONTROL (EN , LP#)
VH High Level Input Threshold Voltage For EN 1.2 - - V
VL Low Level Input Threshold Voltage For EN - - 0.4 V
EN High Level at Ultrasonic Mode For EN - - 1.7 V

EN Low Level at Normal For EN 2.3 - - V

TUSM Ultrasonic Mode operation period - 32 - us

VH High Level Input Threshold Voltage For LP# 1.2 - - V
VL Low Level Input Threshold Voltage For LP# - - 0.4 V
ILKG Input Leakage Current at EN, LP# VEN = VLP# = 5V - 1.0 - uA
INTERNAL POWER SWITCH
RDS(ON)H NMOS_HI ON Resistance VCC=5V - 25 - mΩ
RDS(ON)L NMOS_LO ON Resistance VCC=5V - 12 - mΩ
ILX_LKG H-side MOS Leakage Current VIN = 19V, LX=0V, EN=0V - 0.1 - uA
LDO REGULATOR
VLDO LDO Regulator 3.3 3.36 3.42 V

LDO Load Regulation VIN = 19V , IOUT = 10m~100mA - 2 - %

ILDO_limit LDO Current Limit 150 200 300 mA

LDO Switch bypass R ILDO =50mA - 0.8 - Ω

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Rev. A.5 – Apr., 2019
APW8879A
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VIN=19V, VEN=5V and TA= -40 to 85 oC. Typical values are at TA = 25oC.

APW8879A
Symbol Parameter Test condition Unit
Min. Typ. Max.
POWER-OK INDICATOR
VOUT / VREF, POK go high from Lower 85 90 95 %
POK Threshold
VPOK Hysteresis - 5 - %
(OTP occur, POK always go low)
VOUT / VREF, POK go low from Normal 120 125 130 %
POK Leakage Current - 0.1 1 uA

POK High to Low Debounce Time - 15 - us

EN Low to POK Low Delay - 1 - us

CURRENT LIMIT & OVER CURRENT PROTECTION
I_LIM_P High side Current Limit - 16 - A
I_LIM_N Low side Current Limit - 11 - A
High Side Over Current Protection - 20 - A
PROTECTION
VOVP Over Voltage Protection VOUT/VOUT(MON) 120 125 130 %
Over Voltage Protection delay time - 5 - us
VUVP Under Voltage Protection VOUT/VOUT(MON) 65 70 75 %
Under Voltage Protection delay time - 10 - us
o
TOTP OTP Rising Threshold - 150 - C
o
OTP Hysteresis - 30 - C
VCLK Output
VCLKH Output High Level Voltage ICLK = -10mA 3.18 3.23 3.28 V
VCLKL Output Low Level Voltage ICLK = 10mA 0 0.05 0.1 V
FCLKL CLK Switching Frequency - 250 - KHz

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Rev. A.5 – Apr., 2019
APW8879A

Typical Operating Characteristics

Refer to the typical application circuit. The test condition is VIN=19V, LOUT=1.5µH,COUT=22µF*2 TA= 25oC unless otherwise specified.

Output Voltage (Iout=2A) Output Voltage vs. Output Current

vs. Ambient Temperature
3.5 3.4
3.45
3.4 3.35

3.35

Output Voltage (V)

Output Voltage(V)

3.3
3.3
3.25 3.25
3.2
3.2
3.15
3.1
LP# = H 3.15 LP# = H
3.05
LP# = L LP# = L
3 3.1
-40 -20 0 20 40 60 80 100 120 0 1 2 3 4 5 6 7 8
Junction Temperature(°C) Output Current (A)

Input Voltage Input Voltage

vs. Output Voltage (VOUT=3.33V) vs. Output Voltage (VOUT=3.2V)
3.45 3.3
3.43 3.28
3.41 3.26
3.39 3.24
Output Voltage(V)

Output Voltage(V)

3.37 3.22
3.35 3.2
3.33 3.18
3.31 3.16
3.29 3.14
Iout=1A Iout=1A
3.27 Iout=8A 3.12 Iout=8A
3.25 3.1
5 7 9 11 13 15 17 19 21 23 5 7 9 11 13 15 17 19 21 23
Input Voltage (V) Input Voltage (V)

Efficiency vs. Output Current LDO Output Voltage

VIN=19V , VOUT=3.33V & 3.2V vs. LDO Output Current
100 3.35
98 3.34
96 3.33
Output Voltage (V)

94 3.32
Efficiency (%)

92 3.31
90 3.3
88 3.29
86 3.28
84 LP#=H 3.27
LP#=L
82 3.26
80 3.25
0.01 0.1 1 10 0 20 40 60 80 100
Output Current (A) Output Current (mA)

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Rev. A.5 – Apr., 2019
APW8879A
Typical Operating Characteristics (Cont.)
Refer to the typical application circuit. The test condition is VIN=19V, LOUT=1.5µH,COUT=22µF*2 TA= 25oC unless otherwise specified.

Switching Frequency Switching Frequency

vs. Input Voltage vs. Output Current
800 800

700
Switching Frequency (KHz)

Switching Frequency (KHz)

700
600
600
500

500 400

300
400
200
300
100

200 0
5 7 9 11 13 15 17 19 21 23 0 1 2 3 4 5 6 7 8
Input Voltage (V) Output Current (A)

Switching Frequency
vs. Ambient Temperature
800
Switching Frequency (KHz)

600

400

200

0
-40 -20 0 20 40 60 80 100 120
Junction Temperature (°C)

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Rev. A.5 – Apr., 2019
APW8879A
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=19V, LOUT=1.5µH,COUT=22µF*2 TA= 25oC unless otherwise specified.

Power ON Power OFF

VIN
VIN 1
1
VOUT
VOUT
2 2
VLX
VLX
3 3

IL
IL
4 4

CH1: VIN, 10V/Div, DC CH1: VIN, 10V/Div, DC

CH2: VOUT, 2V/Div, DC CH2: VOUT, 2V/Div, DC
CH3: VLX, 10V/Div, DC CH3: VLX, 10V/Div, DC
CH4: IL, 5A/Div, DC CH4: IL, 5A/Div, DC
TIME: 1ms/Div TIME: 2ms/Div

Enable Disable

VEN VEN
1 1

VOUT VOUT
2 2
VPOK VPOK
3 3

IL IL
4 4

CH1: VEN, 5V/Div, DC CH1: VEN, 5V/Div, DC

CH2: VOUT, 2V/Div, DC CH2: VOUT, 2V/Div, DC
CH3: VPOK, 5V/Div, DC CH3: VPOK, 5V/Div, DC
CH4: IL, 5A/Div, DC CH4: IL, 5A/Div, DC
TIME: 500ms/Div TIME: 10ms/Div

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Rev. A.5 – Apr., 2019
APW8879A
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=19V, LOUT=1.5µH,COUT=22µF*2 TA= 25oC unless otherwise specified.

Load Transient Current Limit

VPOK
VPOK
1 1

VOUT VOUT

2
2 IOUT

IL

3
3
CH1: VPOK, 5V/Div, DC
CH1: VPOK, 5V/Div, DC CH2: VOUT, 2V/Div, DC
CH2: VOUT, 200mV/Div, DC, Offset=4.65V CH3: IL, 5A/Div, DC
CH3: IOUT, 2A/Div, DC TIME: 20ms/Div
TIME: 1ms/Div

Over Voltage Protection Under Voltage Protection

VPOK 1 VPOK
1

VOUT

2
VOUT
2

IL IL
3 3

CH1: VPOK, 5V/Div, DC CH1: VPOK, 5V/Div, DC

CH2: VOUT, 2V/Div, DC CH2: VOUT, 2V/Div, DC
CH3: IL, 1A/Div, DC CH3: IL, 5A/Div, DC
TIME: 20ms/Div TIME: 10ms/Div

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Rev. A.5 – Apr., 2019
APW8879A
Pin Descriptions
PIN
FUNCTION
NO. NAME

Battery Voltage Input. The APW8879A operates from a +5.5V to +24V input rail. Must be closely decoupled to
1 VIN
GND with two 10μF or greater ceramic capacitor.
2 PGND Power Ground of The LGATE Low-Side MOSFET Drivers.
Power good indicator. POK is an open-drain output used to indicate the status of the PWM output voltage.
3 POK
Connect a resistor from POK to a pull-high voltage.
4 CLK 250kHz Clock Output for 10-12V Charge Pump. Control by EN also.
Output Voltage Feedback Pin. This pin is connected to the output voltage.The pin also provide the bypass
5 VOUT
input for internal LDO.
3.3V Linear Regulator Output. LDO can provide 100mA current for external load. Bypass to GND with a
6 LDO
minimum of 4.7uF ceramic capacitor for stability.
Power Switching Output. The LX is the junction of the high-side and low-side power MOSFET to supply power
7 LX
to the output LC filter.
High-side Gate Driver Supply Voltage Input. Connect to an external capacitor to create a boosted voltage
8 BST
suitable to drive a logic-level N-channel MOSFET.
5V Linear Regulator Output for internal control circuit. And VCC to GND with a 1.0uF ceramic capacitor for
9 VCC
stability.
10 AGND Signal ground for this IC .
PWM enable pin. Logic high enables the PWM output. Logic low disables the PWM output. EN pin also be
11 EN used to set Ultrasonic mode. When EN is between 1.2V and 1.7V, it will enter the Ultrasonic mode. If EN is
higher than 2.3V, then it enters the normal mode. Do not float this pin.
Low powermode control signal input pin. Pull high in the normally operation (VOUT=3.36V), and pull low to
12 LP#
enter low power mode.

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Rev. A.5 – Apr., 2019
APW8879A
Block Diagram

POK VOUT LP#

AGND
125% VREF VOUT

Output
Discharge
Delay

90 % VREF
Current
Limit
125% VREF
OV Reference

Fault VIN
VCC
Latch
Logic
UV BOOT

70 % VREF
Thermal UG

PWM Signal Controller

Shutdown
Gate
On-Time Driver VLX
Generator
Error
Comparator
LX

VCC
VCC
ZC

V REF

LX LG

POR Gate
EN Soft-Start
Driver
PGND
VOUT

CLK VIN
CLK Generator
Internal LDO Switching LDO LDO
POK Over Control Control
EN

LDO VCC

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Rev. A.5 – Apr., 2019
APW8879A
Typical Application Circuit

VIN L
VOUT
5.5V~24V VIN LX 3.36V/8A
CBOOT 1.5uH
CIN2 CIN1 0.1uF COUT
10uF 10uF MLCC
RBOOT
22uF*2
BST 3.3Ω

VOUT VSYS
LP#
LP# COUT
0.1uF CCLK1
0.1uF
CLK
APW8879A QBI CLK CCLK2
EN
0.1uF
EN
POK CCLK3
POK 0.1uF
CCLK4
RPOK 0.1uF
VCC 100KΩ
VCC VCP
LDO
LDO
3.3V/100mA
CLDO
CVCC
4.7uF
1uF
AGND PGND

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Rev. A.5 – Apr., 2019
APW8879A
Function Descriptions
Constant-On-Time PWM Controller with Input Feed- Power-On-Reset
Forward
A Power-On-Reset (POR) function is designed to prevent
The constant on-time control architecture is a pseudofixed wrong logic controls when the VCC voltage is low. The
frequency with input voltage feed-forward. This architec- POR function continually monitors the bias supply voltage
ture relies on the output filter capacitor’s effective series on the VCC pin if the enable pin is set high. When the ris-
resistance (ESR) to act as a current-sense resistor, so the ing VCC voltage reaches the rising POR voltage threshold
output ripple voltage provides the PWM ramp signal. (4.3V, typical), the POR signal goes high and the chip ini-
In PFM operation, the high-side switch on-time controlled tiates soft-start operations. Should this voltage drop lower
by the on-time generator is determined solely by a one- than 4.1V (typical), the POR disables the chip.
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by a EN Pin Control
switching frequency control circuit in the on-time generator When VEN is above the EN high threshold (1.2V, minimum),
block.
the converter is enabled. When VEN is below the EN low
The switching frequency control circuit senses the switch-
threshold (0.4V, maximum), the chip is in the shutdown
ing frequency of the high-side switch and keeps regulat-
and only low leakage current is taken from VCC. When EN
ing it at a constant frequency in PWM mode. The design
is between 1.2V to 1.7V, and APW8879A will enter the Ul-
improves the frequency variation and is more outstanding
trasonic mode. The unique ultrasonic mode maintains the
than a conventional constant on-time controller, which
switching frequency above 32kHz, which eliminates noise
has large switching frequency variation over input voltage,
in audio application.
output current and temperature. Both in PFM and PWM,
the on-time generator, which senses input voltage on VIN
pin, provides very fast on-time response to input line tran-
sients. Power-Up Control Logics
Another one-shot sets a minimum off-time (typical: 200ns).
State EN VCC VOUT CLK LDO
The on-time one-shot is triggered if the error comparator is
high, the low-side switch current is below the current-limit S0 1 ON ON ON ON

threshold, and the minimum off-time oneshot has timed S3/S5 0 ON OFF OFF ON
out.
LP# Pin Control
Pulse-Frequency Modulation (PFM) Mode
APW8879A uses the LP# pin to control voltage scaling
In PFM mode, an automatic switchover to pulse-frequency function on thelow power mode.
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the LP# Control Voltage Table
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between State LP# VOUT
PFM and PWM operation to coincide with the boundary S0 H 3.36
between continuous and discontinuous inductor-current
operation (also known as the critical conduction point). S3/S5 L 3.23
The on-time of PFM is given by:

1 VO U T
TO N - P F M = ×
FS W VI N

Where FSW is the nominal switching frequency of the con-

verter in PWM mode. Similarly, the on-time of ultrasonic
mode is the same with PFM mode. The description of ul-
trasonic mode will be illustrated later.

The load current at handoff from PFM to PWM mode is

given by:

1 VI N - VO U T
IL O A D (P F M to P W M) = × × TO N - P F M
2 L
V -V 1 V
= IN O U T × × OUT
2L FS W VI N

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Rev. A.5 – Apr., 2019
APW8879A
Function Descriptions (Cont.)
Soft-Start Over-Voltage Protection (OVP)
The APW8879A has a built-in soft-start to control the rise The over voltage function monitors the output voltage by
rate of the output voltage and limit the input current surge VOUT pin. Should the VOUT voltage increase over 125%
during start-up. During soft-start, an internal voltage ramp of the reference voltage due to the high-side MOSFET fail-
connected to one of the positive inputs of the error ampli- ure or for other reasons, the over voltage protection com-
fier, rises up to replace the reference voltage until the volt- parator will turn off the power MOSFET and shut down the
age ramp reaches the reference voltage. Then, the voltage IC. Once an over-voltage fault condition is set, it can only
on FB regulated at reference voltage. be reset by toggling EN or VIN power-on-reset signal.
In the event of under-voltage, over-voltage, over-tempera-
ture or shutdown, the chip enables the soft-stop function. Current Limit
The soft-stop function discharges the output voltages using
an internal MOSFET. The APW8879A uses the high-side MOSFET’s RDS(ON) and
the low-side MOSFET’s RDS(ON) of the synchronous rectifier
Power OK Indicator as a current-sensing element. The high side current limit
POK is actively held low in shutdown and soft-start. In circuit employs a “peak” current-sensing algorithm, and
the soft-start process, the POK is an open-drain. When the Low side current limit circuit employs a “valley” cur-
the soft-start is finished, the POK is released. In normal rent-sensing algorithm(See Figure 1).
operation, the POK window is from 90% to 125% of the If the magnitude of the current-sense signal at LX pin is
converter reference voltage.When the output voltage stays above the current-limit threshold, the PWM is not allowed
within this window, POK signal will become high. When the to initiate a new cycle. The actual peak current is greater
output voltage outruns 90% or 125% of the target voltage, than the current-limit threshold by an amount equal to the
POK signal is pulled low immediately. inductor ripple current. Therefore, the exact current-limit
In order to prevent false POK drop, capacitors need to characteristic and maximum load capability are a function
parallel at the output to confine the voltage deviation with of the sense resistance, inductor value, and input voltage.
severe load step transient. The PWM controller uses the low-side MOSFETs on-resis-
tance RDS(ON) to monitor the current for protection against
Under-Voltage Protection (UVP) shorted outputs. The MOSFET’s RDS(ON) is varied by tem-
perature and gate to source voltage, the user should de-
In the process of operation, if a short circuit occurs, the
termine the maximum RDS(ON) in manufacture’s datasheet.
output voltage will drop quickly. When load current is big-
The PCB layout guidelines should ensure that noise and
ger than current limit threshold value, the output voltage
DC errors do not corrupt the current-sense signals at LX.
will fall out of the required regulation range. The under-
Place the hottest power MOSFETs as close to the IC as
voltage protection circuit continually monitors the VOUT
possible for best thermal coupling. When combined with
voltage after soft-start is completed. If a load step is strong
the under-voltage protection circuit, this current-limit meth-
enough to pull the output voltage lower than the under
od is effective in almost every circumstance.
voltage threshold, the under voltage threshold is 70% of
the nominal output voltage, the internal UVP delay counter
starts to count. After 3us de-bounce time, the device turns
IPEAK
off both high side and low-side MOSFET with latched.
INDUCTOR CURRENT

Toggling EN pin to low or recycling VIN will clear the latch

and bring the chip back to operation.
IOUT ΔI

ILIMIT

0 Time

Figure 1. Current Limit algorithm

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Rev. A.5 – Apr., 2019
APW8879A
Function Descriptions (Cont.)
Current Limit (Cont.)
An over-current condition will shut down the device, the
VOUT voltage is also discharged to the GND by an internal
resistor, requiring a VIN or EN re-enable again to restart
IC. When the OCP fault is detected, the POK pin will pull
down and latch off the converter. The fault will remain
latched until the EN pin has been pulled below the falling
EN threshold voltage or if VCC has decayed below the fall-
ing POR threshold voltage.

Over-Temperature Protection (OTP)

When the junction temperature increases above the rising
threshold temperature TOTP, the IC will enter the over tem-
perature protection state that suspends the PWM, which
forces the UG and LG gate drivers output low. The thermal
sensor allows the converters to start a start-up process
and regulate the output voltage again after the junction
temperature cools by 30oC. The OTP designed with a 30oC
hysteresis lowers the average TJ during continuous ther-
mal overload conditions, which increases lifetime of the
APW8879A.

Linear Regulator
The LDO regulators can supply up to 100mA for external
loads. Bypass to GND with a minimum of 4.7uF ceramic
capacitor for stability. In APW8879A, the VLDO is fixed
3.3V in standby mode. When PWM output voltage is over
Its bypass threshold (PWM is 3.0V), the internal LDO to
VOUT switchover is active. These actions change the
current path to power the loads from the PWM regulator
voltage, rather than from the internal linear regulator. This
LDO is not controlled by EN and LP#.

CLK for Charge Pump

The 250kHz clock signal drives an external charge pump
circuit, the charge pump circuit can generate approximate
10-12V DC voltage. The example of charge pump circuit is
shown in typical application circuit.

CopyrightANPEC Electronic Corp. 15 www.anpec.com.tw

Rev. A.5 – Apr., 2019
APW8879A
Application Information
Output Inductor Selection These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
The duty cycle (D) of a buck converter is the function of
capacitors have to be paralleled to achieve the desired
the input voltage and output voltage. Once an output volt-
ESR value. If the output of the converter has to support
age is fixed, it can be written as:
another load with high pulsating current, more capacitors
are needed in order to reduce the equivalent ESR and
VO U T suppress the voltage ripple to a tolerable level. A small de-
D=
VI N coupling capacitor (1mF) in parallel for bypassing the noise
is also recommended, and the voltage rating of the output
The inductor value (L) determines the inductor ripple curr- capacitors are also must be considered.
ent, IRIPPLE, and affects the load transient response. To support a load transient that is faster than the switching
Higher inductor value reduces the inductor’s ripple current frequency, more capacitors are needed for reducing the
and induces lower output ripple voltage. The ripple current voltage excursion during load step change. Another aspect
and ripple voltage can be approximated by: of the capacitor selection is that the total AC current going
through the capacitors has to be less than the rated RMS
VI N - VO U T VO U T current specified on the capacitors in order to prevent the
IR I P P L E = × capacitor from over-heating.
FS W × L VI N
Input Capacitor Selection
Where FSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased The input capacitor is chosen based on the voltage rating
and the ripple current and voltage are reduced, a trade off and the RMS current rating. For reliable operation, select-
exists between the inductor’s ripple current and the regula- ing the capacitor voltage rating to be at least 1.3 times
tor load transient response time. higher than the maximum input voltage. The maximum
A smaller inductor will give the regulator a faster load tran- RMS current rating requirement is approximately IOUT/2,
sient response at the expense of higher ripple current. where IOUT is the load current. During power-up, the input
Increasing the switching frequency (FSW) also reduces the capacitors have to handle great amount of surge current.
ripple current and voltage, but it will increase the switch- For low-duty notebook applications, ceramic capacitor is
ing loss of the MOSFETs and the power dissipation of the recommended. The capacitors must be connected be-
converter. The maximum ripple current occurs at the maxi- tween the drain of high-side MOSFET and the source of
mum input voltage. low-side MOSFET with very low-impedance PCB layout.
A good starting point is to choose the ripple current to be
approximately 30% of the maximum output current. Once Thermal Consideration
the inductance value has been chosen, selecting an in- Because the APW8879A build-in high-side and low-side
ductor that is capable of carrying the required peak current MOSFET, the heat dissipated may exceed the maximum
without going into saturation. In some types of inductors, junction temperature of the part in applications. If the junc-
especially core that is made of ferrite, the ripple current will tion temperature reaches approximately 150oC, both pow-
increase abruptly when it saturates. This results in a larger er switches will be turned off and the LX node will become
output ripple voltage. Besides, the inductor needs to have high impedance. To avoid the APW8879A from exceeding
low DCR to reduce the loss of efficiency. the maximum junction temperature, the user will need to
do some thermal analysis. The goal of the thermal analy-
Output Capacitor Selection sis is to determine whether the power dissipated exceeds
Output voltage ripple and the transient voltage deviation the maximum junction temperature of the part. The main
are factors that have to be taken into consideration when power dissipated by the part is approximated:
selecting an output capacitor. Higher capacitor value and
lower ESR reduce the output ripple and the load transient PUPPER=I2OUT(1+TC)(RDS(ON))D+0.5(IOUT)(VIN)(tSW)FSW
drop. Therefore, selecting high performance low ESR ca- PLOWER=I2OUT(1+TC)(RDS(ON))(1-D)
pacitors is recommended for switching regulator applica-
tions. In addition to high frequency noise related to MOS- IOUT is the load current
FET turn-on and turnoff, the output voltage ripple includes TC is the temperature dependency of RDS(ON)
the capacitance voltage drop DVCOUT and ESR voltage drop FSW is the switching frequency
DVESR caused by the AC peak-to-peak inductor’s current. tSW is the switching interval
These two voltages can be represented by: D is the duty cycle

Note that both internal MOSFETs have conduction losses

IR I P P L E
DCO U T = while the upper MOSFET include an additional transition
8 × CO U T × FS W loss. The switching internal, tSW, is the function of the
reverse transfer capacitance CRSS. The (1+TC) term factors
DVE S R = IR I P P L E × RE S R
in the temperature dependency of the RDS(ON) and can be
extracted from the "RDS(ON) vs. Temperature" curve of the
power MOSFET. In APW8879A case, the RDS(ON) is about
25mΩ from specification table.

CopyrightANPEC Electronic Corp. 16 www.anpec.com.tw

Rev. A.5 – Apr., 2019
APW8879A
Application Information (Cont.)
Recommended Minimum Footprint 5. Locate the resistor-divider close to the FB pin to mini-
mize the high impedance trace. In addition, FB pin traces
FC - TQFN 2x3 -12 can’t be close to the switching signal traces (BOOT, and
2.0
LX).
Unit:mm 6. A 4-layer layout is strongly recommended to achieve
better thermal performance.
0.5 *

0.5 * 0.5 *
0.4

0.25

0.5 1.2

1.0 3.0

1.2

0.4

0.5 *

* Just Recommend

0.25
0.5

Layout Consideration

In any high switching frequency converter, a correct layout

is important to ensure proper operation of the regulator.
In general, using short and wide printed circuit traces
should minimize interconnecting impedances and the
magnitude of voltage spike.
In addition, signal and power grounds are to be kept sep-
arating and finally combined using ground plane construc-
tion or single point rounding.
The signal ground and the power ground is at the negative
Side of the output capacitor on each channel, where there
is less noise. Noisy traces beneath the IC are not recom-
mended. Below is a checklist for your layout:
1. Keep the switching nodes (BOOT, and LX) away from
sensitive small signal nodes(VOUT) since these nodes are
fast moving signals. Therefore, keep traces to these nodes
as short as possible and there should be no other weak
signal traces in parallel with theses traces on any layer.
2. Place the high-current paths (VIN, GND and LX) very
close to the device and wide traces. The PGND trace
should be as wide as possible (It should be the top priori-
ty).
3. Decoupling capacitors, the resistor-divider, and boot ca-
pacitor should be close to their pins. (For example, place
the decoupling ceramic capacitor close to the drain of the
high-side MOSFET as close as possible and on the same
layer as the IC.)
4. The input bulk capacitors should be close to the drain
of the high-side MOSFET, and the output bulk capacitors
should be close to the loads. the input capacitor’s ground
should be close to the grounds of the output capacitors
and low-side MOSFET.

CopyrightANPEC Electronic Corp. 17 www.anpec.com.tw

Rev. A.5 – Apr., 2019
APW8879A
Package Information
TQFN2x3-12P

D A

E
Pin 1

L1

A1
A3
NX
aaa C
ex2

SEATING PLANE
e

Pin 1 Corner
L

b e

S TQFN2*3-12
Y
M
B
MILLIMETERS INCHES
O
L MIN. MAX. MIN. MAX.
A 0.70 1.00 0.028 0.039

A1 0.00 0.05 0.000 0.002

A3 0.20 REF 0.008 REF
b 0.20 0.30 0.008 0.012
D 1.90 2.10 0.075 0.083
E 2.90 3.10 0.114 0.122

e 0.50 BSC 0.020 BSC

L 0.35 0.45 0.014 0.018
L1 1.15 1.25 0.045 0.049

aaa 0.08 0.003

CopyrightANPEC Electronic Corp. 18 www.anpec.com.tw

Rev. A.5 – Apr., 2019
APW8879A
Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 A
B OD1 B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F

178.0±2.00 50 MIN. 12.4+2.00

-0.00
13.0+0.50
-0.20 1.5 MIN. 20.2 MIN. 12.0±0.20 1.75±0.10 5.50±0.05

TQFN2x3
P0 P1 P2 D0 D1 T A0 B0 K0

4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 1.0 MIN. 0.30±0.05 2.30±0.20 3.30±0.20 1.00±0.20
-0.00
(mm)

Devices Per Unit

Package type Packing Quantity
TQFN(2x3) Tape & Reel 1500

CopyrightANPEC Electronic Corp. 19 www.anpec.com.tw

Rev. A.5 – Apr., 2019
APW8879A
Taping Direction Information
TQFN2x3-12P

USER DIRECTION OF FEED

Classification Profile

CopyrightANPEC Electronic Corp. 20 www.anpec.com.tw

Rev. A.5 – Apr., 2019
APW8879A
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature (Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Package Volume mm3 Volume mm3
Thickness <350 >350
<2.5 mm 235 °C 220 °C
>2.5 mm 220 °C 220 °C

Table 2. Pb-free Process – Classification Temperatures (Tc)

Package Volume mm3 Volume mm3 Volume mm3
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
>2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM ≧ 2KV
MM JESD-22, A115 VMM ≧ 200V
Latch-Up JESD 78 10ms, 1tr ≧ 100mA

CopyrightANPEC Electronic Corp. 21 www.anpec.com.tw

Rev. A.5 – Apr., 2019
APW8879A
Customer Service

Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

CopyrightANPEC Electronic Corp. 22 www.anpec.com.tw

Rev. A.5 – Apr., 2019