CHAPTER - 1

INTRODUCTION

1.1 OERVIEW OF MEMORY

Memory is a critical component in computing systems, acting as the

workspace where the processor temporarily stores data and instructions required for
execution. It enables fast access to data, bridging the gap between the high-speed
processor and slower storage devices like hard drives or solid-state drives (SSDs).
Without memory, the processor would have to retrieve data from storage for each
operation, significantly slowing down overall system performance. Memory is
classified into two primary categories: volatile and non-volatile. Volatile memory,
such as Random Access Memory (RAM), stores data only while the system is
powered, meaning that all data is lost when the power is turned off. In contrast, non-
volatile memory, like Read-Only Memory (ROM) and flash memory, retains data
even without power, which is essential for permanent storage of system firmware and
user data.

The volatile memory is Static Random Access Memory (SRAM), which stores
data that requires constant power to maintain its state. Unlike Dynamic RAM
(DRAM), which needs periodic refreshing, SRAM offers faster access times and
higher stability, making it an ideal choice for applications requiring high-speed data
retrieval, such as CPU caches and graphics memory as shown in Fig. 1.1.

Fig.1.1 Digital memory

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1.2 STATIC RANDOM ACCESS MEMORY (SRAM)

Static Random Access Memory (SRAM) is a type of volatile memory widely

used in digital circuits for efficient data storage as shown in Fig. 1.2. Unlike Dynamic
Random Access Memory (DRAM), which necessitates periodic refreshing to maintain
data integrity, SRAM retains its information as long as power is supplied. This
characteristic makes SRAM particularly advantageous for applications requiring rapid
data access, such as cache memory in processors, mobile devices, and various
embedded systems.

The architecture of SRAM cells typically employs six transistors (6T) as

shown in Fig. 1.3, which consist of a combination of NMOS and PMOS transistors
arranged to hold a single bit of data. At the core of an SRAM cell is a pair of cross-
coupled inverters, forming a bi- stable latch that stabilizes the stored information. The
efficiency of read and write operations is facilitated through access transistors linked
to bit lines allowing for quick data retrieval and updating capabilities.

Due to its high performance the SRAM plays a crucial role in modern
computing systems, especially in scenarios where speed is paramount. Its advantages
at the cost of higher power consumption and larger cell area compared to DRAM.
These factors limit the scalability of SRAM. This leads to large- scale storage
applications prompting the need for ongoing research to optimize SRAM designs
further.

To address the challenges associated with traditional Silicon-based

Complementary Metal-Oxide-Semiconductor (CMOS) technology at nano-scale
dimensions, innovative solutions are being explored. Among these, Carbon Nanotube
Field Effect Transistors (CNTFETs) present a promising alternative, offering
enhanced performance and energy efficiency. The unique properties of CNTFETs
make them an attractive option for improving SRAM designs and overcoming the
limitations posed by conventional transistors.

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 Fig. 1.2 Static Random Access Memory (SRAM)

1.2.1 FEATURES OF SRAM

 High-Speed Operation: SRAM offers faster access times compared to

DRAM (Dynamic RAM) because it does not need to be refreshed
periodically. This makes SRAM ideal for applications where quick data
access is essential, such as in CPU cache memory.
 Static Nature: Unlike DRAM, which requires periodic refreshing of its
stored data, SRAM retains data as long as power is supplied. This “static”
nature is due to the bi-stable latching circuitry used to store each bit.
 Low Latency: SRAM has very low read and write latency making it highly
suitable for applications requiring rapid data storage and retrieval, such as
high-speed caches in microprocessors.
 High Power Consumption: Although SRAM does not require refreshing
like DRAM, it consumes more power because it continuously draws current
to maintain data, even when not being accessed. This makes it less energy-
efficient compared to DRAM.
 Complex Cell Structure: Each SRAM cell typically consists of six
transistors (6T), making it more complex and larger in size compared to
DRAM cells (which use only one transistor and one capacitor). This larger
size limits its memory density and increases cost per bit.
 Volatile Memory: Like all RAM, SRAM is volatile, meaning it loses its
stored data when power is turned off. This makes it unsuitable for long-term
data storage, which is where non-volatile memory types like flash come in.
 Used in Cache Memory: Due to its high speed and reliability, SRAM is
commonly used in various cache levels (L1, L2, L3) in processors, where
speed is critical for performance.
 No Refresh Needed: One of the key benefits of SRAM is that it doesn’t need

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 to be refreshed periodically, unlike DRAM, which results in faster performance
and simpler control logic.
 Lower Density and Higher Cost: SRAM requires more transistors per bit of
memory compared to DRAM, making it less dense and more expensive to
produce. Hence, it is typically used for small amounts of memory where
speed is critical rather than in main memory.
 Stable and Reliable: Due to its design the SRAM offers stable performance
without needing complex refresh circuitry. It is more reliable and predictable
in environments where consistent performance is necessary.

Fig. 1.3 Basic 6T Binary SRAM Cell

1.3 DYNAMIC RANDOM ACCESS MEMORY (DRAM)

Dynamic Random Access Memory (DRAM) is a type of memory used in

computers and other electronic devices to store data temporarily. It is one of the most
common forms of volatile memory as shown in the Fig. 1.4. DRAM stores each bit of
data in a cell consisting of a capacitor and a transistor. The capacitor holds the charge,
representing data, while the transistor acts as a switch to read or write the data to the
capacitor. Since capacitors tend to leak charge over time, the data stored in DRAM
must be periodically refreshed, which distinguishes it from Static RAM (SRAM),
where data remains intact as long as power is supplied.

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 Fig. 1.4 Dynamic Random Access Memory

The primary advantage of DRAM over other types of memory is its cost and
density. DRAM is relatively inexpensive to manufacture and can store a large amount
of data in a small physical space, making it ideal for use in systems requiring large
amounts of fast, temporary memory, such as personal computers, smartphones, and
gaming consoles. However, its need for constant refreshing leads to higher power
consumption compared to SRAM, and the process of refreshing can introduce delays,
making DRAM slower in certain applications where speed is critical.

Despite these drawbacks, DRAM continues to be widely used due to its

efficiency in terms of space and cost. Over the years, advancements in DRAM
technology, such as the development of DDR (Double Data Rate) memory, have
significantly increased its speed and performance. DDR memory, in particular, allows
data to be transferred on both the rising and falling edges of the clock signal,
effectively doubling the data transfer rate without increasing the clock speed. The
evolution of DRAM technology continues to keep pace with the ever-growing
demands for faster, larger memory capacities in computing devices.

1.3.1 APPLICATIONS OF DRAM

 Main Memory in Computers: DRAM is widely used as the main

memory in computers due to its high density and lower cost per bit.
 Graphics Cards: Often found in graphics processing units (GPUs) for
handling large textures and rendering tasks.
 Mobile Devices: In mobile phones and tablets, DRAM provides a
balance between performance and power efficiency.
 Servers: Data centres use DRAM for memory-intensive applications due
to its density and relatively low cost.

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1.4 CMOS-Based SRAM cell

Complementary Metal-Oxide-Semiconductor (CMOS) technology forms the

foundation of SRAM cells, employing a configuration of MOSFETs (Metal-Oxide-
Semiconductor Field-Effect Transistors) to achieve stable data storage and rapid
access. The CMOS-based SRAM cell consists of six transistors organized in a cross-
coupled latch structure.

At its core, the SRAM cell leverages the fundamental principles of CMOS
technology, employing both n-type and p-type MOSFETs in pairs to create two
inverters. The cross-coupled inverters maintain a bi-stable state, holding one bit of
information by perpetuating a feedback loop as shown in Fig. 1.5. When properly
biased, this loop ensures that the SRAM cell retains its stored data without requiring
periodic refresh cycles, making it suitable for applications where fast and constant
access to data is necessary.

Each SRAM cell comprises two access transistors that control read and write
operations. These access transistors enable data to be written into or read from the
SRAM cell by providing a path for the data to flow in or out of the cell. This design
facilitates high-speed operations and low latency, making CMOS-based SRAM cells
ideal for cache memories and high-performance computing.

Fig. 1.5 CMOS based SRAM circuit

Despite its advantages, CMOS-based SRAM cells possess certain drawbacks.

One significant limitation is their relatively larger size compared to other memory
technologies, such as dynamic RAM (DRAM). The six-transistor structure required
for each bit of data in an SRAM cell demands more silicon real estate, leading to

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increased chip area consumption. This larger footprint impacts overall chip size and
production costs, especially in applications requiring extensive memory capacities.

Additionally, CMOS-based SRAM cells tend to consume more power

compared to alternative memory types like DRAM or flash memory. The continuous
power consumption stems from leakage currents through the transistors, contributing
to higher energy usage, especially in devices that prioritize low power consumption
and battery life.

Moreover, as semiconductor manufacturing technology advances toward

smaller process nodes, CMOS-based SRAM cells face challenges related to scaling.
Shrinking transistor sizes can exacerbate issues with leakage currents, reliability, and
susceptibility to soft errors caused by radiation, impacting the stability and integrity
of stored data.

Efforts to mitigate these drawbacks involve innovative design techniques,

materials exploration, and novel architectures aimed at reducing power consumption,
improving scalability, and optimizing performance while maintaining data integrity.
Research and development continue to address these challenges, striving to enhance
CMOS-based SRAM cells to meet the evolving demands of modern technology.

Advancements in these areas are critical for the future of memory technology,
particularly as applications in mobile devices, IoT, and high-performance computing
continue to grow, requiring solutions that balance power efficiency, performance, and
data reliability.

1.5 CHALLENGES WITH CONVENTIONAL CMOS TECHNOLOGY

The technology advances and the demand for smaller, faster, and more efficient
devices grows, conventional Complementary Metal-Oxide-Semiconductor (CMOS)
technology faces significant challenges. One of the primary issues is power leakage
which becomes increasingly problematic as transistor dimensions shrink. This leakage
not only contributes to higher static power consumption but also raises thermal
management concerns leading to reliability issues in integrated circuits. As transistors
become smaller the insulating layers thin, allowing for more substantial leakage
currents that adversely affect overall performance.

Another critical challenge is the reduction in noise margins due to short-

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channel effects. As CMOS devices scale down, the electric fields become stronger
which can lead to phenomena such as drain-induced barrier lowering (DIBL) and
increased threshold voltage variability. These effects compromise the stability of
stored data and can lead to errors in logic operations making it difficult to maintain
reliable performance in ultra-scaled technologies. This growing susceptibility to noise
necessitates more complex circuit designs to ensure operational integrity.

The reliability of conventional CMOS technology is also hindered by process

variations. As manufacturing techniques evolve achieving uniformity in device
fabrication becomes increasingly challenging. Variations in material properties,
dimensions, and environmental conditions can lead to inconsistent performance
across chips resulting in decreased yield rates and increased costs. This variability
poses significant hurdles for the semiconductor industry, especially as it seeks to meet
the demands for high-density, high-performance integrated circuits.

To overcome these challenges, the exploration of alternative materials and

device architectures has gained traction. Carbon Nanotube Field Effect Transistors
(CNTFETs) have emerged as a promising solution, leveraging the superior electrical,
mechanical, and thermal properties of carbon nanotubes. CNTFETs exhibit reduced
power dissipation and improved carrier mobility, making them suitable for
overcoming the limitations of traditional CMOS technology.

1.6 CARBON NANOTUBE FIELD EFFECT TRANSISTOR (CNTFETs)

The Carbon Nanotube Field-Effect Transistor (CNTFET) is an emerging

technology that leverages the unique electrical properties of carbon nanotubes
(CNTs) to overcome the limitations of traditional silicon-based MOSFETs (Metal-
Oxide-Semiconductor Field-Effect Transistors). CNTFETs are promising candidates
for next-generation nanoelectronics devices due to their superior electrical,
mechanical, and thermal properties, as well as their potential for miniaturization and
lower power consumption.

Carbon nanotubes, which are cylindrical nanostructures composed of rolled-

up sheets of graphene can function as both the channel material and conducting
electrodes in CNTFETs as shown in Fig.1.6. Depending on the configuration and
chirality of the carbon nanotube they can exhibit either metallic or semiconducting
properties which makes them highly versatile in electronic applications. The

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semiconducting CNTs are particularly useful for transistor channels because of their
high electron mobility, ballistic transport behavior, and ability to operate at lower
voltages compared to conventional silicon.

Fig.1.6 Carbon Nanotube Field Effect Transistor (CNTFET)

CNTFETs are advanced transistors that use carbon nanotubes as the channel
offering superior performance and lower power consumption compared to silicon-
based MOSFETs. Their high electron mobility and miniaturization potential make
them ideal for next-generation nanoelectronics.

The unique structure of carbon nanotubes contributes to the exceptional

electrical characteristics of CNTFETs. Due to their one-dimensional geometry carbon
nanotubes enable high ballistic transport, that electrons can travel through the material
with minimal scattering. This property enhances the devices speed and efficiency
allowing CNTFETs to operate at frequencies far exceeding those of traditional silicon
MOSFETs. The CNTs exhibit excellent thermal conductivity which helps in
dissipating heat more effectively during operation thus improving the overall
reliability and performance of the device. These attributes make CNTFETs
particularly advantageous for applications requiring high-speed data processing such
as in microprocessors and high-performance computing.

In addition to their superior electrical performance, CNTFETs hold great

promise for achieving lower power consumption in electronic devices. The ability to
operate at lower voltages reduces energy requirements significantly which is critical
in the context of portable and battery-operated devices. The demand for energy-
efficient solutions continues to rise the CNTFETs can play a vital role in the
development of sustainable electronics. Their potential for integration with flexible

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and lightweight materials opens new avenues for innovative applications in fields
such as wearable technology and flexible displays. The CNTFETs are expected to
pave the way for a new generation of electronic devices that are not only faster and
more efficient but also environmentally friendly.

1.6.1 STRUCTURE OF CNTFETs

The first carbon nanotube field-effect transistors (CNTFETs) were introduced in

1998. These pioneering devices were created by depositing single-wall carbon
nanotubes (CNTs) from solution onto oxidized silicon wafers, which had been pre-
patterned with gold or platinum electrodes. As depicted in Fig. 1.5, the CNTFET is
meticulously designed to optimize performance.

• Carbon Nanotube (CNT) Channel

At the heart of a CNTFET is the carbon nanotube, a cylindrical nanostructure
made from a rolled-up sheet of graphene. The CNT acts as the channel material
through which charge carriers (electrons or holes) move between the source and drain
terminals.

Fig.1.7 Structure of Carbon Nanotube Field Effect Transistor

• Semiconducting CNTs
These are primarily used in CNTFETs for switching purposes because they
exhibit properties similar to semiconductors, such as the ability to form a channel that
can be controlled by a gate voltage.

• Metallic CNTs
These nanotubes, due to their excellent conductivity, can be used for
interconnections or as contact electrodes. The channel length (the distance between
the source and drain) in CNTFETs is typically on the nanoscale, allowing for ultra-
fast carrier transport. The unique structure of the carbon nanotube allows for ballistic

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transport, where charge carriers move through the channel with minimal scattering,
leading to high mobility and efficient operation.

• Source and Drain Electrodes

The source and drain electrodes are the terminals between which the current
flows when the device is active. In CNTFETs, these electrodes are typically made of
metal or doped CNTs and are connected to the carbon nanotube channel.

• Source Electrode
This is where the carriers (electrons or holes) enter the carbon nanotube
channel.

• Drain Electrode
This is where the carriers exit the channel. The behaviour of the current
between the source and drain is controlled by the gate voltage applied to the gate
terminal. In Schottky-Barrier CNTFETs, a Schottky barrier forms at the metal-CNT
junction, affecting the carrier injection into the channel through tunnelling. In
MOSFET-like CNTFETs, the source and drain regions are typically doped to enhance
carrier injection without relying on tunnelling.

• Gate Electrode
The gate electrode plays a central role in controlling the current flow through
the CNT channel. The gate is placed either above or below the carbon nanotube,
separated from the CNT by a dielectric layer (similar to the gate oxide in traditional
MOSFETs). The gate applies an electric field to the carbon nanotube channel,
modulating its conductivity.

• Substrate
The substrate provides mechanical support to the entire structure of the
CNTFET. In some CNTFET designs, the substrate can also serve as the back gate (in
back-gated CNTFETs). The choice of substrate material depends on the specific
application of the CNTFET. Common substrates include silicon, silicon dioxide, and
flexible substrates for certain flexible electronics applications.

1.6.2 TYPES OF CNTFETs

Carbon Nanotube Field-Effect Transistors (CNTFETs) have emerged as

promising alternatives to traditional silicon-based transistors, offering several
advantages such as higher carrier mobility, lower power consumption, and the ability

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to scale to smaller dimensions. Based on their structure and operating principles,
CNTFETs can be categorized into two main types as shown in Fig.1.8. The major two
types areSchottky-Barrier CNTFETs (SB-CNTFETs) and MOSFET-like CNTFETs
(MOS-CNTFETs). These types have distinct characteristics, and each has been
explored for different applications in the field of nanoelectronics.

Fig. 1.8 Classification of Carbon Nanotube Field Effect Transistors

1.6.3 FEATURES OF CNTFET

• High Electron Mobility: Carbon nanotubes (CNTs) exhibit high electron

mobility, which allows for faster charge carrier transport compared to
conventional silicon-based MOSFETs. This enables CNTFETs to operate at
higher frequencies and speeds, making them ideal for high-performance
applications.
• Ballistic Transport: In CNTFETs, electrons can travel through the channel
without scattering, known as ballistic transport. This significantly reduces
resistance and power loss, improving overall device efficiency and
performance, especially at nanoscale dimensions.
• Low Power Consumption: Due to their excellent electrical conductivity and
the ability to operate at lower voltages, CNTFETs consume less power than
traditional MOSFETs. This makes them suitable for energy-efficient
electronic devices and systems requiring low-power operation.
• Scalability and Miniaturization: CNTFETs can be scaled down to very small

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dimensions (sub-nanometre level) due to the nanoscale size of carbon nanotubes.
This allows for greater transistor density on a chip, supporting the continued
miniaturization of electronic devices, in line with Moore's law.
• Reduced Short-Channel Effects: Short-channel effects, a common problem
in traditional silicon transistors as they shrink in size, are significantly
reduced in CNTFETs. The one-dimensional structure of CNTs offers better
control over the channel, minimizing leakage currents and improving overall
performance in scaled-down devices.
• Chirality-Dependent Semiconducting Behaviour: The electronic properties
of CNTs depend on their chirality (the specific angle at which graphene
sheets are rolled into tubes). Semiconducting CNTs are preferred in
CNTFETs due to their ability to switch on and off, while metallic CNTs can
lead to undesirable behaviour.
• High Current-Carrying Capacity: CNTFETs have a higher current-carrying
capacity than silicon MOSFETs, meaning they can handle more electrical
current without degrading performance. This makes them ideal for high-
performance logic circuits and applications that require high power density.
• Improved Thermal Conductivity: Carbon nanotubes possess excellent
thermal conductivity, allowing heat to dissipate more effectively. This helps
reduce the risk of thermal damage in CNTFETs, leading to longer device
lifetimes and better stability under high-performance conditions.
• Tuneable Threshold Voltage: The threshold voltage in CNTFETs can be
tuned by controlling the diameter and chirality of the carbon nanotubes. This
flexibility allows for the design of devices optimized for specific applications.
• Environmental Stability: CNTFETs exhibit good stability in various
environmental conditions, making them suitable for a wide range of
applications, including those in harsh environments like space or industrial
settings.
• Potential for Flexible Electronics: Due to the mechanical flexibility of
carbon nanotubes, CNTFETs are well-suited for flexible electronics. This
makes them useful in emerging technologies such as wearable devices,
bendable displays, and flexible sensors.
• Challenges in Fabrication: Despite their potential, the large-scale fabrication
of CNTFETs faces challenges, such as controlling the alignment and purity of
CNTs, and addressing variability in device performance due to differences in

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 chirality and diameter. Ongoing research is working to overcome these
hurdles.

1.7 SCOPE OF THE PROJECT

The scope of this project focuses on investigating and evaluating the

performance of Static Random Access Memory (SRAM) cells designed using Carbon
Nanotube Field Effect Transistors (CNTFETs). This research aims to explore the
potential of CNTFETs as a promising alternative to conventional CMOS technology
in SRAM design. As CMOS technology approaches its physical limits due to scaling
issues, CNTFETs offer several advantages, including higher carrier mobility, lower
power consumption, and the ability to overcome short-channel effects. The project
examines how CNTFET-based SRAM cells can improve the read and write
performance while reducing power consumption, making them suitable for future
high-performance and low-power memory applications.

The project includes an in-depth performance analysis of CNTFET-based

SRAM cells in terms of key metrics such as power consumption, speed, stability, and
area efficiency. This comparison with conventional CMOS-based SRAM will
highlight the areas where CNTFET technology excels, as well as the challenges that
remain for its adoption. The research will also explore the scalability of CNTFET-
based SRAM and its potential integration into modern nanotechnology-driven
electronic systems.

The project extends to simulating CNTFET-based SRAM designs using

advanced simulation tools to measure and compare their performance across different
technology nodes. The results will provide insights into the feasibility of using
CNTFETs in commercial SRAM designs for future generations of electronic devices,
particularly for applications in portable electronics, high-speed computing, and low-
power embedded systems.

1.8 OBJECTIVES OF THE PROJECT

 To explore the potential of Carbon Nanotube Field Effect Transistors

(CNTFETs) as an alternative to traditional CMOS technology in SRAM
memory design.
 To overcome the limitations of CMOS scaling including increased leakage
currents, power dissipation, and degraded performance.

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  Leverage unique properties of CNTFETs, such as higher carrier mobility,
ballistic transport, and thermal conductivity, to design efficient SRAM cells.
 Optimize SRAM architecture for lower power consumption, faster read/write
operations, and enhanced stability.
 Analyse the scalability and practicality of CNTFET-based SRAM cells in real-
world applications.
 To assess integration challenges of CNTFETs in commercial memory systems
for compact and energy-efficient applications.

1.9 ORGANIZATION OF THE THESIS

The Organization of the thesis as follows,

Chapter 1: This chapter introduces memory systems, focusing on SRAM and its
challenges, particularly in CMOS-based designs. It highlights the limitations of
CMOS technology, such as power leakage and scalability issues, and explores Carbon
Nanotube Field-Effect Transistors (CNTFETs) as a promising alternative. The chapter
outlines the scope, objectives, and significance of employing CNTFETs for efficient
and scalable SRAM design, emphasizing their advantages in addressing future
memory application needs.

Chapter 2: This chapter provides a review of existing research related to SRAM design
and CNTFET technology. It explores various approaches to implementing SRAM, the
limitations of traditional CMOS technology and recent advancements in CNTFET.
Furthermore, it identifies gaps in current research that the project seeks to fill and
emphasizing the need for more efficient and scalable memory solutions.

Chapter 3: This chapter introduces the proposed CNTFET-based SRAM cell and offers
an overview of existing designs.

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