CHAPTER 4

Binary Adder
• A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers.
• It can be constructed with full adders connected in cascade, with the
output carry from each full adder connected to the input carry of the
next full adder in the chain.
• The interconnection of four full-adder (FA) circuits to provide a four-
bit binary ripple carry adder.

• The carries are connected in a chain through the full adders.

• The input carry to the adder is C0 , and it ripples through the full adders to
the output carry C4.
• The S outputs generate the required sum bits.
• An n -bit adder requires n full adders, with each output carry connected to
the input carry of the next higher order full adder.
Carry Propagation
• Full adder with P and G

• An obvious solution for reducing the carry propagation delay time is to employ faster gates with
reduced delays.
• Another solution is to increase the complexity of the equipment in such a way that the carry delay
time is reduced.
• There are several techniques for reducing the carry propagation time in a parallel adder.
• The most widely used technique employs the principle of carry lookahead logic.
• We define two new binary variables

• The output sum and carry can respectively be expressed as

• Gi is called a carry generate , and it produces a carry of 1 when both Ai and

Bi are 1, regardless of the input carry Ci .
• Pi is called a carry propagate , because it determines whether a carry into
stage i will propagate into stage i + 1.
• The Boolean functions for the carry outputs of each stage and
substitute the value of each Ci from the previous equations:
Logic diagram of carry lookahead generator
Four-bit adder with carry lookahead
Binary Subtractor
• The subtraction A - B can be done by taking the 2’s complement of B and adding
it to A.
Four-bit adder–subtractor (with overflow detection)
DECIMAL ADDER
• Computers or calculators that perform arithmetic operations directly in the
decimal number system represent decimal numbers in binary coded form.
• An adder for such a computer must employ arithmetic circuits that accept coded
decimal numbers and present results in the same code.
BCD Adder
• Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the
output sum cannot be greater than 9 + 9 + 1 = 19, the 1 in the sum being an input
carry.
• When the binary sum is equal to or less than 1001, the corresponding BCD
number is identical, and therefore no conversion is needed.
• When the binary sum is greater than 1001, we obtain an invalid BCD
representation. The addition of binary 6 (0110) to the binary sum converts it to
the correct BCD representation and also produces an output carry as required.
 • The condition for a correction and an output
carry can be expressed by the Boolean
function C = K + Z8Z4 + Z8Z2.
• When C = 1, it is necessary to add 0110 to
the binary sum and provide an output carry
for the next stage.

Block diagram of a BCD adder

DECODERS
• A decoder is a combinational circuit that converts binary information
from n input lines to a maximum of 2n unique output lines.
• The decoders presented here are called n -to- m -line decoders,
where m ≤ 2n .
• Their purpose is to generate the 2n minterms of n input variables.
• Each combination of inputs will assert a unique output.
Three-to-eight-line decoder
• The three inputs are decoded into eight outputs, each representing
one of the minterms of the three input variables.
Three-to-eight-line decoder
A two-to-four-line decoder with an enable input constructed
with NAND gates
4 ×16 decoder constructed with two 3 × 8 decoders
Combinational Logic Implementation

• Any combinational circuit with n inputs and m outputs can be

implemented with an n -to-2 n -line decoder and m OR gates.
• The procedure for implementing a combinational circuit by means of
a decoder and OR gates requires that
• The Boolean function for the circuit be expressed as a sum of minterms.
• A decoder is then chosen that generates all the minterms of the input
variables.
• The inputs to each OR gate are selected from the decoder outputs according
to the list of minterms of each function.
Ex: full adder
• S(x, y, z) = 𝛴(1, 2, 4, 7)
• C(x, y, z) = 𝛴(3, 5, 6, 7)
 ENCODERS

• An encoder is a digital circuit that performs the inverse operation of a

decoder.
• An encoder has 2n (or fewer) input lines and n output lines.
• The encoder can be implemented with OR gates whose inputs are
determined directly from the truth table.

• The encoder can be implemented with three OR gates.

• If two inputs are active simultaneously, the output produces an
undefined combination.
• For example, if D3 and D6 are 1 simultaneously, the output of the
encoder will be 111.
• To resolve this ambiguity, encoder circuits must establish an input
priority to ensure that only one input is encoded.
Priority Encoder
• A priority encoder is an encoder circuit that includes the priority function.
• The operation of the priority encoder is such that if two or more inputs are equal
to 1 at the same time, the input having the highest priority will take precedence.

• In addition to the two outputs x and y , the circuit has a third output designated by V ; this is a valid bit
indicator that is set to 1 when one or more inputs are equal to 1.
• If all inputs are 0, there is no valid input and V is equal to 0.
• The other two outputs are not inspected when V equals 0 and are specified as don’t-care conditions.
• Boolean functions
 MULTIPLEXERS
• A multiplexer is a combinational circuit that selects binary information from one
of many input lines and directs it to a single output line.
• The selection of a particular input line is controlled by a set of selection lines.
• Normally, there are 2n input lines and n selection lines whose bit combinations
determine which input is selected.
Two-to-one-line multiplexer
Four-to-one-line multiplexer
Quadruple two-to-one-line multiplexer
Boolean Function Implementation

• Method for implementing a Boolean function of n variables with a multiplexer

that has n - 1 selection inputs.
• The first n - 1 variables of the function are connected to the selection inputs of
the multiplexer.
Ex: consider the Boolean function: F (x, y, z) = 𝛴(1, 2, 6, 7)
Three-State Gates
• A multiplexer can be constructed with three-state gates—digital
circuits that exhibit three states.
• Two of the states are signals equivalent to logic 1 and logic 0 as in a
conventional gate.
• The third state is a high-impedance state in which
• (1) the logic behaves like an open circuit, which means that the output
appears to be disconnected,
• (2) the circuit has no logic significance, and
• (3) the circuit connected to the output of the three-state gate is not affected
by the inputs to the gate.
• The graphic symbol for a three-state buffer gate

The construction of multiplexers with three-state buffers

 HDL MODELS OF COMBINATIONAL CIRCUITS

• The logic of a module can be described in any one (or a combination)

of the following modeling styles:
• Gate-level modeling using instantiations of predefined and user-defined
primitive gates.
• Dataflow modeling using continuous assignment statements with the
keyword assign .
• Behavioral modeling using procedural assignment statements with the
keyword always .
Gate-Level Modeling
• Verilog statements to specify two vectors:
• output [0: 3] D;
• wire [7: 0] SUM;
Hierarchical design
• Two or more modules can be combined to build a hierarchical description
of a design.
• There are two basic types of design methodologies:
• top down and bottom up: the top-level block is defined and then the subblocks
necessary to
build the top-level block are identified.
• bottom-up design: the building blocks are first identified and then combined to build
the top-level block.
• Example, the binary adder. It can be considered as a top-block component
built with four full-adder blocks, while each full adder is built with two half-
adder blocks.
• In a top-down design, the four-bit adder is defined first, and then the two
adders are described.
• In a bottom-up design, the half adder is defined, then each full adder is
constructed, and then the four-bit adder is built from the full adders.
 A bottom-up hierarchical description of a four-bit adder
// Gate-level description of four-bit ripple carry adder: Description of half
adder ( Fig. 4.5b ) // Description of four-bit adder ( Fig. 4.9 )
module half_adder (S, C, x, y);
output S, C; module ripple_carry_4_bit_adder (Sum, C4, A, B, C0);
input x, y; output [3: 0] Sum;
// Instantiate primitive gates output C4;
xor (S, x, y); input [3: 0] A, B;
and (C, x, y); input C0;
endmodule wire C1, C2, C3; // Intermediate carries
// Description of full adder ( Fig. 4.8 ) // Instantiate chain of full adders
module full_adder (S, C, x, y, z); full_adder FA0 (Sum[0], C1, A[0], B[0], C0),
output S, C; FA1 (Sum[1], C2, A[1], B[1], C1),
input x, y, z; FA2 (Sum[2], C3, A[2], B[2], C2),
wire S1, C1, C2; FA3 (Sum[3], C4, A[3], B[3], C3);
// Instantiate half adders endmodule
half_adder HA1 (S1, C1, x, y);
half_adder HA2 (S, C2, S1, z);
or G1 (C, C2, C1);
endmodule
• Note that modules can be instantiated (nested) within other modules,
but module declarations cannot be nested; that is, a module
definition (declaration) cannot be placed within another module
declaration.
• In other words, a module definition cannot be inserted into the text
between the module and endmodule keywords of another module.
• The only way one module definition can be incorporated into another
module is by instantiating it.
Three-State Gates

• The high-impedance state is symbolized by z in Verilog.

• There are four types of three-state gates
• The HDL description must use a tri data type for the
output
• In order to show that they have a common
connection, it is necessary to declare m_out with the
keyword tri.
Two-to-one-line multiplexer with three-state buffers
 Dataflow Modeling
• Dataflow modeling of combinational logic uses a number of operators
that act on binary operands to produce a binary result.
• Dataflow modeling uses continuous assignments and the keyword
assign.
Dataflow description of four-bit adder

• The additionlogic is described by a single statement using the operators of addition and
concatenation.
• The plus symbol (+) specifies the binary addition of the four bits of A with the four bits of B and
the one bit of C in .
• The target output is the concatenation of the output carry C_out and the four bits of Sum.
• Concatenation of operands is expressed within braces and a comma separating the operands.
• Thus, {C_out, Sum} represents the five-bit result of the addition operation.
The conditional operator

• This operator takes three operands:

condition ? true-expression : false-expression;
• The condition is evaluated. If the result is logic 1, the true expression
is evaluated and used to assign a value to the left-hand side of an
assignment statement.
• If the result is logic 0, the false expression is evaluated.
• The two conditions together are equivalent to an if–else condition.
• The continuous assignment assign OUT select ? A : B; specifies the
condition that OUT = A if select = 1, else OUT = B if select =0.
 Behavioral Modeling
• Behavioral modeling represents digital circuits at a functional and algorithmic level.
• Behavioral descriptions use the keyword always , followed by an optional event control
expression and a list of procedural assignment statements.
• The target output of a procedural assignment statement must be of the reg data type.
• The target output of an assignment may be continuously updated, a reg data type retains its
value until a new value is assigned.
Behavioral description of four-to-one line multiplexer