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Simulator

simulator

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bedirhandurmus7
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26 views8 pages

Simulator

simulator

Uploaded by

bedirhandurmus7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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* Circuit Extracted by Tanner Research's L-Edit V8.11 / Extract V8.

11 ;
* TDB File: D:\Donem_4_2\VLSI\adder\nand.tdb
* Cell: Cell0 Version 1.61
* Extract Definition File: C:\Program Files\Tanner EDA\L-Edit Pro\tech\mosis\
mhp_n05.ext
* Extract Date and Time: 05/29/2011 - 09:59

* Warning: Layers with Unassigned AREA Capacitance.


* <Poly Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* Warning: Layers with Unassigned FRINGE Capacitance.
* <Pad Comment>
* <Poly Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* Warning: Layers with Zero Resistance.
* <Pad Comment>
* <cap using Cap-Well>
* <NMOS Capacitor>
* <PMOS Capacitor>

.tran/op 1n 200n method=bdf


.include "C:\Program Files\Tanner EDA\T-Spice Pro v6.02\models\hp05.md"
.lib "C:\Program Files\Tanner EDA\L-Edit Pro\tech\mosis\morbn20.ext"

VPOWER_SUPPLY VDD GND 5

VSourceA0 A0 GND PULSE (0 0 0 1n 1n 10n 20n)


VSourceA1 A1 GND PULSE (0 5 0 1n 1n 10n 20n)
VSourceA2 A2 GND PULSE (0 0 0 1n 1n 10n 20n)
VSourceA3 A3 GND PULSE (0 0 0 1n 1n 10n 20n)

VSourceB0 B0 GND PULSE (0 0 0 1n 1n 15n 30n)


VSourceB1 B1 GND PULSE (0 0 0 1n 1n 15n 30n)
VSourceB2 B2 GND PULSE (0 5 0 1n 1n 15n 30n)
VSourceB3 B3 GND PULSE (0 0 0 1n 1n 15n 30n)

VSourceCin Cin GND PULSE (0 0 0 1n 1n 100n 200n)

.print tran v(B0,GND) v(B1,GND) v(B2,GND) v(B3,GND) v(Cout,GND)


*v(B0,GND) v(B1,GND) v(B2,GND) v(B3,GND) v(Cin,GND) v(S,GND) v(Cout,GND)

* NODE NAME ALIASES


* 9 = VDD (441.5,108)
* 28 = B0 (84,34)
* 29 = A0 (84,52.5)
* 44 = S0 (804,-96)
* 55 = GND (433.5,-324.5)
* 56 = Cin (85,19)
* 59 = B1 (85,-49.5)
* 84 = A3 (84,-219)
* 85 = B2 (85,-189.5)
* 86 = A2 (84.5,-170.5)
* 89 = Cout (776.5,-228)
* 90 = S3 (791,-275.5)
* 116 = B3 (84.5,-238)
M_U1/M1 75 38 VDD 4 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/M1 DRAIN GATE SOURCE BULK (754 4 756 10)
M_U1/M2 75 10 VDD 4 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/M2 DRAIN GATE SOURCE BULK (725 4 727 10)
M_U1/U1/M4 39 12 VDD 3 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M4 DRAIN GATE SOURCE BULK (724 61.5 726 67.5)
M_U1/U1/M1 39 5 VDD 3 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M1 DRAIN GATE SOURCE BULK (753 61.5 755 67.5)
M_U1/M3 75 38 2 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/M3 DRAIN GATE SOURCE BULK (754 -16 756 -12)
M_U1/M4 2 10 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/M4 DRAIN GATE SOURCE BULK (750 -16 752 -12)
M_U1/U1/M3 1 12 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U1/M3 DRAIN GATE SOURCE BULK (749 40.5 751 44.5)
M_U1/U1/M2 39 5 1 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U1/M2 DRAIN GATE SOURCE BULK (753 40.5 755 44.5)
M_U1/U1/M10 12 10 VDD 15 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M10 DRAIN GATE SOURCE BULK (606 61.5 608 67.5)
M_U1/U1/M6 5 10 VDD 8 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M6 DRAIN GATE SOURCE BULK (647 61.5 649 67.5)
M_U1/U1/M5 5 B1 VDD 8 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M5 DRAIN GATE SOURCE BULK (676 61.5 678 67.5)
M_U1/U1/M12 12 10 7 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U1/M12 DRAIN GATE SOURCE BULK (606 40.5 608 44.5)
M_U1/U1/M8 6 10 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U1/M8 DRAIN GATE SOURCE BULK (672 40.5 674 44.5)
M_U1/U1/M11 7 11 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U1/M11 DRAIN GATE SOURCE BULK (602 40.5 604 44.5)
M_U1/U1/M7 5 B1 6 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U1/M7 DRAIN GATE SOURCE BULK (676 40.5 678 44.5)
M_U1/U1/M9 12 11 VDD 15 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M9 DRAIN GATE SOURCE BULK (577 61.5 579 67.5)
M_U1/U1/M13 10 11 VDD 14 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M13 DRAIN GATE SOURCE BULK (509 61.5 511 67.5)
M_U1/U1/M14 10 B1 VDD 14 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M14 DRAIN GATE SOURCE BULK (538 61.5 540 67.5)
M_U1/U1/M15 13 11 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U1/M15 DRAIN GATE SOURCE BULK (534 40.5 536 44.5)
M_U1/U1/M16 10 B1 13 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U1/M16 DRAIN GATE SOURCE BULK (538 40.5 540 44.5)
M_U2/M1 45 58 VDD 21 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/M1 DRAIN GATE SOURCE BULK (419 4 421 10)
M_U2/M2 45 20 VDD 21 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/M2 DRAIN GATE SOURCE BULK (390 4 392 10)
M_U2/U1/M1 57 19 VDD 22 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M1 DRAIN GATE SOURCE BULK (418 61.5 420 67.5)
M_U2/U1/M4 57 18 VDD 22 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M4 DRAIN GATE SOURCE BULK (389 61.5 391 67.5)
M_U2/M3 45 58 17 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/M3 DRAIN GATE SOURCE BULK (419 -16 421 -12)
M_U2/M4 17 20 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/M4 DRAIN GATE SOURCE BULK (415 -16 417 -12)
M_U2/U1/M2 57 19 16 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U1/M2 DRAIN GATE SOURCE BULK (418 40.5 420 44.5)
M_U2/U1/M3 16 18 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U1/M3 DRAIN GATE SOURCE BULK (414 40.5 416 44.5)
M_U2/U1/M6 19 20 VDD 24 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M6 DRAIN GATE SOURCE BULK (312 61.5 314 67.5)
M_U2/U1/M5 19 B0 VDD 24 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M5 DRAIN GATE SOURCE BULK (341 61.5 343 67.5)
M_U2/U1/M8 23 20 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U1/M8 DRAIN GATE SOURCE BULK (337 40.5 339 44.5)
M_U2/U1/M7 19 B0 23 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U1/M7 DRAIN GATE SOURCE BULK (341 40.5 343 44.5)
M_U2/U1/M9 18 A0 VDD 27 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M9 DRAIN GATE SOURCE BULK (242 61.5 244 67.5)
M_U2/U1/M10 18 20 VDD 27 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M10 DRAIN GATE SOURCE BULK (271 61.5 273 67.5)
M_U2/U1/M14 20 B0 VDD 30 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M14 DRAIN GATE SOURCE BULK (203 61.5 205 67.5)
M_U2/U1/M11 26 A0 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U1/M11 DRAIN GATE SOURCE BULK (267 40.5 269 44.5)
M_U2/U1/M12 18 20 26 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U1/M12 DRAIN GATE SOURCE BULK (271 40.5 273 44.5)
M_U2/U1/M16 20 B0 25 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U1/M16 DRAIN GATE SOURCE BULK (203 40.5 205 44.5)
M_U2/U1/M15 25 A0 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U1/M15 DRAIN GATE SOURCE BULK (199 40.5 201 44.5)
M_U2/U1/M13 20 A0 VDD 30 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M13 DRAIN GATE SOURCE BULK (174 61.5 176 67.5)
M_U1/U0/M4 31 40 VDD 33 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M4 DRAIN GATE SOURCE BULK (724 -43 726 -37)
M_U1/U0/M1 31 34 VDD 33 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M1 DRAIN GATE SOURCE BULK (753 -43 755 -37)
M_U1/U0/M3 32 40 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U0/M3 DRAIN GATE SOURCE BULK (749 -64 751 -60)
M_U1/U0/M2 31 34 32 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U0/M2 DRAIN GATE SOURCE BULK (753 -64 755 -60)
M_U1/U0/M10 40 38 VDD 43 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M10 DRAIN GATE SOURCE BULK (606 -43 608 -37)
M_U1/U0/M6 34 38 VDD 37 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M6 DRAIN GATE SOURCE BULK (647 -43 649 -37)
M_U1/U0/M5 34 45 VDD 37 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M5 DRAIN GATE SOURCE BULK (676 -43 678 -37)
M_U1/U0/M12 40 38 36 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U0/M12 DRAIN GATE SOURCE BULK (606 -64 608 -60)
M_U1/U0/M8 35 38 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U0/M8 DRAIN GATE SOURCE BULK (672 -64 674 -60)
M_U1/U0/M11 36 39 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U0/M11 DRAIN GATE SOURCE BULK (602 -64 604 -60)
M_U1/U0/M7 34 45 35 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U0/M7 DRAIN GATE SOURCE BULK (676 -64 678 -60)
M_U1/U0/M9 40 39 VDD 43 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M9 DRAIN GATE SOURCE BULK (577 -43 579 -37)
M_U1/U0/M13 38 39 VDD 42 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M13 DRAIN GATE SOURCE BULK (509 -43 511 -37)
M_U1/U0/M14 38 45 VDD 42 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M14 DRAIN GATE SOURCE BULK (538 -43 540 -37)
M_U1/U0/M15 41 39 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U0/M15 DRAIN GATE SOURCE BULK (534 -64 536 -60)
M_U1/U0/M16 38 45 41 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U0/M16 DRAIN GATE SOURCE BULK (538 -64 540 -60)
M_U2/U0/M1 S0 48 VDD 49 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U0/M1 DRAIN GATE SOURCE BULK (418 -43 420 -37)
M_U2/U0/M4 S0 47 VDD 49 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U0/M4 DRAIN GATE SOURCE BULK (389 -43 391 -37)
M_U2/U0/M2 S0 48 46 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U0/M2 DRAIN GATE SOURCE BULK (418 -64 420 -60)
M_U2/U0/M3 46 47 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U0/M3 DRAIN GATE SOURCE BULK (414 -64 416 -60)
M_U2/U0/M6 48 58 VDD 51 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* Circuit Extracted by Tanner Research's L-Edit V8.11 / Extract V8.11 ;
* TDB File: D:\Donem_4_2\VLSI\adder\nand.tdb
* Cell: Cell0 Version 1.61
* Extract Definition File: C:\Program Files\Tanner EDA\L-Edit Pro\tech\mosis\
mhp_n05.ext
* Extract Date and Time: 05/29/2011 - 09:59

* Warning: Layers with Unassigned AREA Capacitance.


* <Poly Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* Warning: Layers with Unassigned FRINGE Capacitance.
* <Pad Comment>
* <Poly Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* Warning: Layers with Zero Resistance.
* <Pad Comment>
* <cap using Cap-Well>
* <NMOS Capacitor>
* <PMOS Capacitor>

.tran/op 1n 200n method=bdf


.include "C:\Program Files\Tanner EDA\T-Spice Pro v6.02\models\hp05.md"
.lib "C:\Program Files\Tanner EDA\L-Edit Pro\tech\mosis\morbn20.ext"

VPOWER_SUPPLY VDD GND 5

VSourceA0 A0 GND PULSE (0 0 0 1n 1n 10n 20n)


VSourceA1 A1 GND PULSE (0 5 0 1n 1n 10n 20n)
VSourceA2 A2 GND PULSE (0 0 0 1n 1n 10n 20n)
VSourceA3 A3 GND PULSE (0 0 0 1n 1n 10n 20n)

VSourceB0 B0 GND PULSE (0 0 0 1n 1n 15n 30n)


VSourceB1 B1 GND PULSE (0 0 0 1n 1n 15n 30n)
VSourceB2 B2 GND PULSE (0 5 0 1n 1n 15n 30n)
VSourceB3 B3 GND PULSE (0 0 0 1n 1n 15n 30n)

VSourceCin Cin GND PULSE (0 0 0 1n 1n 100n 200n)

.print tran v(B0,GND) v(B1,GND) v(B2,GND) v(B3,GND) v(Cout,GND)


*v(B0,GND) v(B1,GND) v(B2,GND) v(B3,GND) v(Cin,GND) v(S,GND) v(Cout,GND)

* NODE NAME ALIASES


* 9 = VDD (441.5,108)
* 28 = B0 (84,34)
* 29 = A0 (84,52.5)
* 44 = S0 (804,-96)
* 55 = GND (433.5,-324.5)
* 56 = Cin (85,19)
* 59 = B1 (85,-49.5)
* 84 = A3 (84,-219)
* 85 = B2 (85,-189.5)
* 86 = A2 (84.5,-170.5)
* 89 = Cout (776.5,-228)
* 90 = S3 (791,-275.5)
* 116 = B3 (84.5,-238)

M_U1/M1 75 38 VDD 4 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u


* M_U1/M1 DRAIN GATE SOURCE BULK (754 4 756 10)
M_U1/M2 75 10 VDD 4 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/M2 DRAIN GATE SOURCE BULK (725 4 727 10)
M_U1/U1/M4 39 12 VDD 3 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M4 DRAIN GATE SOURCE BULK (724 61.5 726 67.5)
M_U1/U1/M1 39 5 VDD 3 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M1 DRAIN GATE SOURCE BULK (753 61.5 755 67.5)
M_U1/M3 75 38 2 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/M3 DRAIN GATE SOURCE BULK (754 -16 756 -12)
M_U1/M4 2 10 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/M4 DRAIN GATE SOURCE BULK (750 -16 752 -12)
M_U1/U1/M3 1 12 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U1/M3 DRAIN GATE SOURCE BULK (749 40.5 751 44.5)
M_U1/U1/M2 39 5 1 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U1/M2 DRAIN GATE SOURCE BULK (753 40.5 755 44.5)
M_U1/U1/M10 12 10 VDD 15 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M10 DRAIN GATE SOURCE BULK (606 61.5 608 67.5)
M_U1/U1/M6 5 10 VDD 8 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M6 DRAIN GATE SOURCE BULK (647 61.5 649 67.5)
M_U1/U1/M5 5 B1 VDD 8 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M5 DRAIN GATE SOURCE BULK (676 61.5 678 67.5)
M_U1/U1/M12 12 10 7 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U1/M12 DRAIN GATE SOURCE BULK (606 40.5 608 44.5)
M_U1/U1/M8 6 10 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U1/M8 DRAIN GATE SOURCE BULK (672 40.5 674 44.5)
M_U1/U1/M11 7 11 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U1/M11 DRAIN GATE SOURCE BULK (602 40.5 604 44.5)
M_U1/U1/M7 5 B1 6 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U1/M7 DRAIN GATE SOURCE BULK (676 40.5 678 44.5)
M_U1/U1/M9 12 11 VDD 15 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M9 DRAIN GATE SOURCE BULK (577 61.5 579 67.5)
M_U1/U1/M13 10 11 VDD 14 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M13 DRAIN GATE SOURCE BULK (509 61.5 511 67.5)
M_U1/U1/M14 10 B1 VDD 14 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U1/M14 DRAIN GATE SOURCE BULK (538 61.5 540 67.5)
M_U1/U1/M15 13 11 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U1/M15 DRAIN GATE SOURCE BULK (534 40.5 536 44.5)
M_U1/U1/M16 10 B1 13 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U1/M16 DRAIN GATE SOURCE BULK (538 40.5 540 44.5)
M_U2/M1 45 58 VDD 21 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/M1 DRAIN GATE SOURCE BULK (419 4 421 10)
M_U2/M2 45 20 VDD 21 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/M2 DRAIN GATE SOURCE BULK (390 4 392 10)
M_U2/U1/M1 57 19 VDD 22 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M1 DRAIN GATE SOURCE BULK (418 61.5 420 67.5)
M_U2/U1/M4 57 18 VDD 22 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M4 DRAIN GATE SOURCE BULK (389 61.5 391 67.5)
M_U2/M3 45 58 17 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/M3 DRAIN GATE SOURCE BULK (419 -16 421 -12)
M_U2/M4 17 20 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/M4 DRAIN GATE SOURCE BULK (415 -16 417 -12)
M_U2/U1/M2 57 19 16 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U1/M2 DRAIN GATE SOURCE BULK (418 40.5 420 44.5)
M_U2/U1/M3 16 18 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U1/M3 DRAIN GATE SOURCE BULK (414 40.5 416 44.5)
M_U2/U1/M6 19 20 VDD 24 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M6 DRAIN GATE SOURCE BULK (312 61.5 314 67.5)
M_U2/U1/M5 19 B0 VDD 24 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M5 DRAIN GATE SOURCE BULK (341 61.5 343 67.5)
M_U2/U1/M8 23 20 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U1/M8 DRAIN GATE SOURCE BULK (337 40.5 339 44.5)
M_U2/U1/M7 19 B0 23 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U1/M7 DRAIN GATE SOURCE BULK (341 40.5 343 44.5)
M_U2/U1/M9 18 A0 VDD 27 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M9 DRAIN GATE SOURCE BULK (242 61.5 244 67.5)
M_U2/U1/M10 18 20 VDD 27 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M10 DRAIN GATE SOURCE BULK (271 61.5 273 67.5)
M_U2/U1/M14 20 B0 VDD 30 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M14 DRAIN GATE SOURCE BULK (203 61.5 205 67.5)
M_U2/U1/M11 26 A0 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U1/M11 DRAIN GATE SOURCE BULK (267 40.5 269 44.5)
M_U2/U1/M12 18 20 26 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U1/M12 DRAIN GATE SOURCE BULK (271 40.5 273 44.5)
M_U2/U1/M16 20 B0 25 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U1/M16 DRAIN GATE SOURCE BULK (203 40.5 205 44.5)
M_U2/U1/M15 25 A0 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U1/M15 DRAIN GATE SOURCE BULK (199 40.5 201 44.5)
M_U2/U1/M13 20 A0 VDD 30 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U1/M13 DRAIN GATE SOURCE BULK (174 61.5 176 67.5)
M_U1/U0/M4 31 40 VDD 33 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M4 DRAIN GATE SOURCE BULK (724 -43 726 -37)
M_U1/U0/M1 31 34 VDD 33 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M1 DRAIN GATE SOURCE BULK (753 -43 755 -37)
M_U1/U0/M3 32 40 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U0/M3 DRAIN GATE SOURCE BULK (749 -64 751 -60)
M_U1/U0/M2 31 34 32 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U0/M2 DRAIN GATE SOURCE BULK (753 -64 755 -60)
M_U1/U0/M10 40 38 VDD 43 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M10 DRAIN GATE SOURCE BULK (606 -43 608 -37)
M_U1/U0/M6 34 38 VDD 37 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M6 DRAIN GATE SOURCE BULK (647 -43 649 -37)
M_U1/U0/M5 34 45 VDD 37 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M5 DRAIN GATE SOURCE BULK (676 -43 678 -37)
M_U1/U0/M12 40 38 36 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U0/M12 DRAIN GATE SOURCE BULK (606 -64 608 -60)
M_U1/U0/M8 35 38 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U0/M8 DRAIN GATE SOURCE BULK (672 -64 674 -60)
M_U1/U0/M11 36 39 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U0/M11 DRAIN GATE SOURCE BULK (602 -64 604 -60)
M_U1/U0/M7 34 45 35 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U0/M7 DRAIN GATE SOURCE BULK (676 -64 678 -60)
M_U1/U0/M9 40 39 VDD 43 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M9 DRAIN GATE SOURCE BULK (577 -43 579 -37)
M_U1/U0/M13 38 39 VDD 42 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M13 DRAIN GATE SOURCE BULK (509 -43 511 -37)
M_U1/U0/M14 38 45 VDD 42 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U1/U0/M14 DRAIN GATE SOURCE BULK (538 -43 540 -37)
M_U1/U0/M15 41 39 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U1/U0/M15 DRAIN GATE SOURCE BULK (534 -64 536 -60)
M_U1/U0/M16 38 45 41 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U1/U0/M16 DRAIN GATE SOURCE BULK (538 -64 540 -60)
M_U2/U0/M1 S0 48 VDD 49 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U0/M1 DRAIN GATE SOURCE BULK (418 -43 420 -37)
M_U2/U0/M4 S0 47 VDD 49 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* M_U2/U0/M4 DRAIN GATE SOURCE BULK (389 -43 391 -37)
M_U2/U0/M2 S0 48 46 120 NMOS L=700n W=1.4u AD=4.9p PD=9.1u AS=490f PS=2.1u
* M_U2/U0/M2 DRAIN GATE SOURCE BULK (418 -64 420 -60)
M_U2/U0/M3 46 47 GND 120 NMOS L=700n W=1.4u AD=490f PD=2.1u AS=7.84p PS=11.9u
* M_U2/U0/M3 DRAIN GATE SOURCE BULK (414 -64 416 -60)
M_U2/U0/M6 48 58 VDD 51 PMOS L=700n W=2.1u AD=5.145p PD=9.1u AS=9.555p PS=13.3u
* Circuit Extracted by Tanner Research's L-Edit V8.11 / Extract V8.11 ;
* TDB File: D:\Donem_4_2\VLSI\adder\nand.tdb
* Cell: Cell0 Version 1.61
* Extract Definition File: C:\Program Files\Tanner EDA\L-Edit Pro\tech\mosis\
mhp_n05.ext
* Extract Date and Time: 05/29/2011 - 09:59

* Warning: Layers with Unassigned AREA Capacitance.


* <Poly Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* Warning: Layers with Unassigned FRINGE Capacitance.
* <Pad Comment>
* <Poly Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* Warning: Layers with Zero Resistance.
* <Pad Comment>
* <cap using Cap-Well>
* <NMOS Capacitor>
* <PMOS Capacitor>

.tran/op 1n 200n method=bdf


.include "C:\Program Files\Tanner EDA\T-Spice Pro v6.02\models\hp05.md"
.lib "C:\Program Files\Tanner EDA\L-Edit Pro\tech\mosis\morbn20.ext"

VPOWER_SUPPLY VDD GND 5

VSourceA0 A0 GND PULSE (0 0 0 1n 1n 10n 20n)


VSourceA1 A1 GND PULSE (0 5 0 1n 1n 10n 20n)
VSourceA2 A2 GND PULSE (0 0 0 1n 1n 10n 20n)
VSourceA3 A3 GND PULSE (0 0 0 1n 1n 10n 20n)

VSourceB0 B0 GND PULSE (0 0 0 1n 1n 15n 30n)


VSourceB1 B1 GND PULSE (0 0 0 1n 1n 15n 30n)
VSourceB2 B2 GND PULSE (0 5 0 1n 1n 15n 30n)
VSourceB3 B3 GND PULSE (0 0 0 1n 1n 15n 30n)

VSourceCin Cin GND PULSE (0 0 0 1n 1n 100n 200n)

.print tran v(B0,GND) v(B1,GND) v(B2,GND) v(B3,GND) v(Cout,GND)


*v(B0,GND) v(B1,GND) v(B2,GND) v(B3,GND) v(Cin,GND) v(S,GND) v(Cout,GND)

* NODE NAME ALIASES


* 9 = VDD (441.5,108)
* 28 = B0 (84,34)
* 29 = A0 (84,52.5)
* 44 = S0 (804,-96)
* 55 = GND (433.5,-324.5)
* 56 = Cin (85,19)
* 59 = B1 (85,-49.5)
* 84 = A3 (84,-219)
* 85 = B2 (85,-189.5)
* 86 = A2 (84.5,-170.5)
*

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