1. a) Realize the following Boolean expression using dataflow modeling.
(i)Y=A+B (ii) Y=AB [CO1]
b) Design CMOS NAND gate and verify Transient analysis. [CO4]
2. a) Write a HDL code to simulate D-Flipflop .[CO3]
b) Design and verify Transient analysis of CMOS Inverter.CO4]
3. a) Write a HDL code to simulate 4X1 MUX.[CO2]
b) Design CMOS NOR gate and verify using Cadence Virtuoso Tool. [CO4]
4. Design CMOS NAND and NOR gates and Verify Transient analysis. [CO4]
5. a) Verify CMOS NOR gate Transient Analysis. [CO4]
b) Write HDL Code for 1-bit Adder using decoder. [CO2]
6. a) Verify CMOS NOR gate Transient Analysis.[CO4]
b) Write HDL Code for 1-bit Subtractor using decoder. [CO2]
7. Design parity generator using MUX and verify using Xilinx Tool.[CO2]
8. a) Write a HDL code to simulate and verify 4-bit comparator using 1-bit Comparator.
[CO2]
9. a) Write a HDL code to verify JK FLIP FLOP using xilinx tool. [CO3]
b) Design and verify CMOS NAND gate using cadence virtuoso. [CO4]
10. a) Design and verify 2-input AND gate using Cadence Virtuoso Tool.[CO4]
b) Write a HDL code to simulate 4-bit Binary counter. .[CO3]
11. a) Write a HDL code to simulate T flip-flop. .[CO3]
b) Design CMOS Inverter and verify transient analysis using cadence virtuoso tool. [CO4]
12. Design Asynchronous counter using T flipflop.[CO3]
13. Design 1-bit Comparator and perform Transient Analysis using Cadence Virtuoso
Tool. [CO5]
14. Design parity checker using mux and verify using Xilinx Tool. [CO2]
15. a) Design of 2-bit ALU (Adder, Subrtactor, Multiplication, greaterthan). [CO2]
b) Design and verify CMOS AND gate using cadence virtuoso. [CO4]
16. Design parity Checker using MUX and verify using Xilinx Tool.[CO2]
17. Design Mealy FSM based sequence detector and verify using XilinxTool [CO3]
