1 月 8 日_筆試期末測驗
時間: 9:10---10:00
可帶任何書面資料,不能使用手機與
電腦等有網路環境之設備
Ans:
以下的 code 請考試時自己準備
module
sap1(T,clk,clr,q,LDA,ADD,SUB,OUT,OpCode,Con,w_bus,pc_Out,marOut,data1,Operan
d_temp,AccOut,Bout,AddOut);
parameter size='d6;
output [size-1:0]T;
output [size-4:0]q;
output LDA,ADD,SUB,OUT;
output [11:0]Con;
output [7:0]w_bus;
output [3:0]pc_Out;
output [3:0]marOut;
output [7:0]data1,AccOut,Bout,AddOut;
output [size-3:0]OpCode;
output [3:0]Operand_temp;
input clk,clr;
//input [size-3:0]OpCode;
reg [size-3:0]OpCode;
reg [size-1:0]T;
reg [size-4:0]q;
reg [11:0]Con;
reg LDA,ADD,SUB,OUT;
reg [3:0]pc_Out;
reg [3:0]marOut;
reg [7:0]data1,AccOut,Bout;
reg [3:0]Operand_temp;
// to acc
assign w_bus=Con[10]?{4'bz,pc_Out}:(Con[8]? (Con[6] ? (Con[4] ? AccOut:(Con[2] ?
AddOut:8'bz)) : {4'bz,Operand_temp}) : data1);
assign AddOut=Con[3]? AccOut-Bout:AccOut+Bout;
// add B
always @(posedge clk)
begin
if(clr==0) Bout=8'd0;
else if (Con[1]==0) Bout=w_bus;
else Bout=Bout;
end
// add acc
always @(posedge clk)
begin
if(clr==0) AccOut=8'd0;
else
if(Con[5]==0) AccOut=w_bus;
else AccOut=AccOut;
end
// assign AccOutB=Ea?AccOutA:8'bz;
// add IR 0414,
always @(posedge clk or negedge clr)
begin
if(clr==0) OpCode=4'd0;
else if(Con[7]==0) OpCode=w_bus[7:4];
else OpCode=OpCode;
end
always @(posedge clk)
begin
if(Con[7]==0) Operand_temp=w_bus[3:0];
end
// assign Operand=Ei ? 4'bz : Operand_temp;
// add rom
always @(marOut) begin
case ( marOut )
4'd0 : data1 = 8'h07 ;
4'd1 : data1 = 8'h28 ;
4'd2 : data1 = 8'h1b ;
4'd3 : data1 = 8'h2c ;
4'd4 : data1 = 8'he0 ;
4'd5 : data1 = 8'hf0 ;
4'd6 : data1 = 8'hf0 ;
4'd7 : data1 = 8'h99 ;
4'd8 : data1 = 8'h22 ;
4'd9 : data1 = 8'h10 ;
4'd10 : data1 = 8'h14 ;
4'd11 : data1 = 8'h18 ;
4'd12 : data1 = 8'h20 ;
4'd13 : data1 = 8'h00 ;
4'd14 : data1 = 8'h00 ;
4'd15 : data1 = 8'h00 ;
default : data1 = 8'h00 ;
endcase
end
// assign data = Con[8]? 8'hz : data1;
//assign Operand=Ei ? 4'bz : Operand_temp;
//assign w_bus=Con[10]?{4'bz,pc_Out}:(Con[8]? 8'hz : data1);
// assign w_bus=Con[10]?{4'bz,pc_Out}:(Con[8]? (Con[6] ? 8'bz :
{4'bz,Operand_temp}) : data1);//to IR
// mar:save memory address register,
always @(posedge clk)
begin
if(clr==0) marOut=4'd0;
else
if(Con[9]==0) marOut=w_bus[3:0];
else marOut=marOut;
end
// pc:program counter_generate rom address
always @(negedge clk or negedge clr)
begin
if(clr==0) pc_Out=4'd0;
else if(Con[11]==1) pc_Out=pc_Out+4'd1;//cp==1,pc +1,
else pc_Out=pc_Out;
end
// ?
// assign w_bus=Con[10]?{4'bz,pc_Out}:8'bz;
// ring counter
always @(negedge clk or negedge clr)
begin
if(clr==0) q=0;
else q=(q+1)%6;
end
always @(q)
case (q)
3'd0: T=6'b000001;
3'd1: T=6'b000010;
3'd2: T=6'b000100;
3'd3: T=6'b001000;
3'd4: T=6'b010000;
3'd5: T=6'b100000;
default: T=6'b000000;
endcase
// I decoder
always @(OpCode)
case (OpCode)
4'd0: begin LDA=1;ADD=0;SUB=0;OUT=0;end
4'd1: begin LDA=0;ADD=1;SUB=0;OUT=0;end
4'd2: begin LDA=0;ADD=0;SUB=1;OUT=0;end
4'd14:begin LDA=0;ADD=0;SUB=0;OUT=1;end
default:begin LDA=0;ADD=0;SUB=0;OUT=0;end
endcase
// Control_Array
always @(T or LDA or ADD or SUB or OUT)
begin
Con[11]=T[1];
Con[10]=T[0];
Con[9]=~((LDA&T[3])|(ADD&T[3])|(SUB&T[3])|T[0]);
Con[8]=~(T[2]|(LDA&T[4])|(ADD&T[4])|(SUB&T[4]));
Con[7]=~T[2];
Con[6]=~((LDA&T[3])|(ADD&T[3])|(SUB&T[3]));
Con[5]=~((LDA&T[4])|(ADD&T[5])|(SUB&T[5]));
Con[4]=T[3]&OUT;
Con[3]=SUB&T[5];
Con[2]=((ADD&T[5])|(SUB&T[5]));
Con[1]=~((ADD&T[4])|(SUB&T[4]));
Con[0]=~(OUT&T[3]);
end
endmodule
