CT 211: COMPUTER ARCHITECTURE AND ORGANIZATION I
TUTORIAL#03
Computer Memory System
1. Explain the differences between SRAM and DRAM in terms of structure, speed, and cost.
2. What are the advantages of using DRAM for main memory?
3. Name three different applications where ROMs are often used.
4. Describe the concept of a memory hierarchy and its purpose in computer architecture.
5. Explain the concept of locality of reference, and state its importance to memory systems.
6. What are the three forms of locality?
7. Which of L1 or L2 cache is faster? Which is smaller? Why is it smaller?
8. Cache is accessed by its ________, whereas main memory is accessed by its _______.
9. What are the three fields in a direct mapped cache address? How are they used to access a
word located in cache?
10. Explain how fully associative cache is different from direct mapped cache.
11. Explain how set associative cache combines the ideas of direct and fully associative
cache.
12. What are the three fields in a set associative cache address, and how are they used to
access a location in cache?
13. Explain the four cache replacement policies.
14. Why is the optimal cache replacement policy important?
15. What is the worst-case cache behavior that can develop using LRU and FIFO cache
replacement policies?
16. What is effective access time (EAT)?
17. What is a dirty block?
18. Explain the difference between a unified cache and a Harvard cache.
19. What are the advantages of a Harvard cache?
20. Why would a system contain a victim cache? A trace cache?
21. What are the advantages of using a multi-level cache system?
22. Explain the differences among L1, L2, and L3 cache.
23. Explain the differences between inclusive and exclusive cache.
24. What is the advantage to a non-blocking cache?
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25. Explain the principles of virtual memory and its implementation using paging and
segmentation.
26. What is the objective of paging?
27. Discuss the pros and cons of paging.
28. What is a page fault?
29. What causes internal fragmentation?
30. What are the components (fields) of a virtual address?
31. What is a TLB, and how does it improve EAT?
32. What are the advantages and disadvantages of virtual memory?
33. When would a system ever need to page its page table?
34. What causes external fragmentation, and how can it be fixed?
35. Explain the role of page tables in virtual memory systems.
36. Explain the concept of write-through and write-back policies in caching.
37. A CPU accesses memory 10,000 times, with 8,000 hits in the cache. Calculate the cache
hit rate and miss rate.
38. A system has a cache access time of 5 ns and a main memory access time of 50 ns. If the
cache hit rate is 90%, calculate the average memory access time.
39. For a system with a hit rate of 95%, cache access time of 2 ns, and main memory access
time of 100 ns:
a. Calculate the average memory access time.
b. Determine the impact on access time if the hit rate drops to 85%.
40. A 16 KB cache uses a direct-mapping technique. The main memory size is 256 KB, and
the block size is 64 bytes. Calculate:
a) The number of cache blocks.
b) The number of blocks in the main memory.
c) The number of blocks that map to a single cache block.
41. If the hit ratio is 92% and the miss penalty is 100 cycles, while the cache access time is 2
cycles, calculate the effective memory access time.
42. Suppose a computer using direct mapped cache has 220 bytes of byte-addressable main
memory and a cache of 32 blocks, where each cache block contains 16 bytes.
a) How many blocks of main memory are there?
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b) What is the format of a memory address as seen by the cache; that is, what are the
sizes of the tag, block, and offset fields?
43. Suppose a computer using fully associative cache has 216 bytes of byte-addressable main
memory and a cache of 64 blocks, where each cache block contains 32 bytes.
a) How many blocks of main memory are there?
b) What is the format of a memory address as seen by the cache; that is, what are the
sizes of the tag and offset fields?
44. Suppose a byte-addressable computer using set associative cache has 2 21 bytes of main
memory and a cache of 64 blocks, where each cache block contains 4 bytes.
a) If this cache is 2-way set associative, what is the format of a memory address as seen
by the cache; that is, what are the sizes of the tag, set, and offset fields?
b) If this cache is 4-way set associative, what is the format of a memory address as seen
by the cache?
45. Compare the bits required for the tag, index, and block offset for the following
configurations with a main memory of 4 GB and a block size of 32 bytes:
a) Direct-mapped cache with 1 MB size.
b) 4-way set-associative cache with 512 sets.
c) Fully associative cache with 32 KB size.
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