US008181 140B2

(12) United States Patent (10) Patent No.: US 8,181,140 B2

Kireev et al. (45) Date of Patent: May 15, 2012

(54) T-COIL NETWORK DESIGN FOR IMPROVED Musolino et al., "Pulse Forming Network Optimal Design for the
BANDWIDTH AND ELECTROSTATIC Power Supply of Em! Lauchners", IEEE Transactions on Magnetics,
DISCHARGE IMMUNITY vol. 33, No. 1, Jan. 1997, pp. 480-483.*
Neuber et al., "A Compact, Repetitive, 500KV, 500 J, Marx Genera-
(75) Inventors: Vassili Kireev, Sunnyvale, CA (US); tor", IEEE, 2005, pp. 1203-1206.*
James Karp, Saratoga, CA (US); Toan Selmi, L. etal., "Small-Signal MMICAmplifiers with BridgedT-Coil
D. Tran, San Jose, CA (US) Matching Networks", IEEE Journal of Solid-State Circuits, vol. 27,
No. 7, Jul. 1, 1992, pp. 1093-1096.
(73) Assignee: Xilinx, Inc., San Jose, CA (US) Huang, Bo-Jr., et al., "Design and Analysis for a 60-GHz Low-Noise
Amplifier with RF ESD Protection", IEEE Transactions on Micro-
(*) Notice: Subject to any disclaimer, the term of this wave Theory and Techniques, vol. 57, No. 2, Feb. 1, 2009, pp.
patent is extended or adjusted under 35 299-300.
U.S.C. 154(b) by 260 days. Galali et al., Broadband ESD Protection Circuits in CMOS Technol-
ogy, IEEE Journal of Solid State Circuits, vol. 38, No. 12, Dec. 2003,
(21) Appl. No.: 12/615,173 pp. 2334-2340.
Pillai etal., "Novel T-Coil Structure and Implementation in a 6.4-gb/s
(22) Filed: Nov. 9, 2009 CMOS Receiver to Meet Return Loss Specifications", 2007 Elec-
tronic Components and Technology Conference, IBM, 2007, pp.
(65) Prior Publication Data 147-153.
US 201 1/01 13401 Al May 12, 2011 * cited by examiner

(51) Int. Cl. Primary Examiner Phallaka Kik

G06F 17/50 (2006.01) (74) Attorney, Agent, or Firm Kevin T. Cuenot; Thomas
(52) U.S. Cl. ........ 716/122; 716/123; 716/129; 716/130; George
716/132
(58) Field of Classification Search .................. 716/122, (57) ABSTRACT
716/123, 129, 130, 132; 326/38, 101
A method of generating a circuit design comprising a T-coil
See application file for complete search history. network includes determining inductance for inductors and a
parasitic bridge capacitance of the T-coil network. The para-
(56) References Cited
sitic bridge capacitance is compared with a load capacitance
U.S. PATENT DOCUMENTS metric that depends upon parasitic capacitance of a load
coupled to an output of the T-coil network. An amount of
3,155,927 A 11/1964 True electrostatic discharge (ESD) protection of the circuit design
5,546,048 A * 8/1996 Sano et al . .................... 330/263
2003/0102923 Al * 6/2003 Vickram et al . .............. 330/298 that is coupled to the output of the T-coil network and/or a
2005/0172246 Al * 8/2005 Logic et al . ....................... 716/4 parameter of the inductors of the T-coil network is selectively
2 009/003 99 16 Al * 2/2009 Buchmann et al . ............. 326/38 adjusted according to the comparison. The circuit design,
OTHER PUBLICATIONS which can specify inductance of the inductors, the amount of
ESD protection, and/or the width of windings of the induc-
Chen et al., "Design and Optimization of a Compact, Repetitive, tors, is outputted.
High-Power Microwave System", Review of Scientific Instruments,
vol. 76, No. 10, Oct. 2005, abstract only.* 20 Claims, 3 Drawing Sheets

W12e u
su ue(a~NL mr

~I9c increnseG

paciy'ng p~yakal yro

U.S. Patent May 15, 2012 Sheet 1 of 3 US 8,181,140 B2

100

130
135

System Bus
115

Processor I I I Local Memory

105 120
Bulk Storage
Device
Memory Elements 125
110

Circuit
Design Circuit Design
Module 145
140

FIG. 1
U.S. Patent May 15, 2012 Sheet 2 of 3 US 8,181,140 B2

200

1-coil
Input
Node T-coil
235 Network ESD
225 T-coil 215
Input Output
Pad Node
L 240
210
250 Input/
AAA Output
Device
CPD
275 L
C. 255 I
265 CL
ESD
245

- I CTM
270
298

RTM
260
I 220

I I
I I
I I
I I
I I
I I
I = I
I — I
I

FIG. 2
U.S. Patent May 15, 2012 Sheet 3 of 3 US 8,181,140 B2

300

Determine values for CTM, CPD,

and CL
305
Is Yes
CL/12 equal to CB?
Estimate initial value(s) of L for 355
T-coil network No
310
Increase ESD element to
increase CL
Generate circuit design 360
specifying physical layout of T-
coil network using initial
value(s) of L Output resulting circuit design
315 365

Determine initial value of CB,,

denoted as CB11 Done
320

Determine initial value of CB,

denoted as CB1
325

Calculate target value(s) of L

for T-coil network
330

Determine updated value of

CB,, denoted as CB12
335

Determine updated value of CB,

denoted as CB2
340

Is
CB less than CL/12?
345 No
FIG. 3
Yes

Adjust inductor parameter(s) to

increase CB
350
 US 8,181,140 B2
1
T-COIL NETWORK DESIGN FOR IMPROVED which can specify inductance of the inductors, the amount of
BANDWIDTH AND ELECTROSTATIC ESD protection, and/or the width of windings of the induc-
DISCHARGE IMMUNITY tors, is outputted.
Another embodiment of the present invention includes a
FIELD OF THE INVENTION 5 system for generating a circuit design comprising a T-coil
network. The system includes a memory storing program
One or more embodiments disclosed within this specifica- code and a processor coupled to the memory that, upon
tion relate to integrated circuit devices (ICs). More particu- executing the program code, is configured to perform a plu-
larly, one or more embodiments relate to designing a circuit rality of steps. The steps include: determining inductance for
comprising a T-coil network for use with high frequency 10 inductors, and a parasitic bridge capacitance of the T-coil
inputs or outputs of an IC. network, and comparing the parasitic bridge capacitance with
a load capacitance metric that depends upon parasitic capaci-
BACKGROUND tance of a load coupled to an output of the T-coil network. The
processor further can be configured to selectively adjust an
The frequency of input or output (referred to as "input/ 15 amount of ESD protection ofthe circuit design that is coupled
output" hereinafter) signals provided to integrated circuit to the output of the T-coil network or a parameter of the
devices (ICs) has steadily increased over time. As the fre- inductors of the T-coil network according to the comparing of
quency of input/output signals reaches radio frequency (RF) parasitic bridge capacitance with the load capacitance metric.
ranges and approach the gigahertz range, complex imped- The processor outputs the circuit design. The circuit design
ances at the input/output node often result. The complex can specify inductance of the inductors, the amount of ESD
impedance of an IC input/output node can create impedance 20 protection, and the width of windings of the inductors.
matching issues between the source of the input/output signal Another embodiment of the present invention includes a
and the input/output node of the IC. Impedance mismatches device that includes a data storage medium usable by a system
can degrade performance of the input/output node, if not the comprising a processor and a memory. The data storage
IC in general. medium stores program code that, when executed by the
Complex impedances are a function of multiple small 25 system, causes the system to perform executable operations.
capacitances and inductances associated with devices The executable operations include determining inductance
coupled to the input/output node of the IC. These small for inductors and a parasitic bridge capacitance of the T-coil
capacitance and inductances can include gate capacitances, network, and also include comparing the parasitic bridge
inductances and capacitances associated with interconnect capacitance with a load capacitance metric that depends upon
lines, packaging bond wire inductances, capacitance associ- 30 parasitic capacitance of a load coupled to an output of the
ated with input/output pads, capacitances associated with T-coil network. The executable operations further include
electrostatic discharge structures, and the like. selectively adjusting an amount of ESD protection of the
An impedance mismatch between a source of an input/ circuit design that is coupled to the output of the T-coil net-
output signal and an input/output node of an IC results in work or a parameter of the inductors of the T-coil network
inefficient delivery of signal power to the input/output node 35
according to the comparing of parasitic bridge capacitance
since a percentage of the power of the input/output signal is with the load capacitance metric. In addition, the executable
reflected back from the input/output node to the source of the operations further include outputting the circuit design. The
input/output signal. In addition, an impedance mismatch circuit design includes inductance of the inductors, the
leads to a reduction in bandwidth of the input/output node amount of ESD protection, and the width of windings of the
since the small inductances and capacitances become more inductors.
40
significant at higher frequencies.
To avoid signal power loss, RF systems strive to create a BRIEF DESCRIPTION OF THE DRAWINGS
purely resistive impedance at each RF input/output and RF
output. To offset complex impedances at IC input/output FIG. 1 is a block diagram illustrating a system for design-
nodes, matching networks can be implemented at input/out- ing a T-coil network for implementation within an integrated
put nodes of the IC that seek to cancel the complex imped- 45 circuit device (IC) in accordance with one embodiment of the
ances. Without matching networks, many IC input/outputs present invention.
would be band limited with maximum operating frequencies FIG. 2 is a circuit diagram illustrating an exemplary circuit
well below the frequency range of a desired input/output comprising a T-coil network in accordance with another
signal. embodiment of the present invention.
50 FIG. 3 is a flow chart illustrating a method of designing a
SUMMARY T-coil network for ICs in accordance with another embodi-
ment of the present invention.
One or more embodiments disclosed within this specifica-
tion relate to integrated circuit devices (ICs) and, more par- DETAILED DESCRIPTION OF THE DRAWINGS
ticularly, to designing a circuit comprising a T-coil network 55
for use with high frequency input/outputs of an IC. One While the specification concludes with claims defining the
embodiment of the present invention includes a method of features of one or more embodiments of the invention that are
generating a circuit design comprising a T-coil network using regarded as novel, it is believed that the embodiments of the
a system comprising a processor and a memory. The method invention will be better understood from a consideration of
includes determining inductance for inductors and a parasitic the description in conjunction with the drawings. As required,
bridge capacitance of the T-coil network, and also comparing 60 detailed embodiments of the present invention are disclosed
the parasitic bridge capacitance with a load capacitance met- herein; however, it is to be understood that the disclosed
ric that depends upon parasitic capacitance of a load coupled embodiments are merely exemplary of the inventive arrange-
to an output of the T-coil network. An amount of electrostatic ments, which can be embodied in various other forms. There-
discharge (ESD) protection of the circuit design that is fore, specific structural and functional details disclosed
coupled to the output of the T-coil network and/or a parameter 65 herein are not to be interpreted as limiting, but merely as a
of the inductors of the T-coil network can be selectively basis for the claims and as a representative basis for teaching
adjusted according to the comparison. The circuit design, one skilled in the art to variously employ the inventive
 US 8,181,140 B2
3
arrangements in virtually any appropriately detailed struc- coupled to the T-coil network at the coupling point between
ture. Further, the terms and phrases used herein are not the two inductors. The T-coil network can reduce or cancel the
intended to be limiting but rather to provide an understand- complex impedances associated with a capacitive load at the
able description of one or more embodiments of the inven- IC input/output. The implementation of a T-coil network at an
tion. 5 input/output node of an IC can increase the bandwidth of that
One or more embodiments disclosed within this specifica- input/output node. This improvement results in better RF
tion relate to semiconductor integrated circuit devices (ICs). system performance of the input/output node by, for example,
More particularly, one or more embodiments relate to design- reducing return loss, decreasing bit error rates, or increasing
ing a T-coil network for use with an input/output node of an power gain.
IC. In accordance with the inventive arrangements disclosed io Using the design specification and extracted component
within this specification, a T-coil network design technique is values, circuit design module 140 can determine a first esti-
provided that accounts for capacitances overlooked by con- mated value for a total bridge capacitance across two induc-
ventional design techniques. One or more embodiments fur- tors, denoted as CB, within the T-coil network. Circuit design
ther balance different capacitive quantities by modifying module 140 can calculate a value for each of the two induc-
aspects of the T-coil design by adding more electrostatic 15 tors, denoted as L1 and L2, within the T-coil network using the
discharge (ESD) elements and/or modifying parameters of greater of the first value of CB or a load capacitance metric
the inductors of the T-coil network such as a width of the coils seen at the output node of the T-coil network, denoted as
of the inductors of the T-coil network. Both approaches not CL/12. Circuit design module 140 can determine a second
only help to maximize bandwidth of the T-coil network and value of CB using an inter-winding capacitance derived using
minimize distortions, but also serve to increase ESD protec- the values of L, and L2 .
tion provided to the input/output node of the IC. Circuit design module 140 can compare the value of CB to
FIG. 1 is a block diagram illustrating a system 100 for a metric that depends upon the value of CL, e.g., a load
designing a T-coil network for implementation within an IC in capacitance metric, and increase either the value for CB or the
accordance with one embodiment of the present invention. In value of CL until the two values are equal or approximately
one aspect, system 100 can generate one or more T-coil net- equal, e.g., within a predetermined range or tolerance of one
work designs for instantiation within an IC. 25 another. CB can be increased, for example, by increasing the
As pictured in FIG. 1, system 100 can include at least one inter-winding capacitance of L, and L2. CL can be increased,
processor 105 coupled to memory elements 110 through a for example, by increasing an amount of ESD protection
system bus 115. As such, system 100 can store program code applied to the output node of the T-coil network.
within memory elements 110. Processor 105 can execute the The resulting parameters such as values for CB, CL, L1, and
program code accessed from memory elements 110 via sys- 30 L2, the amount of ESD protection used, and other parameters
tem bus 115. In one aspect, for example, system 100 can be relating to the inductors L1, and L2, e.g., width of windings of
implemented as computer that is suitable for storing and/or the inductors, can be output as, or included within, circuit
executing program code. It should be appreciated, however, design 145 and stored within memory elements 110. As used
that system 100 can be implemented in the form of any system herein, "outputting" and/or "output" can mean storing in
comprising a processor and memory that is capable of per- 35 memory elements 110, for example, writing to a file stored in
forming the functions described within this specification. memory elements 110, writing to display 135 or other periph-
Memory elements 110 can include one or more physical eral output device, playing audible notifications, sending or
memory devices such as, for example, local memory 120 and transmitting to another system, exporting, or the like.
one or more bulk storage devices 125. Local memory 120 FIG. 2 is a circuit diagram illustrating an exemplary circuit
refers to random access memory or other non-persistent 200 comprising a T-coil network in accordance with another
memory device(s) generally used during actual execution of 40 embodiment of the present invention. Circuit 200 illustrates
the program code. Bulk storage device(s) 125 can be imple- an input/output node of an IC. As shown, a T-coil network has
mented as a hard drive or other persistent data storage device. been implemented to improve matching of the impedance of
System 100 also can include one or more cache memories the input/output node of the IC with the impedance of an
(not shown) that provide temporary storage of at least some output of a source providing an input/output signal to the
program code in order to reduce the number of times program 45 input/output of the IC. Circuit 200 can include an input/output
code must be retrieved from bulk storage device 125 during device 205, an input/output pad 210, ESD devices 215 and
execution. 220, and T-coil network 225.
Input/output (I/O) devices such as a keyboard 130, a dis- Input/output device 205 can be any input/output device
play 135, and a pointing device (not shown) optionally can be within an IC that is configured to receive an external high
coupled to system 100. The I/O devices can be coupled to 50 frequency signal as an input/output. Input/output device 205
system 100 either directly or through intervening I/O control- can be coupled to additional input/output circuitry within the
lers. Network adapters also can be coupled to system 100 to IC. Additional input/output circuitry represents additional
enable system 100 to become coupled to other systems, com- devices or circuitry that can be coupled to input/output device
puter systems, remote printers, and/or remote storage devices 205 for processing the input/output signal received via input/
through intervening private or public networks. Modems, 55 output pad 210.
cable modems, and Ethernet cards are examples of different An input/output signal is provided to input/output pad 210.
types of network adapters that can be used with system 100. The input/output signal can be a radio frequency (RF) input/
Memory elements 110 can store a circuit design module output signal, e.g., a high speed digital signal. Input/output
140. Circuit design module 140, being implemented in the pad 210 can be any pad structure available within an IC
form of executable program code, can be executed by system manufacturing process that allows a signal external to the IC
100. Circuit design module 140 can receive a design specifi- 60 to be provided to the internal circuitry of the IC. Input/output
cation for a circuit that comprises a T-coil network. Circuit pad 210 is coupled to T-coil network 225 at T-coil input/
design module 140 further can determine and/or obtain, e.g., output node (input/output node) 235. Input/output pad 210
read, extracted component values for one or more compo- can be part of a signal path coupling the input/output signal to
nents or aspects of a circuit design and/or the T-coil network input/output device 205.
included within such a circuit design, that are stored within 65 ESD devices 215 and 220 are coupled to a T-coil output
memory elements 110. A T-coil network generally includes node (output node) 240. Output node 240 provides signal to
two inductors coupled in series with an input/output load input/output device 205. In FIG. 2, ESD devices 215 and 220
 US 8,181,140 B2

are implemented as ESD diodes. It should be appreciated, When implemented at an input/output node, T-coil net-
however, that ESD devices 215 and 220 can be any device work 225 can cancel the complex impedances associated with
within an IC manufacturing process capable of providing input/output device 205 and present a predominantly resistive
protection from ESD events to input/output device 205. For impedance to a source, which generates a high frequency
example, the ESD devices 215 and 220 can be diodes, how- 5 input/output signal to drive input/output device 205. Typi-
ever, ESD devices 215 and 220 are not limited to just diodes. cally, input and output nodes of an RF system are designed to
T-coil network 225 can include two inductors, denoted as L have a matched characteristic impedance of 50 ohms.
250 and L 255, and a termination resistor, denoted a RTM 260. Accordingly, the resistance of the source (Rsou,,C,) and RTM
T-coil network 225 can include a plurality of parasitic capaci- 260 each can be implemented with characteristic impedances
tances. The parasitic capacitances, though not actual circuit io of approximately 50 ohms. T-coil network 225, when prop-
elements, are represented in FIG. 2 as CL 245, CBI 265, CTM erly implemented, can have the effect of cancelling complex
270, and CPD 275. impedances seen by the output of the source which generates
CL 245 represents a sum of the parasitic capacitances the input/output signal so that the input/output node of the IC
appearing at output node 240 and, thus, the input/output node is seen by this source as purely resistive with the resistance of
of input/output device 205. Accordingly, CL 245 represents 15 the source (Rsou,,C,) being approximately equal to RTM 260.
the load capacitance seen by T-coil network 225. CL 245 can Conventional T-coil network design techniques evaluate
include a variety of parasitic capacitances associated with CBI to determine whether CBI is less than required by cancel-
devices coupled to output node 240. For example, CL 245 can lation equations and, based upon that evaluation, add a physi-
include gate capacitances associated with input/output device cal capacitor CBL to meet the requirements for cancellation.
205, capacitance associated with interconnect lines coupling More particularly, based upon the evaluation of CBI, conven-
devices to output node 240, capacitances associated with 20 tional T-coil network design techniques incorporate physical
ESD devices 215 and 220, and the like. CL 245, along with capacitor CBL, which would be coupled to input/output node
various parasitic inductances and capacitances associated 235 and node 298. Such techniques seek to reduce CL 245 to
with the IC and IC packaging, can create a complex imped- an allowable value that the source which generates the input/
ance to a source providing the high frequency input/output output signal can adequately drive. Other considerations that
signal to input/output device 205. 25 influence CL 245 include, for example, the amount of ESD
CB1265 represents an inter-winding capacitance associated protection desired and a maximum tolerable loss of band-
with inductors L 250 and L 255. As used within this specifi- width at the input/output node of the IC. Thus, the process
cation, "inter-winding capacitance" refers to a parasitic starts with less than ideal assumptions. The values of L 250
capacitance caused by capacitive coupling between closely and L 255 are calculated as a function of CL 245. The value of
spaced windings of an inductor. Inter-winding capacitance 30 k, which is the mutual inductance between L 250 and L 255,
increases as the width of the windings of an inductor is is set to 0.5±0.1. CBI 265 then is extracted using an electro-
increased. Correspondingly, inter-winding capacitance magnetic (EM) simulation tool with L 250 and L 255 set to the
decreases as the width of the windings is decreased. Thus, the previously calculated values. Using the relationship Cf=Car+
value of CBI 265 increases as the width of the windings of CBL, CBL can be increased until CB=CLl12 to maximizeband-
each of L 250 and L 255 increases. The value of CBI 265 35 width.
decreases as the width of the windings of each of L 250 and L Conventional T-coil network design techniques, as
255 is decreased. Since the values of L 250 and L 255 are described above, do not account for loop back capacitance
matched, the value of CBI 265 can be said to increase, or created by CTM 270 and CPD 275, which are modeled in FIG.
decrease as the case may be, according to the width of one or 2. The exclusion or absence of CTM 270 and CPD 275 from
both of L 250 and L 255. conventional T-coil network design techniques results in an
It should be appreciated that while the width of the wind- 40 inaccurate impedance matching of the T-coil network to the
ings ofthe inductors is listed as one parameter ofthe inductors source which generates the input/output signal. Within con-
and T-coil network to be modified, other parameters relating ventional T-coil network design techniques, bridge capaci-
to routing of the inductors can be modified as well to effect a tance CB is, therefore, defined as CB=CBI+CBL. Conventional
change in the inter-winding capacitance CBI 265 of inductors T-coil network design techniques further determine values of
L250 and L255. For example, the spacing, e.g., distance, 45 L 250 and L 255, as well parameters of L 250 and L 255,
between windings of inductors L250 and 255 can be varied. In according to the value of CL 245. To achieve the condition
another example, a grounded metal shield can be placed where CB=CL/l2 to maximize bandwidth of the input/output
beneath the T-coil. Aspects of the shield can be further varied node of the IC, the physical capacitor CBL typically is
to influence the inter-winding capacitance CBI. included as described.
CTM 270 can represent various capacitances associated 50 In accordance with the inventive arrangements disclosed
with termination resistor RTM 260. For example, CTM 270 can within this specification, CB and CL/12 can be compared to
represent parasitic capacitances created by capacitive cou- then design the inductors. Loopback capacitances CPD 275
pling between a polysilicon layer used to implement RTM 260 and CTM 270 are modeled and included in the design tech-
on an underlying substrate layer of the IC. CPD 275 can nique. CTM 270 and CPD 275 can be determined via a calcu-
represent various capacitances associated with input/output 55 lation based on silicon data, a two or three-dimensional EM
pad 210. For example, CPD 275 can represent parasitic simulation extracted from layout databases, or any other
capacitances created by capacitive coupling between the method of deriving the parasitic capacitance associated with
metal layers used to implement input/output pad 210 and the RTM 260 and input/output pad 210. Using such techniques, an
underlying substrate layer of the IC. initial estimate of CBI 265 for inductors L 250 and L 255 can
Parasitic capacitances CB1265, CTM 270, and CPD 275 can be made. For example, CBI 265 can be initially estimated
collectively be referred to as a bridge capacitance of T-coil 60 using a value for inductors L 250 and L 255 that provides
network 225. In one embodiment, the bridge capacitance, desired bandwidth for the input/output node to the IC. Further
denoted as CB, generally can be determined by taking CPD details regarding the design of a T-coil network, in accor-
275 and CTM 270 in series with the resulting quantity in dance with one or more embodiments disclosed herein, is
parallel with CB1265. This relationship can be rewritten in the provided with reference to FIG. 3.
form CB=[(CTM*CPD)l(CTM+CPD)]+CBI. For purposes of 65 FIG. 3 is a flow chart illustrating a method 300 of designing
clarity, the reference numbers of FIG. 2 have been excluded a T-coil network for use within an IC in accordance with
from the rewritten equation. another embodiment of the present invention. Method 300
 US 8,181,140 B2
iA 8
can be implemented using a system as described with refer- L are used, one or more other parameters of the inductors in
ence to FIG. 1. In general, method 300 describes a method of the physical model of the T-coil network can be modified
T-coil network design for increasing bandwidth and ESD and/or updated by the system, e.g., automatically, or in
performance at an IC input/output node. In doing so, method response to a user input/output specifying such updated
300 utilizes the circuit design modeled and described with 5 parameters, to provide the target values of L calculated in step
reference to FIG. 2. 330. In step 340, the system can determine an updated value
Beginning in step 305, the system can determine values for of CB, denoted as CB2. CB2 can be determined according to the
the parasitic capacitance of the termination resistor CTM the previously noted expression where CBZ [(CTM*CPD)l(CTM+
parasitic capacitance of the pad of the input/output node CPD, CPD)]+CBI, wherein CBI2 is used in place of CBI.
and the load capacitance CL. This information can be 10 In step 345, the system can compare the most recent value
obtained from a database, for example, given that the charac- of CB, e.g., CB2, with a load capacitance metric. In one
teristics of the pad, the T-coil resistor, and the capacitance of embodiment, the load capacitance metric can be defined as
the input/output device are known. The values, for instance, CL/12. Accordingly, the most recent value of CB, e.g., CB2,
can be determined, or will have been determined, from prior can be compared with CL/12 to determine whether CB is less
simulations or the measured characteristics of prior imple- 15 than the load capacitance metric. When the value of CB is less
mented ICs using a same manufacturing process. than the value of CL/12, method 300 can continue to step 350.
In step 310, the system can estimate a value of L, referring In step 350, one or more parameters of the inductors can be
to each of the inductors of the T-coil network. Initially, the adjusted. For example, as noted, the windings of the inductors
value of L can be estimated based upon a variety of factors within the T-coil network, as specified in the physical layout
such as the desired bandwidth of the input/output of the IC, a of the circuit design, can be adjusted to change the value of
20
selected amount of ESD protection in terms of the number CB. More particularly, the width of the windings of the induc-
and type of ESD devices used, etc. In step 315, a physical tors of the T-coil network can be increased. Increasing the
description of the inductors can be generated. The physical width of the windings of the inductors of the T-coil network
description of the inductors can be modeled as described with increases the inter-winding capacitance CBI, which therefore
reference to FIG. 2 and include a physical model of each of increases the value of CB. Increasing the width of the wind-
the various parameters of the inductors. The physical descrip- 25 ings of the inductors of the T-coil network also decreases the
tion of the inductors can be determined using the value of L series resistance through the inductors L, which increases
determined in step 310. For example, given initial values of L ESD performance of the T-coil network. Thus, after step 350,
determined in step 310, the system can automatically gener- method 300 can loop back to step 335 to continue processing.
ate a physical description of the inductors that is expected to When the value of CB is greater than or equal to the value of
provide the initial value of L determined in step 310 using an 30 the load capacitance metric, in this case CL/12, method 300
EM simulator to perform an EM simulation. The physical can proceed to step 355. It should be appreciated that when
description generated can, for example, specify values the value of CL divided by 12, e.g., the load capacitance
including, but not limited to, number of windings of each metric, is equal to CB2, the bandwidth of an input/output node
inductor, initial width of the windings, a value of k, and the utilizing the T-coil network specified by the circuit design is
like. These parameters can be determined based upon the 35 maximized. More particularly, the bandwidth of the flat time
initially determined value of inductance L. delay response is maximized.
In step 320, the system can determine an initial value of the In step 355, the system can determine whether the value of
inter-winding capacitance CBI. The initial value of CBI, the load capacitance metric CL/12 is equal to the value of CB .
denoted as CBII, can be determined according to the circuit When the value of CL/12 is equal to the value of CB, method
design of the T-coil network described in step 315 where the 300 can continue to step 365 as bandwidth of the flat time
40
estimated values of L from step 310 are inserted into the delay response has been maximized. Maximizing flat time
circuit design specifying a physical layout of the T-coil net- delay response effectively minimizes distortion of the
work as described with reference to FIG. 2. In one embodi- received digital signal. When the value of CL/12 is not equal
ment, the initial value of CBI, denoted as CBLI, can be deter- to the value of CB, e.g., when the value of CB is greater than
mined by the EM simulator and extracted from an EM the value of CL/12, method 300 can proceed to step 360. In
simulation. The EM simulation can be performed by the 45 step 360, the amount of ESD protection provided to the input/
system or another electronic automation design tool and then output node of the IC can be increased. The circuit design
provided to the system. In one aspect, the EM simulation specifying the physical layout of the T-coil network can be
described with reference to steps 315 and 320 canbe one, e.g., updated to include increased ESD protection. For example, a
a single, EM simulation from which the physical parameters number of ESD devices can be increased or a size of the ESD
of the inductors and the initial value of CBI are determined. 50 devices at the output of the T-coil network can be increased.
In step 325, the system can determine an initial value of CB, Increasing the amount of ESD protection as described
denoted as CB1, using the inter-winding capacitance CBI increases the parasitic capacitance CL. Method 300 can iterate
determined in step 320. As noted with reference to FIG. 2, so that CL, continues to increase until of CL/12 is equal, or
CB=[(CTM*CpD)l(CTm+CpD)]+CBI. In step 330, the system approximately equal within some predetermined tolerance or
can calculate the target value of L for the inductors of the 55
range, of the value of CB as determined in step 355.
T-coil network using the value of CBl determined in step 325. In step 365, a circuit design can be output. The circuit

_*
The target value of L can be determined using the expression
L=4*(Cm RTM 2), where Cm represents the greater of the
value of either CB or CL/12. In this example, CB can be
design can specify the physical layout of the T-coil network,
and thus, parameters including, but not limited to, values for
the inductors, width of the windings of the inductors, the load
replaced with CB1. The value of CL can be the value deter- capacitance, the parasitic bridge capacitance, the amount of
mined in step 305. 60 ESD protection, and the like.
Using the target value for L calculated in step 330, the One or more embodiments disclosed within this specifica-
system can determine an updated value of CBI denoted as tion relate to the design of a T-coil network for use with
CBI1, in step 335. In one embodiment, the value of CBI2 can be input/output nodes of an IC. The one or more embodiments
calculated using a three dimensional EM simulator operating provide a more accurate model and process for determining
upon the circuit design specifying the physical layout of the 65 the bridge capacitance of the T-coil network. The T-coil net-
T-coil network that incorporates the values of L determined in work design processes disclosed herein are iterative in nature
step 330. It should be appreciated that as the target values of and seek to maximize bandwidth of the T-coil network by
 US 8,181,140 B2
10
varying loop width of the inductors of the T-coil network servlet, a source code, an object code, a shared library/dy-
and/or increasing the ESD protection provided to the input/ namic load library and/or other sequence of instructions
output node of the IC. The one or more embodiments dis- designed for execution on a computer system.
closed herein do not require the inclusion of a physical The terms "a" and "an," as used herein, are defined as one
capacitor CBi to maximize bandwidth as do conventional 5 or more than one. The term "plurality," as used herein, is
T-coil network design techniques. defined as two or more than two. The term "another," as used
Further, the one or more embodiments disclosed within herein, is defined as at least a second or more. The terms
this specification can be used as part of, or within, a design/ "including" and/or "having," as used herein, are defined as
optimization practice or technique to provide guidance to comprising, i.e., open language. The term "coupled," as used
maximize performance of a T-coil network. One or more io herein, is defined as connected, whether directly without any
steps can be performed manually and provided to the system intervening elements or indirectly with one or more interven-
as input/outputs. For example, in lieu of using simulations, a ing elements, unless otherwise indicated. Two elements also
circuit designer may fabricate test ICs from which values of can be coupled mechanically, electrically, or communica-
parasitic capacitance and/or other parameters of the T-coil tively linked through a communication channel, pathway,
network may be determined. The circuit designer may con- 15 network, or system.
tinue to optimize the inductors and/or T-coil network through One or more embodiments disclosed herein can be embod-
multiple iterations of adjusting values as described within this ied in other forms without departing from the spirit or essen-
specification and creating further test ICs in lieu of simula- tial attributes thereof. Accordingly, reference should be made
tions. to the following claims, rather than to the foregoing specifi-
The flowchart in the figures illustrates the architecture, cation, as indicating the scope of the embodiments of the
functionality, and operation of possible implementations of 20 present invention.
systems, methods and computer program products according
to one or more embodiments of the present invention. In this What is claimed is:
regard, each block in the flowchart may represent a module, 1. A method of generating a circuit design comprising a
segment, or portion of code, which comprises one or more T-coil network, the method comprising:
portions of executable program code that implements the 25 determining inductance for inductors and a parasitic bridge
specified logical function(s). capacitance of the T-coil network;
It should be noted that, in some alternative implementa- comparing the parasitic bridge capacitance with a load
tions, the functions noted in the blocks may occur out of the capacitance metric that depends upon parasitic capaci-
order noted in the figures. For example, two blocks shown in tance of a load coupled to an output of the T-coil net-
succession may, in fact, be executed substantially concur- 30 work;
rently, or the blocks may sometimes be executed in the reverse selectively adjusting, by a processor, an amount of electro-
order, depending upon the functionality involved. It also static discharge protection of the circuit design that is
should be noted that each block of the flowchart illustrations, coupled to the output of the T-coil network or a param-
and combinations of blocks in the flowchart illustrations, can eter of the inductors of the T-coil network according to
be implemented by special purpose hardware-based systems 35 the comparing of the parasitic bridge capacitance with
that perform the specified functions or acts, or combinations the load capacitance metric; and
of special purpose hardware and executable instructions. outputting the circuit design, wherein the circuit design
One or more embodiments of the present invention can be comprises inductance of the inductors, the amount of
realized in hardware or a combination of hardware and soft- electrostatic discharge protection, and a width of wind-
ware. The one or more embodiments can be realized in a ings of the inductors.
centralized fashion in one system or in a distributed fashion 40 2. The method of claim 1, wherein selectively adjusting
where different elements are spread across several intercon- comprises adjusting a ratio of the parasitic bridge capacitance
nected systems. Any kind of data processing system or other with the load capacitance metric without including a physical
apparatus adapted for carrying out the methods described capacitor at an input node of the T-coil network.
herein is suited. 3. The method of claim 1, wherein determining the para-
One or more embodiments of the present invention further 45 sitic bridge capacitance comprises determining the parasitic
can be embedded in a device such as a computer program bridge capacitance according to a parasitic capacitance of a
product, which comprises all the features enabling the imple- termination resistor within the T-coil network denoted as
mentation of the methods described herein. The device can CTM a parasitic capacitance of an input/output pad coupled to
include a data storage medium, e.g., a computer-usable or an input of the T-coil network denoted as CPD, and an inter-
computer-readable medium, storing program code that, when 50 winding capacitance of the inductors denoted as CBI.
loaded and executed in a system comprising memory and a 4. The method of claim 3, further comprising calculating
processor, causes the system to perform the functions the parasitic bridge capacitance according to CB
described herein. Examples of data storage media can [(CTM*CPD)l(CTM+CPD)]+CBI, wherein the parasitic bridge
include, but are not limited to, optical media, magnetic media, capacitance is denoted as CB.
magneto-optical media, computer memory such as random 55 5. The method of claim 1, wherein selectively adjusting
access memory or hard disk(s), or the like. comprises, when the bridge capacitance is less than the load
The terms "computer program," "software," "application," capacitance metric, increasing the width of windings of the
"computer-usable program code," "program code," "execut- inductors.
able code," variants and/or combinations thereof, in the 6. The method of claim 1, wherein selectively adjusting
present context, mean any expression, in any language, code comprises, when the bridge capacitance exceeds the load
or notation, of a set of instructions intended to cause a system 60 capacitance metric, increasing the amount of electrostatic
having an information processing capability to perform a discharge protection.
particular function either directly or after either or both of the 7. The method of claim 1, wherein determining inductance
following: a) conversion to another language, code or nota- for inductors and a parasitic bridge capacitance of the T-coil
tion; b) reproduction in a different material form. For network comprises:
example, program code can include, but is not limited to, a 65 determining initial values of parasitic capacitance of a
subroutine, a function, a procedure, an object method, an termination resistor within the T-coil network denoted as
object implementation, an executable application, an applet, a CTM a parasitic capacitance of an input/output pad
 US 8,181,140 B2
11 12
coupled to an input of the T-coil network denoted as parasitic bridge capacitance according to CB[(CTM*CPD)l
CPS), and the parasitic capacitance of the load; (CTM+CPS)]+CBI, wherein the parasitic bridge capacitance is
estimating initial values for the inductors; denoted as CB .
determining an initial value of inter-winding capacitance 14. The system of claim 10, wherein selectively adjusting
of the inductors denoted as CBI according to the initial 5 comprises, when the bridge capacitance is less than the load
capacitance metric, increasing the width of windings of the
values for the inductors; and inductors.
determining an initial value of parasitic bridge capacitance, 15. The system of claim 10, wherein selectively adjusting
denoted as CB, wherein the parasitic bridge capacitance comprises, when the bridge capacitance exceeds the load
depends upon each of CTM CPS), and CBI. capacitance metric, increasing the amount of electrostatic
8. The method of claim 7, further comprising: 10 discharge protection.
calculating updated values for the inductors using the ini- 16. A non-transitory medium usable by a system compris-
tial value of parasitic bridge capacitance; ing a processor and a memory, wherein the non-transitory
using the updated values for the inductors, determining an medium stores program code that, when executed by the
updated value of inter-winding capacitance of the induc- system, causes the system to perform executable operations
tors; and 15 comprising:
calculating an updated value of parasitic bridge capaci- determining inductance for inductors and a parasitic bridge
tance according to the updated value of inter-winding capacitance of the T-coil network;
capacitance. comparing the parasitic bridge capacitance with a load
9. The method of claim 1, further comprising selecting the capacitance metric that depends upon parasitic capaci-
20 tance of a load coupled to an output of the T-coil net-
load capacitance metric to be one twelfth of the parasitic
work;
capacitance of the load.
selectively adjusting an amount of electrostatic discharge
10. A system for generating a circuit design comprising a
protection of the circuit design that is coupled to the
T-coil network, the system comprising:
output of the T-coil network or a parameter of the induc-
a memory storing program code; and
tors of the T-coil network according to the comparing of
a processor coupled to the memory that, upon executing the
25 the parasitic bridge capacitance with the load capaci-
program code, is configured to perform a plurality of
tance metric; and
steps comprising:
outputting the circuit design, wherein the circuit design
determining inductance for inductors and a parasitic bridge
comprises inductance of the inductors, the amount of
capacitance of the T-coil network;
electrostatic discharge protection, and a width of wind-
comparing the parasitic bridge capacitance with a load
30 ings of the inductors.
capacitance metric that depends upon parasitic capaci-
17. The medium of claim 16, wherein selectively adjusting
tance of a load coupled to an output of the T-coil net-
comprises adjusting a ratio of the parasitic bridge capacitance
work;
with the load capacitance metric without including a physical
selectively adjusting an amount of electrostatic discharge
capacitor at an input node of the T-coil network.
protection of the circuit design that is coupled to the
35 18. The medium of claim 16, wherein determining the
output of the T-coil network or a parameter of the induc-
parasitic bridge capacitance comprises determining the para-
tors of the T-coil network according to the comparing of
sitic bridge capacitance according to a parasitic capacitance
the parasitic bridge capacitance with the load capaci-
of a termination resistor within the T-coil network denoted as
tance metric; and
CTM a parasitic capacitance of an input/output pad coupled to
outputting the circuit design, wherein the circuit design
an input of the T-coil network denoted as CPS, and an inter-
comprises inductance of the inductors, the amount of 40
winding capacitance of the inductors denoted as CBI.
electrostatic discharge protection, and a width of wind-
19. The medium of claim 18, further causing the system to
ings of the inductors.
perform an executable operation comprising calculating the
11. The system of claim 10, wherein selectively adjusting
parasitic bridge capacitance according to C,—[(CTM*CPD)l
comprises adjusting a ratio of the parasitic bridge capacitance
(CTM+CPD)]+CBI, wherein the parasitic bridge capacitance is
with the load capacitance metric without including a physical
45 denoted as CB .
capacitor at an input node of the T-coil network.
20. The medium of claim 16, wherein selectively adjusting
12. The system of claim 10, wherein determining the para-
comprises:
sitic bridge capacitance comprises determining the parasitic
when the bridge capacitance is less than the load capaci-
bridge capacitance according to a parasitic capacitance of a
tance metric, increasing the width of windings of the
termination resistor within the T-coil network denoted as
inductors; and
CTM a parasitic capacitance of an input/output pad coupled to so
when the bridge capacitance exceeds the load capacitance
an input of the T-coil network denoted as CPS, and an inter-
metric, increasing the amount of electrostatic discharge
winding capacitance of the inductors denoted as CBI.
protection.
13. The system of claim 12, wherein the processor is con-
figured to further peform the step comprising calculating the