Power Harvester Design for Semi-Passive UHF RFID Tag Using a Tunable Impedance Transformation

Jaturong Wilas, Kamon Jirasereeamornkul and Pinit Kumhom

Department of Electronic and Communication Engineering King Mongkuts University of Technology Thonburi, 10140, Thailand E-mail: jwk_yumi@hotmail.com, kamon.jir@kmutt.ac.th, pinit.kum@kmutt.ac.th
Abstract This paper proposes a design of a power harvester for a semi-passive RFID Tag. A tunable impedance transformation circuit is inserted between the antenna and the rectifier unit to maximize the power delivered to the rectifier of a tag and minimize reflections from the antenna input port. A power harvester for the UHF band of 950 MHz has been designed based on a 0.35 m CMOS technology. This impedance matching is designed to maximize efficiency by characterizing both the tunable impedance transformation circuit and the conventional rectifier circuit. The antenna is modeled as an RF source with series impedance ZS of 50 while the rectifier is modeled an impedance ZL, which is approximated from the process and design parameters of the NMOS transistors used in the conventional NMOS rectifier. These two impedances are used to find optimal matching parameters of the chosen lowpass LL matching circuit. The simulation results show that the required voltage for a 1.2V secondary battery can be achieved with the tunable impedance matching circuit and conventional 2-stage rectifier. The DC output of the rectifier yields the maximum DC voltage of 1.77V, the maximum average current of 4.72A, and the power conversion efficiency of 15.85% for the input RF power of -14.47dBm at the battery voltage of 1.2V.

I.

INTRODUCTION

Radio frequency identification (RFID) technology has been increasingly applied in many areas such as manufacturing, asset tracking, and public transportation. RFID tags can be classified into three types including passive tags, semi passive tags, and active tags. In case of passive tags, the power for transmitting a response to the reader is induced from the RF signals sent from the reader. Hence, low-power operation is required for the passive tag, and it can be applied only in short range. In contrary, the active tags use the power from a battery for both the transmission and other active components such as ICs so that distance between the reader and a tag is long, and information besides the tag identification (tag ID) can be transmitted from the tag. However, the active tag has several disadvantages such as finite battery life, large volume, and high cost [1], [2]. The semi passive tags can send more data similar to the active tag while having smaller size. They contain a smaller battery that powers their ICs while relying on induced power for data transmission. Therefore, the semipassive tags are attractive especially if we can harvest the RF power effectively. One of the key elements of the power harvester for RFID tag in the CMOS process is the efficiency.

The power harvester circuit consists of multiple rectifier cells in a stage configuration that accumulates the output DC voltage of each stage to build the supply DC voltages. A popular circuit to implement the power harvester is a charge pump circuit. However, if using conventional diodes, turn-on voltage of a diode is still large comparing to the RF signal voltage. Therefore, several papers [4], [5] used Schottky diodes in the rectifiers because they have a small junction resistor and low forward voltage of 200-300 mV at 7A, which are good for a small input RF signal. Later, a gatedrain-connected NMOS is used as the diodes such as the conventional NMOS rectifier proposed in [3]. However, the high threshold voltage caused the reduction of the efficiency. Later, T. Umeda et al. proposed to use VBTH distributors for the switched of external-VTH-cancellation (EVC) techniques for NMOS type rectifier [2]. The integrated rectifier with recharge battery for the 950-MHz RF was proposed in order to achieve high sensitivity CMOS rectifier with a secondary battery for sensor network systems and a low-power wireless transmission system. Also, in [6], the internal-VTHcancellation (IVC) circuit composed of high dielectric constant ferroelectric capacitor properties and current mirror bias circuit had been utilized in a passive tag. Based on the idea of the internal-VTH-cancellation, a conventional CMOS rectifier circuit consisting diode-connected n-channel and pchannel MOS transistors with self-VTH-cancellation (SVC) was applied to improve the efficiency aspects of the system [7]. In passive tags, an impedance transformation had been investigated in order to boost the input RF signal [5], [8]. The added matching network can improve efficiency, sensitivity and discrete components of a circuit for passive tag. One of the design issues is the tradeoff between the minimum return loss and maximum sensitivity of operation at UHF frequency. Based on the idea of using a matching circuit to maximize the power transfer to a given rectifier, this paper proposes to use a lowpass LL matching circuit to deliver maximal power to the input of the conventional NMOS rectifier circuit. The proposed circuit help reduce the number of rectifier stages so that the overall efficiency can be improved. The remainder of the paper organized as follows. The overview of a power harvester in a tag is provided in the next section. Then, the proposed design is described in section III. Finally, the simulation results are discussed before the conclusion.

978-1-4244-4522-6/09/$25.00 2009 IEEE

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II.

SYSTEM OVERVIEW

The proposed power harvester for semi-passive tag is targeted for 950 MHz RF signal. Figure 1 shows the block diagrams of such a tag which consists of a dipole antenna, a matching network, a rectifier, a receiver (Rx), a transmitter (Tx), signal processor, and a secondary battery. In a semipassive tag, the power is mainly drawn from the RF signal although a secondary battery is required for keeping the signal processor running. The rectifier is the key for converting sinusoidal RF signal to DC voltage which is multiplied to the level that can charged into the battery by having multiple rectifier stages. The matching network, which is the main focus of the proposed design, can help increasing the voltage level of the RF signal so that less rectifier stages are needed.

consider the design of tunable impedance but rather concentrate on the second problem. The goal for designing the tunable lowpass LL matching network is to provide maximum power transfer at 950 MHz. In this design, the antenna is modeled as an RF source with series impedance ZS. On the output side of the matching circuit, the input impedance of the rectifier is considered as the impedance ZL. The lossless network with purely reactive components is achieved by setting the complex output impedance of the network ZOUT to be equal to the complex conjugate of the load impedance ZL and the input impedance of the network ZIN to be equal to the complex conjugate of the source impedance ZS:
OUT L IN S

(1) (2)

To obtain (1) and (2), we ignore the series resistance of the inductors and the capacitors [10]. This results as the following equations. IN L OUT S S
VL

L
VS

Fig.1. Block diagram of semi-passive RFID tag with secondary-battery.

The L/C Matching Network Design Tool [11] is used for the calculation of all components given that the ZS and ZL are known. For our case, the ZS is considered to be a purely resistive of 50 and we use the rectifiers effective input resistance, which varies according input voltage level, and load current, as the ZL. We illustrate how we estimate the input resistance of the chosen rectifier circuit in the subsection C, and an example of the design procedure is illustrated in the subsection D.

VS

S
VL

(3) (4)

Fig.2. A Lowpass LL matching network with the tunable impedance transformation network.

III. A.

PROPOSED CIRCUIT DESIGN

Tunable Impedance Transformation Circuit The main problems of adding a matching circuit in a power harvester are that (1) it is hard to control the impedance to a specific value, and (2) the matching impedance changes because of both the load and RF input changes. The first problem can be alleviated by using tunable impedance so that the desired impedance can be tuned later. In this paper, a tunable lowpass LL matching network, shown in Figure 2, is chosen as the matching network. The difficult part of the matching circuit is that it is very difficult to design the exact value of the inductors and capacitors. Since tunable variable capacitors are easier to obtain than those of inductors, we will assume that the two capacitors are tunable to compensate the drifts of the inductance values [9]. However, we will not

Fig.3. Two stages of conventional NMOS-type rectifier circuit.

B.

Rectifier Circuit We adopt the conventional NMOS rectifier circuit proposed in [3] to illustrate the results of adding the matching circuit designed in the previous subsection. Figure 3 shows two-stage rectifier circuit used in this paper. The rectifier NMOS transistors are connected as a self-bias by connecting its gate (G) and drain (D) terminals. If the input RF signal

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voltage is higher than the threshold of an NMOS, it will turn on. The topology in Fig. 3 works as a full bridge rectifier, in which the DC output storing in the output capacitor is doubled in each stage. Since the input voltage from the matching circuit is higher than those without it, only two stages of the rectifier circuit is enough for boosting the DC output to a usable level. The relation between the input RF voltage and output voltage of the rectifier is as follows. The voltage level at terminal X2 is raised to 4VRF-VGS by assuming CS1 and CS2 are much larger than C1 and C2 respectively. The rectification output voltage VOUT is computed from VOUT=4(VRF-VTH), (5)

shown in Fig. 4. A diode-connected NMOS is in saturation region when VGS, which is equal to VDS, is greater than VTH; otherwise, it is cutoff. Therefore, in the negative half of the signal, the transistor M1 is in the saturation region, and the transistor M2 is cutoff as shown in Fig. 4(a). The opposite is true for the positive half of the signal as shown in Fig. 4(b). Ignoring the parasitic capacitances, we can model an NMOS as a current source with a parallel resistor, RO, as shown in Fig. 5. The resistance value of RO depends on the drain current at saturation point, denoted as ID, SAT, and the channel length modulation, denoted as, following (7). O
D,SAT

(7)

where VTH is the threshold voltage of M2, M4. For our estimation, we assume that VTH is 0V, Hence, the maximum output voltage VOUT can be approximated as VOUT4VRF (6)

The DC load of the rectifier circuit is a battery whose voltage is considered to vary between 0.4 to 1.2 volts. This results in the variation of the effective input impedance, which we consider as the ZL of the matching circuit in the previous subsection. The input impedance of the rectifier circuit is analyzed in the next subsection.

We measure the resistance RO by simulating a typical SPICE model of the TSMC 0.35u process. In this measurement, VGS is set to a specific value above the threshold voltage, then sweep VDS, and plot ID to get the VI curve at the given VGS. The resistance RO is the inverse of the slope of the VI curve in the saturation region. Since this resistance varies according to VGS, which is the input voltage level of the rectifier, we use the average value of the measured RO in the range above VTH of the NMOS. Finally, since we use two stages rectifier, the approximated resistance is the impedance of two RO in parallel, which is RO/2. We use this value as the ZL of the matching circuit, and apply the L/C Matching Network Design Tool to find the parameters of the matching circuit. Configuration of the Proposed Circuit To illustrate the design of the proposed matching circuit, we approximate the impedance of the conventional NMOS rectifier using NMOS of the TSMC 0.35m mixed-signal process. The SPICE model is used in simulation to find the resistance RO. The resulting RO is 3.07 k which gives ZL of 1535. This value is used together with ZS of 50 to find the matching circuit parameters, LS, LL, CVS and CVL, using the L/C Matching Network Design Tool. The parameters of the designed matching circuit are as follows: LS = 17.85 nH LL = 98.99 nH CVS = 1.29 pF CVL = 0.23 pF D.

(a)

(b)

Fig.4. (a) Diode connected NMOS for negative phase. (b) Diode connected NMOS for positive phase.

Obviously, the chosen circuit will not give the optimal matching for all cases. However, this matching is still give a considerable higher output voltage level comparing to the one without a matching circuit. IV. SIMULATION RESULTS AND DISCUSSIONS
Fig.5. Diode connected NMOS model.

Approximation of the Rectifier Input Impedance At 950 MHz, we can model each stage of the rectifier as two NMOS transistors in parallel, of which one is in the saturation region and the other is in the cutoff region, as

C.

To evaluate the proposed design, SPICE simulations using the free LT SPICE of the Linear Technology Corporation are carried out using the proposed circuit, shown in Fig. 6. The circuit consists of the sinusoidal signal generator as the RF input, a proposed tunable impedance matching circuit with the parameters designed in the previous section, the conventional 2-stage rectifier circuit, and a model of a secondary battery circuit. The RF input is set to 950MHz with power between

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-16dBm to 0dBm, and RS of 50 . The TSMC 0.35m CMOS model is applied in this simulation. All NMOS transistors are designed with W and L of 40m and 0.4m respectively.

B.

Effect of RF Input Power This simulation is performed to see the effect of the RF input power to the overall efficiency. The power efficiency is measured using (8). %
OUT IN

where PIN and POUT are the power of input and output of rectifier, VOUT and IOUT are the rectifiers DC output voltage and current, respectively. Figure 8 shows the efficiency of the proposed power harvester at various RF input power and the battery voltage at 1.2V. The results are compared with the efficiencies of the previous power harvesters including, (1) EVC NMOS rectifier proposed in [3], (2) the conventional CMOS rectifier and (3) the SVC CMOS rectifier from [7], and (4) the IVC CMOS rectifier proposed in [6].
Fig.6. Proposed circuit for simulation.
45 40
No. matching Optimal matching Average matching

OUT OUT IN

% ,

(8)

Power Conversion Efficiency [%]

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.5

35 30 25 20 15 10 5 0 -16

Proposed Design @ -14dBm input power Vbat = 1.2V @ 15.85% Max.Vout =1.77V @ 23.44% SVC CMOS Rectifier IVC CMOS Rectifier

Output Voltage [Vrms]

EVC NMOS Rectifier -14 -12 Conven.CMOS Rectifier -10 -8 -6 -4 RF Input Power [dBm] -2 0

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Resistance Load [k] Fig.7.Voltage output for various resistance load.

Fig.8 Power conversion efficiency for various RF input power.

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Effect of ZL to Tuning Circuit The first simulation is performed to see the effect of the load change to the output voltage of the matching circuit. We set the RF input at -14dBm, vary ZL of the matching circuit from 0.5k to 5k, and measure the output voltage level. We compare the voltage level over ZL of (1) no matching circuit, (2) optimal matching circuit in which optimal parameters for a specific ZL is used, and (3) the proposed matching circuit using parameters based on the average ZL. From Fig. 7, which shows the result from the simulation, the voltage level of the optimal matching circuit shows the best possible voltage levels that can be provided for each load for RF input power at -14dBm. The proposed matching circuit is either equal to or less than the optimal values. The voltage levels of the proposed matching are closest to the optimal values during the load ranging from the 1k to 2.5k, which is closest to the 1535 used in the calculation. However, these values are much better than those without the matching circuit.

Power Conversion Efficiency [%]

A.

Vbat @ 1.2V Vbat @ 1.0V Vbat @ 0.8V Vbat @ 0.6V Vbat @ 0.4V
20 18 16 14 12 10 8 6 4 2 -16 -14 -12 -10

Proposed design

RF Input Power [dBm]

-8

-6

-4

-2

Fig.9 Power conversion efficiency for various battery voltage.

Note that we compare our results with the results from the respective papers, which may have different experimental setup. However, it is a good evaluation that our proposed

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method can improve the efficiency considerably over a wide range of the input RF power level. In addition, we show the efficiency at the DC output before the protection diode to see how much the efficiency is dropped because of the diode. C. Effect of RF Input Power The final simulation shows the effect of the load by varying the battery voltage at 0.4V, 0.6V, 0.8V, 1.0V and 1.2V and finding the efficiency at various RF input power. The result, shown in Fig. 9, indicates the drop of efficiency when the battery voltage is lower. This is because higher current is drawn when the battery voltage is lower; hence, higher loss power. V. CONCLUSIONS

[9] J. H. Sinsky and C. R. Westgate, Design of an Electronically Tunable Microwave Impedance Transformer, in IEEE MTT-S International Microwave Symposium, vol.2, Denver, CO, USA, pp.647-650, Jun 1997. [10] P. Scheele, F. Goelden, A. Giere, S. Mueller, and R. Jakoby, Continuously Tunable Impedance Matching Network Using Ferroelectric Varactors, in IEEE MTT-S Conf, pp.603-606, Jun 2005. [11] J.Wetherell., L/C Matching Network Design Tool [Online], Available: http://www.bwrc.eecs.berkeley.edu/Research/ RF/project /60GHz/matching/ImpMatch.html [12] R. Jacob Baker, CMOS: Circuit Design, Layout and Simulation, 2nd ed. New Jersey: Wiley, 2008. [13] Mosis Service., Wafer Electrical Test Data and SPICE Model Parameters [Online], Available: http://www.mosis.com/ Technical/Testdata/tsmc-035-prm.html

A matching circuit is inserted between an antenna and a conventional NMOS rectifier to improve efficiency of the power harvester for an RFID semi-passive tag, in which a power received from tag readers is harvested for charging to secondary battery. The parameters of the chosen lowpass LL matching network are computed based on estimated value of the rectifiers input resistance. The simulation shows that although it is difficult to obtain optimal matching for all loads, an average matching circuit can improve the efficiency. For the future works, we are in the process of layout the design, and investigate inserting the matching circuit into other kinds of rectifiers. REFERENCES
[1] K. Finkenzeller, RFID Handbook: Fundamentals and Applications in Contactless Smart Cards and Identification, 2nd ed. New York: Wiley, 2003. [2] T. Umeda, H. Yoshida, S. Sekine, Y. Fujita, T. Suzuki, and S. Otaka, A 950-MHz Rectifier Circuit for Sensor Network Tags With 10-m Distance, IEEE J. Solid-State Circuits, vol.41, no.1, pp.35-41, Jan 2006. [3] M. Usami, A. Sato, K. Sameshima, K. Watanabe, H. Yoshigi, R. Imura ,Powder LSI: An ultra small RF identification chip for individual recognition applications, in IEEE ISSCC Dig. Tech. Papers, pp. 398399, Feb. 2003. [4] U. Karthaus and M. Fischer, Fully integrated passive UHF RFID transponder IC with 16.7-W minimum RF input Power, IEEE J. Solid-State Circuits, vol.38, no.10, pp.1602-1608, Oct 2003. [5] T. Yuan, C. Qiu, L. WeiLi, Q. Zhang, and M. Seng Leong, Passive RFID Tag Designed Using Discrete Components, in Proc. ISAP Conf. Japan, pp.616-619, Aug 2007. [6] H. Nakamoto, D. Yamazaki, T. Yamamoto, H. Kurata, S. Yamada, K. Mukaida, T. Ninomiya, T. Ohkawa, S. Masui, and K. Gotoh, A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-m Technology, IEEE J. Solid-State Circuits, vol.42, no.1, pp.101-110, Jan 2007. [7] Koji Kotani and Takashi Ito, High Efficiency CMOS Rectifier Circuit with Selft-Vth-Cancelltion and Power Regulation Function for UHF RFIDs, in IEEE Int. Asian Solid-State Circuits Conf. Korea, pp.119-122, Nov 2007. [8] A. Shameli, A. Safarian, A. Rofougaran, M. Rofougaran, and F. De Flaviis, Power Harvester Design for Passive UHF RFID Tag Using a Voltage Boosting Technique, IEEE Trans. Microw, Theory Tech., vol. 55, no.6, pp.1089-1097, Jun 2007.

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