PAE2248 System-on-Chip Design
UI-SoC Design Issues
L7: On Chip Buses – Clock Distribution
Presented By
Dr. V. Vaithianathan
Associate Professor, ECE Dept
Lesson Plan
Sl. No. of
Lecture
No Hours
L1 Architecture of the SoC 1
L2 Design Issues of SoC 1
Hardware-Software Codesign - Codesign Flow &
L3 2
Codesign Tools
L4 Core Libraries, EDA tools, Web Pointers 1
L5 SoC Design Flow 1
L6 General Guidelines for Design Reuse 1
L7 On Chip Buses – Clock Distribution 1
L8 Physical Design and Deliverable Models 1
Lecture 7
• On chip Buses
• Clock Distribution
Session Objectives
• To understand basic of On chip Buses
• To learn about Clock Distribution
Session Outcomes
• At the end of this lecture, the students will
be able to know about
– On chip Buses
– Clock Distribution
On-Chip Buses
• On-chip buses play an extremely important role in
SoC design.
• Bus-based designs are easy to manage primarily
because on-chip buses provide a common interface
by which various cores can be connected.
• Thus, the design of on-chip buses and the data
transaction protocol must be considered prior to the
core selection process.
• On-chip bus design after the selection and
development of cores leads to conflicting data
transfer mechanisms.
• Subsequently, it causes complications at SoC-level
integration and results in additional hardware as well
as lower performance.
On-Chip Buses
• Because core providers cannot envision all possible
interfaces, parameterized interfaces should be used in
the core design.
• For example, FIFO based interfaces are reasonably
flexible and versatile in their ability to handle varying
data rates between cores and the system buses.
• Several companies and organizations such as VSI
Alliance are actively working to develop an acceptable
on-chip bus and core interface standard/specifications
that support multiple masters, separate identity for
data and control signals, fully synchronous and
multiple cycle transactions, bus request-and-grant
protocol.
Clock Distribution
• Clock distribution rules are one of the most important
rules for cores as well as SoC designs.
• Any mismatch in clocking rules can impact the
performance of an entire SoC design.
• It may even cause timing failures throughout the
design.
• Therefore, establishing robust clock rules is necessary
in SoC design.
• These rules should include clock domain analysis,
style of clock tree, clock buffering, clock skew
analysis, and external timing parameters such as
setup/hold times, output pin timing waveforms, and
so on.
Clock Distribution
• The majority of SoCs consist of multiple clock
domains.
• It is always better to use the smallest number of clock
domains.
• It is better to isolate each clock in an independent domain
and use buffers at the clock boundary.
• If two asynchronous clock domains interact, the
interaction should be limited to a single, small
submodule in the design hierarchy.
• The interface between the clock domains should avoid
metastability and the synchronization method should
be used at the clock boundaries.
• A simple resynchronization method consists of clock
buffering and dual stage flip-flops or FIFOs at the
clock boundary.
Clock Distribution
• When cores contain local PLLs, a low-frequency chip-
level synchronization clock should be distributed with
on-chip buses.
• Each core’s local PLL should lock to this chip-level
synchronization clock and generate required
frequency for the core.
• Control on clock skew is an absolute necessity in SoC
design.
• It avoids data mismatch as well as the use of data
lock-up latches.
• A simple method to minimize clock skew is to edge-
synchronize master and derived clocks.
Clock Distribution
Figure 1.14 Clock distribution schemes for balanced load and minimized
clock skew.
Clock Distribution
• The general practice has been to use a balanced clock
tree that distributes a single clock throughout the
chip to minimize the clock skew.
• Examples of such trees are given in Figure 1.14.
• The basic principle is to use a balanced clock tree and
clock buffer at the beginning of the clock tree so that
any skew at the upper level can be adjusted by
adjusting the buffer delay
Clear/Set/Reset Signals
• It is essential to document all reset schemes in detail
for the entire design.
• The documentation should state
• whether resets are synchronous, asynchronous, or
internal/external power-on-resets,
• how many resets are used, any software reset
schemes used,
• whether any functional block has its locally
generated resets,
• whether resets are synchronized with local clocks,
and so on.
• Whenever possible, synchronous reset should be used
because it avoids race conditions on reset.
Clear/Set/Reset Signals
• Static timing analysis becomes difficult with
asynchronous resets, and the designer must carefully
evaluate the reset pulse width at every flip-flop to
make sure it becomes inactive synchronously to
clocks.
• Hence, whenever reset/clear is asynchronous, their
deactivation should be resynchronized.
Review Questions
1. What are SOC standard buses?
2. Which bus is an arm developed standard bus that
aims to help efficient on-chip processing?
3. What is the purpose of a bus interface or bus
bridge?
4. What is pipelining in shared bus transactions?
5. What is clock distribution in VLSI?
6. Which is the type of clock distribution?
7. What is a clock in transmission?
8. Why is the H tree clock distributed?
Session Summary
• In this lecture, we have discussed about
– On chip Buses
– Clock Distribution
Text Books & References
1. Rochit Rajsuman, “System-on-a-chip: Design and
Test”, Advantest America R & D Centre, 2000.
2. Hubert Kaeslin, “Digital Integrated Circuit Design: From
VLSI Architectures to CMOS Fabrication”, Cambridge
University Press, 2008.
3. B. Al Hashimi, “System on chip-Next generation
electronics”, The IET, 2006.
4. P Mishra and N Dutt, “Processor Description Languages”,
Morgan Kaufmann, 2008.
5. Michael J. Flynn and Wayne Luk, “Computer System
Design: System-on-Chip”, Wiley, 2011.
Thank You
