Question Set:
Question 1
(Choose 1 answer)
Which of the following components was used in the first ENIAC computer?
A. Bipolar transistors
B. Field transistors
C. Vacuum tubes
D. Semiconductor ICs
Question 2
(Choose 1 answer)
Which of the following statements is NOT part of the Von Neumann principle?
A. Computers can operate according to a stored program
B. The computer uses a program counter to indicate the location of the next statement
C. A computer's memory is addressable
D. Each statement must have a memory area containing the address of the next instruction
Question 3
(Choose 2 answers)
Regarding the ALU (Arithmetic Logic Unit), besides basic arithmetic operations, what
operations can it perform?
A. It handles logical operations such as AND, OR, XOR, NOT
B. It handles data transfer operations like MOVE, GO, JUMP
C. It handles decoding operations after an instruction is fetched
D. It handles bit shifting operations like multiplication and division by powers of two
Question 4
(Choose 1 answer)
Consider some computer generations:
1: The first computer generation
2: The second computer generation
3: The third computer generation
And some technologies used in computer generations:
A: Vacuum Tubes
B: Transistors
C: Integrated Circuits (IC)
D: Microprocessors
Select the main technology applied in each computer generation:
A. 1-D; 2-C; 3-B
B. 1-A; 2-C; 3-D
C. 1-A; 2-B; 3-C
D. 1-D; 2-B; 3-C
Question 5
(Choose 1 answer)
What electronic component is used to govern operations such as fetching, decoding, and
performing arithmetic operations executed by a processor?
A. Using a system clock
B. Using a quartz crystal
C. Using an analog-to-digital converter
D. Using a counter
Question 6
(Choose 1 answer)
The pulse rate in the clock system is known as the:
A. Clock cycle
B. Clock speed
C. Clock time
D. Clock tick
Question 7
(Choose 1 answer)
The instruction, which adds 1 to the value in a memory location, has five stages: fetch opcode
(four cycles), fetch operand address (three cycles), fetch operand (three cycles), add 1 to
operand (three cycles), and store operand (three cycles). An interrupt sends a request at the
beginning of the fetch operand stage. How many cycles does the processor take to enter the
interrupt processing cycle?
A. 6
B. 7
C. 8
D. 9
E. 10
Question 8
(Choose 1 answer)
Which representation is most efficient to perform arithmetic operations on signed integer
numbers?
A. Sign-magnitude
B. 2's complement
C. 1's & 2's complement
D. 1's complement
Question 9
(Choose 1 answer)
Interprets the instructions in memory and causes them to be executed.
A. Registers
B. CPU interconnection
C. Arithmetic and Logic Unit (ALU)
D. I/O Modules
E. Control Unit (CU)
Question 10
(Choose 1 answer)
What is the function of the bus system in the computer?
A. Extend the communication function of the computer
B. Connect components in the computer
C. Control peripherals
D. Transform signals in the computer
E. All of the mentioned
Question 11
(Choose 1 answer)
What is the correct order of memory access speed from fastest to slowest?
A. Registers > Cache > RAM > SSD
B. Cache > Registers > RAM > SSD
C. Registers > Cache > SSD > RAM
D. Cache > Registers > SSD > RAM
E. All of the mentioned are wrong
Question 12
(Choose 1 answer)
What is the special feature of Memory Cache?
A. Allows faster access than DRAM memory
B. Memory cache is outboard storage memory
C. Allows faster access than CPU registers
D. Fixed memory - Read Only Memory
E. Has a larger capacity than HDD
Question 13
(Choose 1 answer)
A set-associative cache consists of 64 lines, divided into four-line sets. 2192^{19}-words
main memory contains 4K blocks of 128 words each. How many bits are there in the tag field
of the cache?
A. 5
B. 6
C. 7
D. 8
E. 9
Question 14
(Choose 1 answer)
Which one of the following is invalid about RAM?
A. Both static and dynamic RAMs are volatile; that is, power must be continuously supplied
to the memory to preserve the bit values.
B. A dynamic memory cell is simpler and smaller than a static memory cell.
C. Both static and dynamic RAMs require the supporting refresh circuitry.
D. SRAMs are somewhat faster than DRAMs
Question 15
(Choose 1 answer)
In error-correcting code (single ECC), how many bits are used to correct one bit in 8-bit data?
A. 4
B. 5
C. 6
D. 7
Question 16
(Choose 1 answer)
What is correct about increasing performance and endurance?
A. Hard Disk > DRAM > NAND Flash > SRAM
B. Hard Disk > NAND Flash > DRAM > SRAM
C. NAND Flash > Hard Disk > SRAM > DRAM
D. Hard Disk > DRAM > SRAM > NAND Flash
Question 17
(Choose 1 answer)
With the hard disk data layout, the set of all the tracks in the same relative position on the
platter is called:
A. Cylinder
B. Tracks
C. Inter-track gap
D. Sector
Question 18
(Choose 1 answer)
The speed of data delivery is your main concern when configuring a RAID drive for a Media
Streaming Server. This server has two hard disks installed. What type of RAID should you
install, and what type of data will be stored on Disk 1 and Disk 2?
A. RAID 0 - Disk 1 (Stripe) and Disk 2 (Stripe)
B. RAID 0 - Disk 1 (Mirror) and Disk 2 (Mirror)
C. RAID 1 - Disk 1 (Stripe) and Disk 2 (Stripe)
D. RAID 1 - Disk 1 (Mirror) and Disk 2 (Mirror)
Question 19
(Choose 1 answer)
In terms of performance, what is the main advantage of a solid-state drive over a magnetic
disk?
A. A solid-state drive has faster access time, lower latency, and higher reliability.
B. A solid-state drive has larger capacity, lower power consumption, and lower cost.
C. A solid-state drive has better compatibility, longer lifespan, and higher security.
D. A solid-state drive has none of the mentioned advantages over a magnetic disk.
Question 20
(Choose 1 answer)
Assume that a truth table:
X Y OUTPUT
1 0 1
0 1 1
Which basic operator matches the table above?
A. AND
B. OR
C. NAND
D. NOR
Question 21
(Choose 1 answer)
In isolated I/O:
A. The I/O devices and the memory share the same address space
B. The I/O devices have a separate address space from memory
C. The memory and I/O devices have an associated address space
D. A part of the memory is specifically set aside for the I/O operation
E. None of the mentioned
Question 22
(Choose 1 answer)
What is an interrupt vector?
A. Part of memory which contains the addresses of interrupt handlers
B. A signal an I/O device sends to CPU
C. A signal an I/O software sends to CPU
D. None of the mentioned
Question 23
(Choose 1 answer)
What is the main distinction between Interrupt-Driven I/O and Direct Memory Access
(DMA)?
A. Interrupt-Driven I/O involves the CPU in every data transfer, while DMA bypasses the
CPU and transfers data directly between I/O device and memory
B. Interrupt-Driven I/O requires special hardware and software support, while DMA does not
need any additional components
C. Interrupt-Driven I/O is suitable for small and frequent data transfers, while DMA is
suitable for large and infrequent data transfers
D. All of the mentioned
Question 24
(Choose 1 answer)
What role does an Application Programming Interface (API) play in software development?
A. It allows program access to hardware resources using high-level language libraries
B. It defines low-level machine instructions
C. It provides a standard for binary portability
D. It manages system resources for the operating system and machine language instructions
Question 25
(Choose 1 answer)
Which state indicates that a process is currently being executed by the processor?
A. Running
B. Ready
C. NewBorn
D. Halted
Question 26
(Choose 1 answer)
Which of the following statements is incorrect about Translation Look-aside Buffer (TLB)?
A. The use of TLB eliminates the need for keeping a page table in memory
B. TLB only maintains a subset of the entries stored in the full memory-based page table
C. When there is a TLB miss the system needs to access the page table
D. A translation lookaside buffer (TLB) is a memory cache that stores the recent translations
of virtual memory to physical memory
Question 27
(Choose 1 answer)
How does Boolean algebra contribute to the design of digital circuits?
A. It simplifies the implementation of desired functions
B. It helps in the analysis of economic data
C. It facilitates the design of analog circuits
D. It is primarily used for chemical engineering and physical engineering
Question 28
(Choose 1 answer)
When both inputs are 0, what is the result of a NOR gate?
A. 0
B. 1
C. 2
D. Undefined
E. #NA
Question 29
(Choose 1 answer)
The operation yields true (binary value 1) if and only if both of its operands are true.
A. OR
B. AND
C. XOR
D. NAND
Question 30
(Choose 1 answer)
We have a long-term queue of process requests, typically stored on:
A. main memory
B. disk
C. cache memory
D. registers
Question 31
(Choose 1 answer)
Which registers can be assigned to a variety of functions by the programmer?
A. Data registers
B. General purpose registers
C. Address registers
D. Condition codes (flags)
Question 32
(Choose 1 answer)
The hardware mechanism that allows a device to notify the CPU is called:
A. polling
B. interrupt
C. driver
D. controlling
Question 33
(Choose 1 answer)
What is a branch instruction?
A. The instructions that are used to divide a program into multiple subprograms
B. The instructions that have as one of its operands the address of the next instruction to be
executed
C. The instructions that are used to pause the program
D. The instructions that are used to return to the beginning of the program
Question 34
(Choose 1 answer)
Which of the following statement is correct about addressing modes?
A. They define how the operands of an instruction are specified, including immediate,
register, direct, and indirect addressing modes
B. Addressing modes are irrelevant in computer architecture, and all instructions only operate
on values stored in registers
C. Addressing modes are limited to only immediate and direct modes; register and indirect
addressing modes are not used in modern computer systems
D. All instructions in computer architecture use indirect addressing modes, making it the only
relevant mode for operand specification
Question 35
(Choose 1 answer)
A benchmark program is running on a 400 MHz processor. The executed program consists of
500 instruction executions, with the following instruction mix and clock cycle count in Table
below:
Instruction type: Arithmetic (300 instructions), Data transfer (100 instructions),
Control transfer (100 instructions)
Cycles per instruction: Arithmetic (1), Data transfer (2), Control transfer (2)
Calculate MIPS rate for this case.
A. MIPS rate = 285.7
B. MIPS rate = 275.7
C. MIPS rate = 265.7
D. MIPS rate = 295.7
Question 36
(Choose 1 answer)
In MASM32, which OPCODE is used to compare two values?
A. COM
B. CMP
C. IF... ELSE
D. TEST
Question 37
(Choose 1 answer)
What is the primary purpose of the "Fetch instruction" phase in the operation of a processor?
A. To read an instruction from memory
B. To interpret the instruction
C. To perform arithmetic operations on data
D. To write data to memory
Question 38
(Choose 1 answer)
What is the role of the registers in a processor?
A. Registers in a processor provide fast, temporary storage for data and instructions,
facilitating efficient access during instruction execution
B. Registers are only used to store data temporarily during the execution of a program and do
not contribute to the processing of instructions
C. Registers are solely responsible for storing data from the main memory and have no
involvement in holding instructions or facilitating data manipulation
D. Registers are only necessary when the CPU is idle and have no impact on the speed or
efficiency of instruction execution
Question 39
(Choose 1 answer)
What is the significance of the program counter (PC) in the fetch phase of the instruction
cycle?
A. The program counter (PC) is not used in the fetch phase, and its role is limited to tracking
the number of instructions executed by the CPU
B. The program counter (PC) in the fetch phase holds the memory address of the next
instruction to be fetched and executed
C. The program counter (PC) is responsible for executing instructions and has no specific role
during the fetch phase
D. The program counter (PC) is only relevant in multi-core processors and does not contribute
to the fetch phase of the instruction cycle in single-core systems
Question 40
(Choose 1 answer)
Which of the following statement is correct in the context of Instruction Pipelining?
A. Instruction Pipelining reduces the efficiency of instruction execution by introducing delays
and dependencies between instructions
B. Instruction Pipelining is only effective for specific types of instructions and has no impact
on the overall efficiency of instruction execution
C. Instruction Pipelining enhances efficiency by enabling simultaneous execution of multiple
instructions in different stages, boosting overall throughput
D. Instruction Pipelining improves efficiency by processing multiple instructions
simultaneously, reducing execution time. However, it can face challenges like hazards,
introducing delays and impacting overall performance
Question 41
(Choose 1 answer)
What does CISC stand for?
A. Complex Instruction Set Computer
B. Computer Instruction Set Complex
C. Complex Instruction Summarize Computer
D. Computer Instruction Summarize Complex
Question 42
(Choose 1 answer)
What is one of the advantages of using a register file in computer architecture?
A. Reduction in memory accesses, saving time
B. More efficient use of space due to dynamic adaptation
C. Efficient handling of both local and global variables
D. Easier management of cache residency
Question 43
(Choose 1 answer)
What is the main benefit of using RISC over CISC?
A. RISC has more instructions and addressing modes than CISC
B. RISC has faster instruction execution and simpler instruction decoding than CISC
C. RISC has variable-length instruction formats and direct memory access than CISC
D. RISC has more registers and pipelines than CISC
Question 44
(Choose 1 answer)
In SuperScalar computer architecture, the primary goal of utilizing multiple processors
concurrently is to
A. Increase processing speed by increasing CPU frequency
B. Improve performance by executing more than one instruction per machine cycle
C. Reduce the size of the CPU to conserve energy
D. Enhance computational power by increasing the number of CPU cores
Question 45
(Choose 1 answer)
is (are) determined by the number of instructions that can be fetched and executed at the same
time (the number of parallel pipelines) and by the speed and sophistication of the mechanisms
that the processor uses to find independent instructions.
A. Instruction-level parallelism
B. Machine parallelism
C. Both instruction-level parallelism and machine parallelism
D. None of the mentioned
Question 46
(Choose 1 answer)
"Multiple processors share a single memory or pool of memory by means of a shared bus or
other interconnection mechanism; a distinguishing feature is that the memory access time to
any region of memory is approximately the same for each processor". Which concept does the
statement belong to?
A. Symmetric multiprocessor (SMP)
B. Nonuniform memory access (NUMA)
C. Cluster
D. Single instruction, multiple data (SIMD)
Question 47
(Choose 1 answer)
Which write technique in which all write operations are made to main memory as well as to
the cache, ensuring that main memory is always valid.
A. Write through
B. Write back
C. Write around
D. No write allocate
Question 48
(Choose 1 answer)
How does multithreading improve the performance of a processor?
A. It increases the instruction-level parallelism by issuing multiple instructions from different
threads in the same cycle
B. It increases the thread-level parallelism by executing multiple threads on different cores or
processors
C. It increases the utilization of the processor resources by hiding the latency of long-latency
events such as cache misses or branch mispredictions
D. All of the mentioned
Question 49
(Choose 1 answer)
Follow the Amdahl's law for multiprocessors, if only 10% of the code is inherently serial (f =
0.9), running the program on a multicore system with 4 processors, a performance gain
(speedup factor) would be
A. 307%
B. 297%
C. 317%
D. 327%
Question 50
(Choose 1 answer)
What is the most common mapping technique used in cache memory in modern computers?
A. Direct Mapping
B. Fully Associative
C. Set Associative
D. None of the mentioned
Đáp án
1. C
2. D
3. A, D
4. C
5. A
6. B
7. E
8. B
9. E
10. B
11. A
12. A
13. D
14. C
15. B
16. B
17. A
18. A
19. A
20. B
21. B
22. A
23. A
24. A
25. A
26. A
27. A
28. B
29. B
30. B
31. B
32. B
33. B
34. A
35. A
36. B
37. A
38. A
39. B
40. C
41. A
42. A
43. B
44. B
45. A
46. A
47. A
48. D
49. A
50. C
51. B
